A method for electroplating metal on the back side of a wafer

Abstract

The present invention belongs to the field of semiconductor technology and relates to a method for electroplating metal on the back side of a wafer. The method forms at least two positioning holes through the edge of the wafer, and forms an electroplated metal layer on the back side of the wafer through the positioning holes, so that the groove pattern formed between the electroplated metal layer and the wafer is the same as the pattern of the scribe line on the front side of the wafer, thereby avoiding the use of a double-sided lithography machine, significantly reducing the equipment cost, having a simple process flow, being easy for industrial production, significantly reducing the fragmentation rate, significantly improving the production efficiency, and having broad application prospects.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for electroplating metal on the back side of a wafer. Background Art

[0002] Due to the excellent properties of copper such as good heat dissipation performance, electrical performance, mechanical strength, electromagnetic shielding, etc., it has become a trend to electroplate a thick copper layer on the back side of a chip. For example, to achieve good chip performance, it is necessary to electroplate a 10 - 50μm thick copper layer on the back side of a 20 - 100μm thin wafer, and then perform wafer dicing after completion.

[0003] Although the electroplating thick copper process has been relatively mature, electroplating thick copper on such a thin wafer (20 - 100μm thin wafer) is still quite challenging. For example:

[0004] 1) During the process of thick copper dicing, the blade is prone to breakage, and the chip will also be damaged. If laser dicing is used, a high - precision ultraviolet or blue - light laser needs to be selected, which is costly, and as the thickness increases, the dicing efficiency will also decrease.

[0005] 2) To replicate the pattern on the front side of the wafer to the back side of the wafer, generally double - sided lithography or the method of opening the carrier plate is used. The process is complex, the double - sided lithography equipment is expensive, and stress problems may occur during the etching of the carrier plate. The complex process increases the risk of debris during the process, which is not convenient for mass production.

[0006] Therefore, for the thick copper electroplating process of thin wafers, it is necessary to develop a new production method that is conducive to mass production and has a simpler process. Summary of the Invention

[0007] Aiming at the deficiencies of the existing technology, the purpose of the present invention is to provide a method for electroplating metal on the back side of a wafer. By using the method of positioning holes, the correspondence of the patterns on the front side and the back side of the wafer is realized, thereby avoiding the problems of using double - sided lithography equipment and / or etching carrier plates, and the process flow is simple, the fragment rate is significantly reduced, which is conducive to mass production.

[0008] To achieve this purpose, the present invention adopts the following technical solutions:

[0009] The present invention provides a method for electroplating metal on the back side of a wafer, and the method includes the following steps:

[0010] Form at least two positioning holes at the edge of the wafer, and the positioning holes at least penetrate through the thickness direction of the wafer.

[0011] Form a seed layer on the back side of the wafer to obtain a component with a seed layer.

[0012] Positioning is performed using the positioning holes, and a patterned glue layer is formed on the surface of the seed layer of the seed layer-containing component away from the wafer to obtain a glue layer-containing component.

[0013] Among them, the patterned glue layer partially covers the seed layer, and the pattern formed in the area of the seed layer covered by the patterned glue layer is denoted as the back pattern.

[0014] The front surface of the wafer has dicing streets, and the pattern formed by the dicing streets is denoted as the front pattern.

[0015] At least two positioning points are arranged in a matching manner on both the back pattern and the front pattern, and the positioning points are arranged corresponding to the positioning holes.

[0016] An electroplated metal layer is formed on the surface of the seed layer in the area not covered by the patterned glue layer, and the patterned glue layer is removed to obtain an assembly with a back pattern.

[0017] Preferably, the method for forming at least two positioning holes includes: forming the positioning holes by laser etching. Among them, a light spot with a size below 10 μm is formed during the laser etching.

[0018] Preferably, the power of the laser etching is 1 - 10 W.

[0019] Preferably, the wavelength of the laser etching is 320 - 380 nm.

[0020] Preferably, the pulse frequency of the laser etching is 100 - 500 kHz.

[0021] Preferably, the single-pulse energy of the laser etching is 0.1 - 1 μJ.

[0022] Preferably, before forming at least two positioning holes, the method further includes:

[0023] Bonding the front surface of the wafer to a glass substrate to obtain a bonded component.

[0024] Performing a thinning process on the back surface of the wafer of the bonded component to obtain a thinned component.

[0025] Preferably, the front surface of the wafer is bonded to the glass substrate through an adhesive layer.

[0026] Among them, the positioning holes penetrate through the thickness direction of the wafer and also penetrate through the adhesive layer, or the positioning holes penetrate through the thickness direction of the wafer and also penetrate through the adhesive layer and the glass substrate.

[0027] Preferably, the thickness of the wafer after thinning treatment is 20~100μm, such as 20μm, 29μm, 38μm, 47μm, 56μm, 65μm, 74μm, 83μm, 92μm or 100μm, etc., but not limited to the listed values, and other unlisted values within this range are equally applicable.

[0028] Preferably, the seed layer includes a first sub-layer and a second sub-layer stacked in sequence along the wafer.

[0029] Preferably, the first sub-layer is a titanium layer.

[0030] Preferably, the second sub-layer is a copper layer.

[0031] Preferably, the thickness of the first sub-layer is 50~80nm.

[0032] Preferably, the thickness of the second sub-layer is 200~400nm.

[0033] Preferably, the processing processes of the first sub-layer and the second sub-layer independently include evaporation plating and / or sputtering plating.

[0034] Preferably, the sputtering power of the first sub-layer is 300~500W.

[0035] Preferably, the sputtering power of the second sub-layer is 200~350W.

[0036] Preferably, the vacuum degrees in the sputtering plating of the first sub-layer and the second sub-layer are the same. The base vacuum is: ≤5×10 - 7 Torr; the working gas pressure is 3~5mTorr, such as 3mTorr, 3.2mTorr, 3.4mTorr, 3.5mTorr, 3.8mTorr, 4.0mTorr, 4.2mTorr, 4.5mTorr or 5mTorr, etc., to reduce scattering at low gas pressure and improve the film layer uniformity; the pre-sputtering time is 10~15 minutes, such as 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes or 15 minutes, etc., to ensure that the pre-sputtering time thoroughly removes the oxide on the titanium target surface and ensure the sputtering stability.

[0037] Preferably, the sputtering plating of the first sub-layer and the second sub-layer independently includes any one or a combination of at least two of DC sputtering, RF sputtering or magnetron sputtering.

[0038] Preferably, the deposition rate in the sputtering plating of the first sub-layer is 0.2~0.4nm / s.

[0039] Preferably, the deposition rate in the sputtering plating of the second sub-layer is 1.0~1.8nm / s.

[0040] Preferably, the forming process of the patterned glue layer is a photolithography process.

[0041] Preferably, the steps of the photolithography process include spin coating, photolithography, and development performed in sequence.

[0042] Preferably, the thickness of the patterned glue layer is denoted as H1, and the thickness of the electroplated metal layer is denoted as H2, where the ratio of H1 to H2 is 1.20:1 or more.

[0043] And / or, the back pattern is the same as the front pattern.

[0044] Preferably, the thickness of the patterned glue layer is 12 - 65 μm.

[0045] And / or, the thickness of the electroplated metal layer is 10 - 50 μm.

[0046] Preferably, the forming process of the electroplated metal layer is horizontal electroplating.

[0047] Preferably, after removing the patterned glue layer, the method further includes:

[0048] Debonding the assembly with the back pattern, and directly dicing the wafer composite after debonding by attaching a dicing tape.

[0049] Compared with the prior art, the present invention has at least the following beneficial effects:

[0050] (1) The method for electroplating metal on the back of a wafer provided by the present invention realizes the replication of the front pattern of the wafer to the back pattern of the wafer through the positioning holes, and can avoid the use of double-sided lithography equipment; moreover, compared with the traditional process of etching the carrier plate, it can significantly reduce the risk of fragmentation, improve production efficiency and production yield.

[0051] (2) The method for electroplating metal on the back of a wafer provided by the present invention forms a patterned glue layer on the seed layer, and subsequent cutting of the electroplated thick copper layer is not required, reducing the risk of fragmentation during the thick copper cutting process. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a schematic flow chart of the method for electroplating metal on the back of a wafer provided by the specific embodiment of the present invention.

[0053] Figure 2 is a schematic diagram of the first assembly obtained in step S101 in Embodiment 1 of the present invention.

[0054] Figure 3 is a schematic diagram of the assembled component obtained in step S102 in Embodiment 1 of the present invention.

[0055] Figure 4 It is a schematic diagram of the thinned component obtained in step S103 of Embodiment 1 of the present invention.

[0056] Figure 5 It is a schematic diagram of forming positioning holes in step S104 of Embodiment 1 of the present invention.

[0057] Figure 6 It is a schematic diagram of the component with a seed layer obtained in step S2 of Embodiment 1 of the present invention.

[0058] Figure 7 It is a schematic diagram of the component with a glue layer obtained in step S3 of Embodiment 1 of the present invention.

[0059] Figure 8 It is a schematic diagram of the assembly with an electroplated metal layer formed in step S4 of Embodiment 1 of the present invention.

[0060] Figure 9 It is a schematic diagram of the assembly with a back pattern in step S4 of Embodiment 1 of the present invention.

[0061] In the figure, 1 - wafer; 2 - adhesive layer; 3 - glass substrate; 4 - positioning hole; 5 - seed layer; 6 - patterned glue layer; 7 - electroplated metal layer; 8 - back cutting area. Detailed implementation manners

[0062] For the convenience of understanding the present invention, the following embodiments are listed. Those skilled in the art should understand that the embodiments are only for helping to understand the present invention and should not be regarded as specific limitations to the present invention.

[0063] It should be understood that in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0064] It should be noted that in the description of the present invention, unless otherwise clearly defined and limited, the terms "set", "connected", "connected to" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood through specific situations.

[0065] To solve the problems in the prior art, such as high equipment cost, reduced cutting efficiency, and high risk of fragmentation, when electroplating a 10 - 50μm thick copper layer on the back of a wafer with a thickness of 20 - 100μm, the present invention associates the positioning points on the front and back of the wafer by using positioning holes, and avoids the problem of thick copper cutting through photolithography. The overall process flow is short, the fragmentation rate is low, and the application prospect is broad.

[0066] The following will be described in detail with specific implementation examples.

[0067] As a specific embodiment of the present invention, a method for electroplating metal on the back of a wafer is provided, and the specific process is as Figure 1 shown. The method includes the following steps:

[0068] S1. Form at least two positioning holes at the edge of the wafer, and the positioning holes penetrate at least the thickness direction of the wafer.

[0069] It should be noted that the process difficulty of setting positioning holes in the present invention is completely different from that of drilling holes in other process productions. Firstly, the present invention is aimed at the wafer production process. On the one hand, the wafer is small and thin, with high brittleness, and is prone to cracks and breakage. During the drilling process, stress will inevitably be generated. How to ensure that the wafer is not damaged during drilling is crucial. On the other hand, the entire process belongs to micron - level manufacturing, with extremely high requirements for unknown precision. This requires high precision in the drilling position and small deviation in the hole diameter. At the same time, the roughness of the hole wall after drilling may also affect the subsequent performance of the wafer. To solve the above difficulties, the present invention adopts a laser etching drilling process, and improves the drilling precision by controlling the formation of a light spot with a diameter of less than 10μm during laser etching. At the same time, a femtosecond laser is preferably used to reduce stress concentration and reduce the risk of fragmentation.

[0070] In some specific embodiments of the present invention, the diameter of the positioning hole is less than or equal to 10μm. For example, it can be 10μm, 9.8μm, 9.5μm, 9μm, 8.5μm, 8μm, 7.5μm, 7μm, 6.5μm, 6μm, 5.5μm, 5μm, 4.5μm, 4μm, or 3.5μm, etc., but is not limited to the listed values, and other unlisted values within this range are equally applicable.

[0071] The present invention preferably controls the diameter of the positioning hole to be less than or equal to 10μm, which can better improve the positioning accuracy and reduce the risk of wafer fragmentation.

[0072] Using the method provided by the present invention does not require etching the carrier plate, greatly reducing the production cost and the risk of fragmentation.

[0073] In certain specific embodiments of the present invention, the method for forming at least two positioning holes includes: forming the positioning holes by laser etching. Wherein, a light spot with a size below 10 μm is formed during the laser etching. For example, it can be 10 μm, 9.8 μm, 9.5 μm, 9 μm, 8.5 μm, 8 μm, 7.5 μm, 7 μm, 6.5 μm, 6 μm, 5.5 μm, 5 μm, 4.5 μm, 4 μm or 3.5 μm, etc., but not limited to the listed values. Other unlisted values within this range are equally applicable.

[0074] In certain specific embodiments of the present invention, the power of the laser etching is 1 - 10 W. For example, it can be 1 W, 2 W, 3 W, 4 W, 5 W, 6 W, 7 W, 8 W, 9 W or 10 W, etc., but not limited to the listed values. Other unlisted values within this range are equally applicable. The wavelength of the laser etching is 320 - 380 nm. For example, it can be 320 nm, 330 nm, 340 nm, 350 nm, 352 nm, 353 nm, 354 nm, 355 nm, 356 nm, 357 nm, 358 nm, 359 nm, 360 nm, 370 nm or 380 nm, etc., but not limited to the listed values. Other unlisted values within this range are equally applicable. Generally, a 355 laser is used in the present invention. Due to the differences in chip manufacturing processes and usage environments, the actual emitted wavelength range fluctuates within 320 - 380 nm. Generally speaking, the wavelength of the laser etching is ultraviolet 355 nm. Silicon has an absorption rate of ultraviolet light at 355 nm of over 80%, which can be efficiently converted into ablation energy, reducing heat diffusion. The ultraviolet wavelength is shorter, and a smaller light spot (close to the diffraction limit) can be focused, meeting the requirement of a 10 - μm aperture.

[0075] The pulse frequency of the laser etching is 100 - 500 kHz. For example, it can be 100 kHz, 145 kHz, 189 kHz, 234 kHz, 278 kHz, 323 kHz, 367 kHz, 412 kHz, 456 kHz or 500 kHz, etc., but not limited to the listed values. Other unlisted values within this range are equally applicable. The single - pulse energy of the laser etching is 0.1 - 1 μJ. For example, it can be 0.1 μJ, 0.2 μJ, 0.3 μJ, 0.4 μJ, 0.5 μJ, 0.6 μJ, 0.7 μJ, 0.8 μJ, 0.9 μJ or 1 μJ, etc., but not limited to the listed values. Other unlisted values within this range are equally applicable.

[0076] When laser - drilling the above - mentioned wafer bonding chips in the present invention, the configuration of the laser needs to comprehensively consider factors such as material properties, processing quality (aperture, precision, heat - affected zone), efficiency and cost, etc.

[0077] The pulse type adopted in the present invention is femtosecond laser (fs level, 100 - 500 fs), and the heat affected zone is almost zero, avoiding silicon melting or microcracks, ensuring smooth hole walls and no residual stress. If the budget is limited, picosecond laser (ps level) can be selected, but the repetition frequency needs to be appropriately reduced to reduce heat accumulation.

[0078] The single - pulse energy of the laser etching in the present invention is 0.1 - 1 μJ. This single - pulse energy needs to match the aperture and the thickness of the silicon wafer, and the average power is 1 - 10 W.

[0079] The repetition frequency of the present invention is 100 - 500 kHz. When using a high repetition frequency, the processing speed can be improved. It needs to be combined with a high - speed galvanometer and a motion platform, and needs to be optimized through experiments to avoid rough edges caused by heat accumulation.

[0080] The optical system configuration in the laser etching process of the present invention includes a spot control and a focusing system. Among them, the spot control uses DOE (Diffractive Optical Element) or SLM (Spatial Light Modulator) to form a spot below 10 μm to improve the processing accuracy. In the focusing system, the NA value of the objective lens ≥ 0.4. A high numerical aperture reduces the spot size. For example, for a 10 - μm aperture, the spot diameter needs to be ≈ 5 μm; Galvanometer scanning system: It is paired with an F - theta lens to ensure the spot consistency under high - speed scanning and guarantee the position accuracy of ±1 μm.

[0081] Exemplarily, the processing environment of the laser etching in the present invention is a clean room (ISO5 level), and nitrogen purging is adopted during the etching process. The scanning speed of the galvanometer system is 500 mm / s.

[0082] In some specific embodiments of the present invention, before forming at least two positioning holes, the method further includes:

[0083] Bonding the front side of the wafer to a glass substrate to obtain a bonded assembly.

[0084] Thinning the back side of the wafer in the bonded assembly to obtain a thinned assembly.

[0085] The present invention preferably performs the bonding and thinning treatment steps first. The glass substrate is a transparent substrate, which can also identify the front - side pattern of the wafer during the laser hole - drilling process, and can avoid the problem of hole blockage that occurs during the process of drilling holes first and then bonding and thinning.

[0086] In some specific embodiments of the present invention, the front side of the wafer is bonded to the glass substrate through an adhesive layer.

[0087] In the present invention, the adhesive layer can be a transparent material or an opaque material, and there is no special limitation in this regard. Since the front pattern of the wafer has a certain thickness, even if an opaque material is used, the adhesive layer formed on the front of the wafer still has the same convex pattern as the front pattern, which does not affect the drilling operation.

[0088] In some specific embodiments of the present invention, the positioning hole penetrates through the adhesive layer while penetrating through the thickness direction of the wafer, or the positioning hole penetrates through the adhesive layer and the glass substrate while penetrating through the thickness direction of the wafer.

[0089] Generally, if bonding is performed first and then drilling is carried out, the positioning hole penetrates through the adhesive layer and the glass substrate while penetrating through the thickness direction of the wafer.

[0090] In some specific embodiments of the present invention, the thickness of the thinned wafer is 20 - 100 μm, for example, it can be 20 μm, 29 μm, 38 μm, 47 μm, 56 μm, 65 μm, 74 μm, 83 μm, 92 μm or 100 μm, etc., but is not limited to the listed values, and other unlisted values within this range are equally applicable.

[0091] It should be noted that the thinner the wafer, the higher the risk of fragmentation in each process during production. Currently, for wafers with a thickness of 20 - 100 μm, if a thick copper layer with a thickness of up to 10 - 50 μm is electroplated on its back, the manufacturing difficulty is even greater.

[0092] The present invention has no special requirements for the material of the wafer, and the wafer material well-known to those skilled in the art can be used, for example, it can be silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, sapphire, quartz or aluminum nitride, etc.

[0093] S2. A seed layer is formed on the back of the wafer to obtain a component with a seed layer.

[0094] In some specific embodiments of the present invention, the seed layer includes a first sub-layer and a second sub-layer stacked in sequence along the wafer.

[0095] Those skilled in the art know that by setting the seed layer in the present invention, the seed layer can significantly improve the adhesion between the copper plating layer and the wafer substrate, prevent the copper layer from falling off or delaminating in subsequent processes, and moreover, as a conductive layer, the seed layer can effectively reduce the contact resistance between the copper plating layer and the wafer substrate, thereby improving the current transmission efficiency and reducing energy loss; furthermore, it can improve the quality of the copper layer in subsequent electroplating of copper, that is, improve the uniformity of the electroplated metal layer.

[0096] Among them, the first sub-layer is a titanium layer and the second sub-layer is a copper layer.

[0097] It should be noted that the process of fabricating the seed layer includes four steps: pretreatment, titanium seed layer sputtering, copper seed layer sputtering, and post-treatment and detection:

[0098] Pretreatment: Use RCA standard cleaning (SC1 + SC2) to remove organic residues and metal contaminants, and then adopt plasma cleaning method to perform Ar plasma bombardment (RF power 50 - 100W, 5 minutes) in the sputtering chamber to activate the silicon surface.

[0099] Among them, RCA standard cleaning is a crucial wet chemical cleaning process in semiconductor manufacturing, aiming to remove particles, organic and inorganic contaminants on the surface of silicon wafers, and provide a clean surface for subsequent semiconductor manufacturing processes. This process was developed by the Radio Corporation of America (RCA). SC1 + SC2 refers to SC-1 cleaning solution and SC-2 cleaning solution, and the specific proportion of substances is not specially limited, and the composition well-known to those skilled in the art can be adopted.

[0100] Titanium seed layer sputtering: Prepare a high-purity titanium target (≥99.995%), pre-sputter to remove the surface oxide layer, and deposit the titanium seed layer in a low-pressure argon gas environment.

[0101] Copper (Cu) seed layer sputtering: Switch the target to a high-purity copper target (≥99.999%), pre-sputter to clean the target surface, and deposit a conductive copper layer on the titanium layer to ensure continuity and low resistivity.

[0102] Post-treatment and detection: According to the product properties, vacuum alloying can be selected, and low-temperature annealing is used to optimize the conductivity of the copper layer. After the coating is completed, quality inspection includes film thickness, resistivity, adhesion, and uniformity tests.

[0103] For the sputtering process of the seed layer, it is necessary to adjust the sputtering parameters in combination with the characteristics of the wafer size (such as uniformity, thermal management requirements) and the requirements of the subsequent electroplating process. Here, taking an 8-inch silicon-based wafer as an example, the following parameter descriptions are given exemplarily:

[0104] In some specific embodiments of the present invention, the thickness of the first sub-layer is 50 - 80nm, for example, it can be 50nm, 55nm, 60nm, 62nm, 65nm, 70nm, 75nm, 78nm, or 80nm, etc. The surface area of an 8-inch wafer is relatively large, and it is necessary to ensure the uniformity and adhesion of the titanium layer to avoid the failure of the barrier layer due to being too thin (<50nm) or introducing stress due to being too thick (>100nm).

[0105] In certain specific embodiments of the present invention, the thickness of the second sub-layer is 200 - 400 nm, and for example, it can be 200 nm, 210 nm, 220 nm, 250 nm, 280 nm, 300 nm, 310 nm, 320 nm, 350 nm, 370 nm, 380 nm or 400 nm, etc. The 8-inch power device needs to support subsequent copper electroplating with a thickness of 10 - 50 μm. The seed layer needs to be continuous and hole-free, while balancing conductivity and cost.

[0106] In the present invention, the thickness of the seed layer is relatively thin, and subsequent cutting can be directly carried out without chemical etching.

[0107] In certain specific embodiments of the present invention, the processing processes of the first sub-layer and the second sub-layer independently include evaporation plating and / or sputtering plating.

[0108] The present invention has no special restrictions on the specific process parameters during the processing of the first sub-layer and the second sub-layer, and the process parameters well-known to those skilled in the art can be adopted. Here, only the process parameters of sputtering plating are introduced.

[0109] Preferably, the sputtering power of the first sub-layer is 300 - 500 W, and for example, it can be 300 W, 320 W, 340 W, 350 W, 380 W, 400 W, 420 W, 450 W, 480 W or 500 W, etc.

[0110] Preferably, the sputtering power of the second sub-layer is 200 - 350 W, and for example, it can be 200 W, 210 W, 220 W, 250 W, 280 W, 300 W, 320 W or 350 W, etc. The melting point of copper is relatively low, so it is necessary to avoid droplet contamination caused by overheating of the target.

[0111] Preferably, the vacuum degrees in the sputtering plating of the first sub-layer and the second sub-layer are the same, and the base vacuum is: ≤5×10 - 7 Torr, and for example, it can be 5×10 -7 Torr, 4.9×10 -7 Torr, 4.8×10 -7 Torr, 4.7×10 -7 Torr, 4.5×10 - 7 Torr, 4.3×10 -7 Torr, 4.2×10 -7 Torr, 4.0×10 -7 Torr, 3.9×10 -7 Torr, 3.8×10 -7 Torr or 3.5×10 -7Torr, etc., to obtain higher cleanliness requirements and reduce impurity contamination; the working gas pressure is 3~5mTorr, for example, it can be 3mTorr, 3.2mTorr, 3.4mTorr, 3.5mTorr, 3.8mTorr, 4.0mTorr, 4.2mTorr, 4.5mTorr or 5mTorr, etc., to reduce scattering with low gas pressure and improve film uniformity; the pre-sputtering time is 10~15 minutes, for example, it can be 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes or 15 minutes, etc., to ensure the pre-sputtering time to completely remove the oxide on the surface of the titanium target and ensure the sputtering stability.

[0112] Preferably, the deposition rate in the sputtering plating of the first sublayer is 0.2~0.4nm / s, for example, it can be 0.2nm / s, 0.23nm / s, 0.25nm / s, 0.27nm / s, 0.29nm / s, 0.32nm / s, 0.34nm / s, 0.36nm / s, 0.38nm / s or 0.4nm / s, but is not limited to the listed values. Other unlisted values within the range are also applicable. At this time, using a low speed can improve the density of the film layer.

[0113] Preferably, the deposition rate in the sputtering plating of the second sub-layer is 1.0~1.8nm / s, for example, it can be 1.0nm / s, 1.09nm / s, 1.18nm / s, 1.27nm / s, 1.36nm / s, 1.45nm / s, 1.54nm / s, 1.63nm / s, 1.72nm / s or 1.8nm / s, but is not limited to the listed values. Other unlisted values within the range are also applicable. A high rate is used to increase production capacity during the sputtering plating of the second sub-layer, but it needs to be coordinated with gas pressure optimization.

[0114] S3, positioning is performed using the positioning holes, and a patterned adhesive layer is formed on a surface of the seed layer of the seed layer-containing component away from the wafer to obtain an adhesive layer-containing component.

[0115] The patterned adhesive layer partially covers the seed layer, and the pattern formed on the seed layer in the area covered by the patterned adhesive layer is recorded as a back side pattern.

[0116] The front side of the wafer has a cutting path, and a pattern formed by the cutting path is recorded as a front side pattern.

[0117] The back pattern and the front pattern both have at least two positioning points that are matched with each other, and the positioning points are arranged corresponding to the positioning holes.

[0118] In the present invention, there is no particular limitation on the specific material of the adhesive in the pattern-containing adhesive layer, and a photoresist well known to those skilled in the art may be used, for example, a negative photoresist or a positive photoresist.

[0119] Preferably, the process for forming the patterned glue layer is a photolithography process.

[0120] In certain specific embodiments of the present invention, the steps of the photolithography process include spin coating, photolithography, and development carried out in sequence.

[0121] Specifically, the photolithography process includes:

[0122] S301, spin coating: forming a first glue layer on the surface of the seed layer.

[0123] S302, photolithography: disposing a mask plate matching the required back pattern on the surface of the first glue layer, and performing exposure and drying.

[0124] S303, development: removing the unnecessary part of the first glue layer to obtain the patterned glue layer.

[0125] In certain specific embodiments of the present invention, the thickness of the patterned glue layer is denoted as H1, and the thickness of the electroplated metal layer is denoted as H2, where the ratio of H1 to H2 is 1.20:1 or more, for example, it can be 1.20:1, 1.21:1, 1.22:1, 1.23:1, 1.24:1, 1.25:1, 1.26:1, 1.27:1, 1.28:1, 1.29:1, 1.30:1, 1.32:1, 1.35:1, 1.40:1, 1.45:1, 1.50:1, or 1.5:1, etc., but not limited to the listed values, and other unlisted values within this range are equally applicable, preferably (1.20 - 2.0):1.

[0126] The method for electroplating metal on the back side of the wafer provided by the present invention preferably controls the ratio of H1 to H2 to be 1.20:1 or more, which can avoid the metal overflowing to the upper surface of the patterned glue layer during the electroplating of copper, resulting in adhesion during cutting; more preferably, the ratio of H1 to H2 is (1.20 - 2.0):1, which can further reduce the thickness of the spin coating and the usage amount of the developing agent, and the production cost is lower.

[0127] Preferably, the back pattern is the same as the front pattern.

[0128] Precisely because the back pattern needs to be the same as the front pattern, it is necessary to calibrate the photolithography position by laser drilling, so as to accurately obtain an electroplated thick copper layer with the back pattern and the front pattern being consistent, avoid using double-sided photolithography (expensive equipment), and do not need to etch the carrier plate (complicated and difficult process). The seed layer of the present invention is relatively thin and can be directly cut without the need for separate etching. Moreover, the overall process flow is simple and suitable for mass production.

[0129] In certain specific embodiments of the present invention, the thickness of the patterned glue layer is 12 - 65 μm. For example, it can be 12 μm, 15 μm, 20 μm, 22 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, 40 μm, 42 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, etc., but is not limited to the listed values, and other unlisted values within this range are equally applicable.

[0130] S4. Form an electroplated metal layer on the surface of the seed layer in the area not covered by the patterned glue layer, and remove the patterned glue layer to obtain an assembly with a back pattern.

[0131] In certain specific embodiments of the present invention, the thickness of the electroplated metal layer is 10 - 50 μm. For example, it can be 10 μm, 15 μm, 19 μm, 24 μm, 28 μm, 33 μm, 37 μm, 42 μm, 46 μm, 50 μm, etc., but is not limited to the listed values, and other unlisted values within this range are equally applicable.

[0132] In certain specific embodiments of the present invention, the forming process of the electroplated metal layer is horizontal electroplating.

[0133] In certain specific embodiments of the present invention, there are no special restrictions on the process parameters and the composition of the electroplating solution during the electroplating of the metal layer, and the process parameters well-known to those skilled in the art can be used. For example, the current density in the electroplated metal layer is 2 - 5 A / dm², where the low current density is 2 - 3 A / dm², suitable for high-precision coatings such as 10 - 20 μm to reduce edge effects; the high current density is 4 - 5 A / dm², used for rapid deposition of thick copper layers such as 30 - 50 μm, and strong stirring is required to maintain uniformity. The components of the electroplating solution in the electroplated metal layer are 70 - 220 g / L of copper sulfate (copper sulfate pentahydrate), 150 - 250 g / L of sulfuric acid, 30 - 90 ppm of chloride ions, 60 - 90 ppm of additives (such as thiourea derivatives), 10 - 30 ppm of leveling agents (such as polyethylene glycol), 20 - 40 ppm of inhibitors (such as tetrabutylammonium bromide), 120 - 480 ppm of carriers (complexes containing chloride ions and vanadium ions), etc.

[0134] In certain specific embodiments of the present invention, the material of the electroplated metal layer described in the present invention includes metals such as copper and copper alloys.

[0135] Preferably, after removing the patterned glue layer, the method further includes: debonding the assembly with the back pattern, and directly attaching a dicing film to the debonded wafer composite for dicing.

[0136] The present invention can use an E-chuck suction cup for debonding.

[0137] Since the seed layer formed by the process method provided by the present invention is relatively thin, after subsequent debonding, scribing film can be directly pasted for cutting without the need for an etching process, and the success rate of wafer preparation is high.

[0138] The following will be described in detail with specific embodiments.

[0139] Embodiment 1

[0140] This embodiment provides a method for electroplating copper on the back of a wafer. The method includes the following steps:

[0141] S101. Complete the front process of wafer 1 to obtain a first component, as Figure 2 shown.

[0142] S102. Bond the front of the wafer 1 to the glass substrate 3 through the adhesive layer 2 to obtain a bonded component, as Figure 3 shown.

[0143] S103. Thinning the back of the wafer 1 in the bonded component to a thickness of 50 μm to obtain a thinned component, as Figure 4 shown.

[0144] S104. As Figure 5 shown, use laser etching to form 3 positioning holes 4 on the edge of the wafer 1. The positioning holes 4 penetrate through the thickness direction of the wafer 1 and also penetrate through the adhesive layer 2 and the glass substrate 3, and the 3 positioning holes 4 are not on the same straight line to better form a positioning effect.

[0145] Among them, the pulse type used for the laser etching is 300 fs femtosecond laser, the power is 5 W; the wavelength of the laser etching is 355 nm; the pulse frequency of the laser etching is 200 kHz; the single pulse energy of the laser etching is 0.5 μJ, and DOE (diffractive optical element) is used, and the NA value of the objective lens in the focusing system is 0.4 to form a 5 μm spot, and an F-theta lens is used to ensure the spot consistency under high-speed scanning, ensure the position accuracy of ±1 μm, and the scanning speed of the galvanometer system is 500 mm / s.

[0146] S2. Form a seed layer 5 on the back of the wafer 1 to obtain a component with a seed layer, as Figure 6 shown.

[0147] The seed layer 5 includes a first sub-layer and a second sub-layer that are sequentially stacked along the wafer 1. Among them, the first sub-layer is a titanium layer, and the second sub-layer is a copper layer. The thickness of the first sub-layer is 60 nm. The thickness of the second sub-layer is 300 nm.

[0148] Among them, the sputtering power of the first sub-layer is 400W, and the deposition rate is 0.3nm / s; the sputtering power of the second sub-layer is 250W, and the deposition rate is 1.5nm / s; the vacuum degrees in the sputtering coatings of the first sub-layer and the second sub-layer are the same, the base vacuum is 4×10 -7 Torr, and the working gas pressure is 4mTorr for both.

[0149] S3. Position with the positioning hole 4, and form a patterned glue layer 6 on the surface of the seed layer 5 of the seed layer-containing component away from the wafer 1 to obtain a glue layer-containing component, as Figure 7 shown.

[0150] Among them, the patterned glue layer 6 partially covers the seed layer 5, and the pattern formed in the area covered by the patterned glue layer 6 on the seed layer 5 is denoted as the back pattern. The front side of the wafer 1 has a scribe lane, and the pattern formed by the scribe lane is denoted as the front pattern. At least two positioning points are arranged in a matching manner on both the back pattern and the front pattern, the positioning points are arranged corresponding to the positioning hole 4, and the back pattern and the front pattern are the same.

[0151] Specifically, the forming process of the patterned glue layer 6 is a photolithography process, and the photolithography process includes:

[0152] S301. Glue coating: Form a first glue layer on the surface of the seed layer 5.

[0153] S302. Photolithography: Set a mask plate matching the required back pattern on the surface of the first glue layer, and perform exposure and drying.

[0154] S303. Development: Remove the unnecessary part of the first glue layer to obtain the patterned glue layer 6. The thickness of the patterned glue layer 6 is denoted as H1, and the thickness of the electroplated copper layer 7 is denoted as H2, where the ratio of H1 to H2 is 1.20:1. Specifically, the thickness of the patterned glue layer 6 is 60μm.

[0155] S4. Perform horizontal electroplating on the surface of the seed layer 5 in the area not covered by the patterned glue layer 6 to form an electroplated copper layer 7 with a thickness of 50μm, as Figure 8 shown, and remove the patterned glue layer 6 to expose the back cutting area 8 to obtain an assembly with a back pattern, as Figure 9 shown.

[0156] S5. Debond the assembly with the back pattern, and directly cut the wafer 1 composite after debonding by pasting a dicing film.

[0157] The method for electroplating copper on the back side of the wafer provided in this embodiment has simple steps, greatly shortening the production process of backside copper electroplating. Without using a double-sided lithography machine, by directly drilling holes at the edge of the wafer from the front side, the pattern of the front cutting channel can be replicated to the back side, thus avoiding the problems of wafer fragmentation or high production costs caused by the cutting process for electroplating thick copper, and having broad application prospects.

[0158] Embodiment 2

[0159] This embodiment provides a method for electroplating copper on the back side of a wafer, and the method includes the following steps:

[0160] S101. Complete the front process of the wafer to obtain a first component.

[0161] S102. Bond the front side of the wafer to a glass substrate through an adhesive layer to obtain a bonded component.

[0162] S103. Perform a thinning process on the back side of the wafer in the bonded component until the thickness of the wafer is 20 μm to obtain a thinned component.

[0163] S104. Use laser etching to form 3 positioning holes at the edge of the wafer. The positioning holes penetrate through the thickness direction of the wafer and also penetrate through the adhesive layer and the glass substrate, and the 3 positioning holes are not on the same straight line to better form a positioning effect.

[0164] Among them, the pulse type used in the laser etching is femtosecond laser, with a power of 10 W; the wavelength of the laser etching is 355 nm; the pulse frequency of the laser etching is 100 kHz; the single-pulse energy of the laser etching is 1 μJ, and a DOE (diffractive optical element) is used, and the NA value of the objective lens in the focusing system is 0.5 to form a 4-μm light spot, and an F-theta lens is used to ensure the consistency of the light spot under high-speed scanning, guarantee the position accuracy of ±1 μm, and the scanning speed of the galvanometer system is 400 mm / s.

[0165] S2. Form a seed layer on the back side of the wafer to obtain a component with a seed layer.

[0166] The seed layer includes a first sub-layer and a second sub-layer stacked in sequence along the wafer. Among them, the first sub-layer is a titanium layer, and the second sub-layer is a copper layer. The thickness of the first sub-layer is 80 nm. The thickness of the second sub-layer is 400 nm.

[0167] Among them, the sputtering power of the first sub-layer is 500 W, and the deposition rate is 0.4 nm / s; the sputtering power of the second sub-layer is 350 W, and the deposition rate is 1.0 nm / s; the vacuum degrees in the sputtering plating of the first sub-layer and the second sub-layer are the same, and the base vacuum is 5×10 -7Torr, and the working pressure is 5 mTorr for all.

[0168] S3. Position with the positioning holes, and form a patterned glue layer on the surface of the seed layer of the seed layer component away from the wafer to obtain a glue layer component.

[0169] Among them, the patterned glue layer partially covers the seed layer, and the pattern formed on the area of the seed layer covered by the patterned glue layer is recorded as the back pattern. The front of the wafer has scribe lanes, and the pattern formed by the scribe lanes is recorded as the front pattern. There are at least two positioning points with matching settings on both the back pattern and the front pattern. The positioning points are correspondingly set with the positioning holes, and the back pattern and the front pattern are the same.

[0170] Specifically, the forming process of the patterned glue layer is a lithography process, and the lithography process includes:

[0171] S301. Glue coating: Form a first glue layer on the surface of the seed layer.

[0172] S302. Lithography: Set a mask plate matching the required back pattern on the surface of the first glue layer, and perform exposure and drying.

[0173] S303. Development: Remove the unnecessary part of the first glue layer to obtain a patterned glue layer. The thickness of the patterned glue layer is recorded as H1, and the thickness of the electroplated copper layer is recorded as H2. The ratio of H1 to H2 is 1.25:1. Specifically, the thickness of the patterned glue layer is 50 μm.

[0174] S4. Perform horizontal electroplating on the surface of the seed layer in the area not covered by the patterned glue layer to form an electroplated copper layer with a thickness of 40 μm, and remove the patterned glue layer to obtain a combined component with a back pattern.

[0175] S5. Debond the combined component with the back pattern, and directly cut the wafer composite after debonding by attaching a dicing film.

[0176] The method for electroplating copper on the back of the wafer provided in this embodiment has simple steps, greatly shortens the production process of electroplating copper on the back, does not require a double-sided lithography machine, and can directly copy the front scribe lane pattern to the back by punching holes at the edge of the wafer from the front, thus avoiding the problems of wafer fragmentation or high production cost caused by the cutting process for electroplating thick copper, and has broad application prospects.

[0177] Embodiment 3

[0178] This embodiment provides a method for electroplating copper on the back of a wafer. The method includes the following steps:

[0179] S101. Complete the front process of the wafer to obtain the first component.

[0180] S102. Bond the front side of the wafer to the glass substrate through an adhesive layer to obtain a bonded component.

[0181] S103. Thinning the back side of the wafer in the bonded component until the thickness of the wafer is 100 μm to obtain a thinned component.

[0182] S104. Use laser etching to form 2 positioning holes at the edge of the wafer, and the positioning holes penetrate through the thickness direction of the wafer and also penetrate through the adhesive layer and the glass substrate.

[0183] Among them, the pulse type used for the laser etching is femtosecond laser, and the power is 1 W; the wavelength of the laser etching is 355 nm; the pulse frequency of the laser etching is 500 kHz; the single pulse energy of the laser etching is 0.1 μJ, and DOE (diffractive optical element) is used, and the NA value of the objective lens in the focusing system is 0.4 to form a 5-μm spot, and an F-theta lens is used to ensure the spot consistency under high-speed scanning, ensure the position accuracy of ±1 μm, and the scanning speed of the galvanometer system is 550 mm / s. S2. Form a seed layer on the back side of the wafer to obtain a component with a seed layer.

[0184] The seed layer includes a first sub-layer and a second sub-layer that are sequentially stacked along the wafer. Among them, the first sub-layer is a titanium layer, and the second sub-layer is a copper layer. The thickness of the first sub-layer is 50 nm. The thickness of the second sub-layer is 200 nm.

[0185] Among them, the sputtering power of the first sub-layer is 300 W, and the deposition rate is 0.2 nm / s; the sputtering power of the second sub-layer is 200 W, and the deposition rate is 1.8 nm / s; the vacuum degrees in the sputtering coatings of the first sub-layer and the second sub-layer are the same, the base vacuum is 4.5×10 -7 Torr, and the working gas pressure is 3 mTorr.

[0186] S3. Use the positioning holes for positioning, and form a patterned glue layer on the surface of the component with a seed layer on the side of the seed layer away from the wafer to obtain a component with a glue layer.

[0187] Among them, the patterned glue layer partially covers the seed layer, and the pattern formed in the area of the seed layer covered by the patterned glue layer is recorded as the back pattern. The front side of the wafer has cutting channels, and the pattern formed by the cutting channels is recorded as the front pattern. There are at least two positioning points that are matched and set on both the back pattern and the front pattern, the positioning points are correspondingly set with the positioning holes, and the back pattern and the front pattern are the same.

[0188] Specifically, the forming process of the patterned glue layer is a photolithography process, and the photolithography process includes:

[0189] S301, Glue coating: Form a first glue layer on the surface of the seed layer.

[0190] S302, Photolithography: Set a mask plate matching the required back pattern on the surface of the first glue layer, and perform exposure and drying.

[0191] S303, Development: Remove the unnecessary part of the first glue layer to obtain a patterned glue layer. The thickness of the patterned glue layer is denoted as H1, and the thickness of the electroplated copper layer is denoted as H2. The ratio of H1 to H2 is 1.2:1. Specifically, the thickness of the patterned glue layer is 12 μm.

[0192] S4, Horizontally electroplate on the surface of the seed layer in the area not covered by the patterned glue layer to form an electroplated copper layer with a thickness of 10 μm, and remove the patterned glue layer to obtain an assembly with a back pattern.

[0193] S5, Debond the assembly with the back pattern, and directly attach a dicing film to the debonded wafer composite for cutting.

[0194] The method for electroplating copper on the back of the wafer provided in this embodiment has simple steps, greatly shortens the production process of electroplating copper on the back, does not require a double-sided lithography machine, and can directly replicate the front cutting channel pattern to the back by punching holes at the edge of the wafer from the front, thus avoiding the problems of wafer fragmentation or high production cost caused by the cutting process for electroplating thick copper, and has broad application prospects.

[0195] Example 4

[0196] This embodiment provides a method for electroplating copper on the back of a wafer. Except that the thickness of the patterned glue layer in step S303 is 55 μm, that is, the ratio of H1 to H2 is controlled to be 1.1:1, the rest are the same as those in Example 1 and will not be elaborated here.

[0197] Compared with Example 4, Example 1 can better ensure that the copper layer during the electroplating copper process will not grow to the upper surface of the patterned glue layer, thus avoiding the situation that it is difficult to remove the subsequent glue layer or still need to cut the copper layer.

[0198] Example 5

[0199] This embodiment provides a method for electroplating copper on the back of a wafer. Except for laser etching to form a 12-μm light spot, the rest are the same as those in Example 1 and will not be elaborated here.

[0200] In this embodiment, due to the relatively large diameter of the formed light spot, the diameter of the drilled positioning holes is as high as 20 μm, making it difficult to perform more precise positioning of the mask on the back side. After electroplating thick copper, when cutting, on the one hand, part of the thick copper needs to be cut, and on the other hand, there are some areas on the back side of the wafer that are not electroplated with thick copper, which easily leads to the failure of the production process.

[0201] Embodiment 6

[0202] This embodiment provides a method for electroplating copper on the back side of a wafer. The method is the same as that of Embodiment 1 except that the pulse type used in laser etching is 100 ps laser, and details are not repeated here.

[0203] In this embodiment, due to the use of picosecond laser, the situation of silicon melting or microcracks on the wafer is likely to occur, and residual stress may appear. Compared with Embodiment 1, the fragmentation rate of the wafer increases.

[0204] Embodiment 7

[0205] This embodiment provides a method for electroplating copper on the back side of a wafer. The method is the same as that of Embodiment 1 except that step S104 is performed first and then step S103, and details are not repeated here.

[0206] Compared with Embodiment 7, in Embodiment 1, thinning is performed first and then laser etching, and there is no risk of blockage of the positioning holes. In Embodiment 7, laser etching is performed first and then thinning, and during the subsequent thinning process, the positioning holes are blocked, making it difficult to accurately position the back-side mask through the positioning holes later, and the process cannot continue.

[0207] Comparative Example 1

[0208] This comparative example provides a process for electroplating thick copper films on both sides with window holes. The method is carried out using the method provided in the specific embodiment of CN111710647A.

[0209] In this comparative example, by forming a glass carrier plate window at the contact point on the front side of the wafer, thick film electroplating of Cu can be performed on both the front and back crystal planes. However, this process requires a double-sided lithography machine. Those skilled in the art know that the price of a double-sided lithography machine is significantly higher than that of a single-sided lithography machine, and the equipment operation accuracy requirements are high. Moreover, after removing the photoresist layer in this comparative example, the seed layers on both sides need to be removed by etching. The overall process is very complex, and each additional step will significantly increase the risk of fragmentation, resulting in a significantly higher fragmentation rate of the overall process compared to the present invention.

[0210] The present invention illustrates the detailed features of the present invention through the above embodiments, but the present invention is not limited to the above detailed features, that is, it does not mean that the present invention must rely on the above detailed features to be implemented. Those skilled in the art should understand that any improvement to the present invention, the equivalent replacement of the technical features selected by the present invention, the addition of auxiliary technical features, the selection of specific ways, etc., all fall within the protection scope and the disclosure scope of the present invention.

Claims

1. A method for electroplating metal on the back side of a wafer, characterized in that, The method includes the following steps: Form at least two positioning holes at the edge of the wafer, and the positioning holes penetrate at least the thickness direction of the wafer; Form a seed layer on the back surface of the wafer to obtain a seed layer-containing component; Using the positioning holes for positioning, form a patterned glue layer on the surface of the seed layer of the seed layer-containing component away from the wafer to obtain a glue layer-containing component; Wherein, the patterned glue layer partially covers the seed layer, and the pattern formed in the area covered by the patterned glue layer on the seed layer is denoted as the back pattern; the front surface of the wafer has a scribe lane, and the pattern formed by the scribe lane is denoted as the front pattern; the back pattern and the front pattern are the same; There are at least two positioning points arranged in a matching manner on both the back pattern and the front pattern, and the positioning points are arranged corresponding to the positioning holes; Form an electroplated metal layer on the surface of the seed layer in the area not covered by the patterned glue layer, and remove the patterned glue layer to obtain a combined component with a back pattern.

2. The method for electroplating metal on the back side of a wafer according to claim 1, wherein The method for forming at least two positioning holes includes: forming the positioning holes by laser etching; And / or, the process parameters of the laser etching at least satisfy one of the following: A. The average power of the laser etching is 1-10W; B. The wavelength of the laser etching is 320-380nm; C. The pulse frequency of the laser etching is 100-500kHz; D. The single pulse energy of the laser etching is 0.1-1μJ.

3. The method for electroplating metal on the back side of a wafer according to claim 1 or 2, characterized in that, Before forming at least two positioning holes, the method further includes: Bond the front surface of the wafer to a glass substrate to obtain a bonded component; Perform a thinning process on the back surface of the wafer of the bonded component to obtain a thinned component.

4. The method for electroplating metal on the back side of a wafer according to claim 3, wherein The front surface of the wafer is bonded to the glass substrate through an adhesive layer; Wherein, the positioning holes penetrate the adhesive layer while penetrating the thickness direction of the wafer, or the positioning holes penetrate the adhesive layer and the glass substrate while penetrating the thickness direction of the wafer.

5. The method for electroplating metal on the back side of a wafer according to claim 3, characterized in that, The thickness of the wafer after the thinning process is 20-100μm.

6. The method for electroplating metal on the back side of a wafer according to claim 1 or 2, wherein The seed layer includes a first sub-layer and a second sub-layer stacked in sequence along the wafer; wherein, the first sub-layer is a titanium layer, and the second sub-layer is a copper layer; And / or, the processing processes of the first sub-layer and the second sub-layer independently include evaporation plating and / or sputtering plating.

7. The method for electroplating metal on the backside of a wafer according to claim 1, wherein The forming process of the patterned glue layer is a photolithography process; Wherein, the steps of the photolithography process include spin coating, photolithography, and development performed in sequence.

8. The method for electroplating metal on the back side of a wafer according to claim 1, wherein The thickness of the patterned glue layer is denoted as H1, and the thickness of the electroplated metal layer is denoted as H2, where the ratio of H1 to H2 is 1.20:1 or more.

9. The method for electroplating metal on the back side of a wafer according to claim 1 or 8, characterized in that, The thickness of the patterned glue layer is 12-65μm; And / or, the thickness of the electroplated metal layer is 10-50μm.

10. The method for electroplating metal on the back side of a wafer according to claim 3, wherein After removing the patterned glue layer, the method further includes: Debond the combined component with the back pattern, and directly attach a dicing film to the wafer composite after debonding and perform dicing.

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