Method for improving defects of gate oxide layer under-buried process

Abstract

The invention provides a method for improving defects of a gate oxide layer under-buried process, which comprises the following steps of: providing a substrate, forming a groove with a preset depth on a high-voltage device region on the substrate, and removing a first photoresist layer; shallow trench isolation is formed on the substrate to define an active region, a doped well of a high-voltage device region is formed through ion implantation, the shallow trench isolation used for defining the active region of the high-voltage device region is located at the edge of a trench, and the bottom end of the shallow trench isolation is deeper than other shallow trench isolation; forming a second photoresist layer covering the shallow trench isolation on the substrate, and photoetching to open the second photoresist layer on the high-voltage device region to expose the substrate and the shallow trench isolation on the second photoresist layer; and etching the exposed shallow trench isolation at the high-voltage region to a required height by utilizing an etching process of the shallow trench isolation relative to a high selection ratio of the substrate, and removing the second photoresist layer. According to the invention, the defects of a gate oxide layer embedding process can be improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for improving gate oxide layer buried process defects. Background Art

[0002] In the prior art, after the shallow trench isolation of the active area is formed and the well ion implantation of the HV (high voltage) MOS device is performed, a gate oxide layer buried process (HVOX Etch) is required, that is, the Si and STI (shallow trench isolation) in the HV device area are etched to a certain depth.

[0003] The existing gate oxide layer buried process has the following defects:

[0004] 1. When etching the silicon trench, due to the vertical blocking of STI, a certain amount of silicon residue will be formed at the junction of AA and STI. Trying to directly remove the lateral silicon residue by isotropic etching will cause the bottom of the silicon trench to become curved (bowl), which will greatly reduce the reliability of the final gate oxide layer. Simply adjusting the process parameters cannot achieve the formation of an ideal silicon trench. The silicon residue will cause a current tunneling effect and greatly reduce the reliability of the oxide layer. In severe cases, it will directly lead to device failure.

[0005] 2. In the manufacturing process, there is an AA / STI etching step after the AA is formed, which leads to a decrease in the STI trench depth and a decrease in the device's anti-punchback isolation performance;

[0006] 3. The dose of well ion implantation in the HVMOS region is also reduced due to the influence of AA etching.

[0007] In order to solve the above problems, it is necessary to propose a new method for improving the defects of the gate oxide layer buried process. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving defects in the gate oxide layer buried process, so as to solve the problem of defects in the gate oxide layer buried process in the prior art.

[0009] To achieve the above objectives and other related objectives, the present invention provides a method for improving gate oxide layer buried process defects, comprising:

[0010] Step 1, providing a substrate, forming a first photoresist layer on the substrate, photolithographically opening the first photoresist layer to define a formation position of a groove on the high-voltage device area, forming a groove of a preset depth on the high-voltage device area on the substrate by an etching method, and removing the first photoresist layer;

[0011] Step 2: forming shallow trench isolation on the substrate to define an active area, and forming a doped well in the high-voltage device area by ion implantation, wherein the shallow trench isolation for defining the active area of ​​the high-voltage device area is located at the edge of the trench, and its bottom end is deeper than the other shallow trench isolations;

[0012] Step 3, forming a second photoresist layer covering the shallow trench isolation on the substrate, and photolithographically opening the second photoresist layer on the high-voltage device region to expose the substrate and the shallow trench isolation thereon;

[0013] Step 4: using an etching process with a high selectivity ratio of the shallow trench isolation relative to the substrate, etching the shallow trench isolation exposed at the high-voltage area to a desired height, and removing the second photoresist layer.

[0014] Preferably, the substrate in step one is a silicon substrate.

[0015] Preferably, a hard mask layer is formed on the substrate in step one before the first photoresist layer.

[0016] Preferably, the hard mask layer in step one is an oxide layer.

[0017] Preferably, the etching method in step one is dry etching.

[0018] Preferably, in step one, the first photoresist layer is removed by using an ashing process and a wet cleaning method.

[0019] Preferably, the shallow trench isolation material in step 2 is spin-on-glass, dense oxide formed by high-density plasma chemical vapor deposition, silicon dioxide, or double filling of silicon dioxide and silicon nitride.

[0020] Preferably, in step four, the second photoresist layer is removed by using an ashing process and a wet cleaning method.

[0021] As described above, the method of improving the gate oxide layer buried process defects of the present invention has the following beneficial effects:

[0022] The present invention defines a shallow trench isolation depth in an active area of ​​a high-voltage device area that is deeper, and in subsequent etching, the final depth of the shallow trench isolation in the high-voltage device area can be increased, thereby enhancing the device's isolation performance against punch-through. Since the shallow trench isolation is formed after the trench is formed, no silicon residue will be formed at the junction of the active area and the shallow trench isolation, thereby improving the reliability of subsequent oxide layer formation. The dose of the doped well in the high-voltage device area will not be lost due to the influence of etching the active area, thereby improving the stability of device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram showing defects of the gate oxide layer buried process in the prior art;

[0024] Figure 2 Shown is a schematic diagram of the process flow of the present invention;

[0025] Figure 3 It is a schematic diagram showing the photolithography process of opening the first photoresist layer to define the formation position of the groove on the high-voltage device region according to the present invention;

[0026] Figure 4 It is a schematic diagram showing the formation of a groove of a preset depth according to the present invention;

[0027] Figure 5 It is a schematic diagram of forming shallow trench isolation according to the present invention;

[0028] Figure 6 It is a schematic diagram showing the second photoresist layer on the high voltage device region opened by photolithography according to the present invention;

[0029] Figure 7 It is a schematic diagram showing etching the exposed shallow trench isolation at the high pressure area to a desired height according to the present invention. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] See also Figure 2 The present invention provides a method for improving gate oxide layer buried process defects, comprising:

[0032] Step 1: Provide a substrate 101, form a first photoresist layer 103 on the substrate 101, and open the first photoresist layer 103 by photolithography to define the formation position of the groove on the high-voltage device area, so as to form Figure 3 The structure shown in FIG. 1 is formed by etching a groove of a preset depth on the high voltage device region on the substrate 101, and the first photoresist layer 103 is removed to form a structure as shown in FIG. Figure 4 The structure shown;

[0033] In an embodiment of the present invention, the substrate 101 in step 1 is a silicon substrate 101 .

[0034] In an embodiment of the present invention, a hard mask layer 102 is formed on the substrate 101 in step one before the first photoresist layer 103 .

[0035] In an embodiment of the present invention, the hard mask layer 102 in step 1 is an oxide layer, which can be formed by thermal oxidation, chemical vapor deposition, physical vapor deposition, etc.

[0036] In an embodiment of the present invention, the etching method in step 1 is dry etching.

[0037] In an embodiment of the present invention, in step 1, the first photoresist layer 103 is removed by using an ashing process and a wet cleaning method.

[0038] Step 2: forming a shallow trench isolation 104 on the substrate 101 to define an active area, and forming a doped well 105 in the high voltage device area by ion implantation, wherein the shallow trench isolation 104 used to define the active area of ​​the high voltage device area is located at the edge of the trench, and its bottom end is deeper than other shallow trench isolations 104, forming a doped well 105 in the high voltage device area. Figure 5 The structure shown can be formed in different shallow trench isolation 104 formation processes. Since the shallow trench isolation 104 of the active area defining the high-voltage device area is deep, the final depth of the shallow trench isolation 104 of the high-voltage device area can be increased in the subsequent etching, and the device's anti-breakthrough isolation performance is enhanced; since the shallow trench isolation 104 is formed after the trench is formed, silicon residue will not be formed at the junction of the active area and the shallow trench isolation 104, thereby improving the reliability of the subsequent formation of the oxide layer;

[0039] In an embodiment of the present invention, the material of the shallow trench isolation 104 in step 2 is spin-on-glass, dense oxide formed by high-density plasma chemical vapor deposition, silicon dioxide, or double filling of silicon dioxide and silicon nitride.

[0040] Step 3: Form a second photoresist layer 106 covering the shallow trench isolation 104 on the substrate 101, and photolithographically open the second photoresist layer 106 on the high-voltage device region to expose the substrate 101 and the shallow trench isolation 104 thereon, so as to form a Figure 6 The structure shown;

[0041] Step 4: Using an etching process with a high selectivity ratio of the shallow trench isolation 104 to the substrate 101, the exposed shallow trench isolation 104 at the high voltage area is etched to a desired height. The etching method can be dry etching or wet etching to remove the second photoresist layer 106 to form a Figure 7 By reducing the etching of the doped well 105 area, the dose of the doped well 105 in the high-voltage device area will not be lost due to the etching of the active area, thereby improving the stability of device performance.

[0042] In an embodiment of the present invention, in step 4, the second photoresist layer 106 is removed by using an ashing process and a wet cleaning method.

[0043] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] In summary, the present invention defines a shallow trench isolation depth in the active area of ​​the high-voltage device area as being deeper, which can increase the final depth of the shallow trench isolation in the high-voltage device area in subsequent etching, and enhance the device's isolation performance against punch-through; since the formation of the shallow trench isolation is after the formation of the trench, no silicon residue will be formed at the junction of the active area and the shallow trench isolation, thereby improving the reliability of the subsequent formation of the oxide layer; the dose of the doped well in the high-voltage device area will not be lost due to the influence of the etching of the active area, thereby improving the stability of the device performance. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0045] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving gate oxide layer buried process defects, characterized in that: At least: Step 1, providing a substrate, forming a first photoresist layer on the substrate, photolithographically opening the first photoresist layer to define a formation position of a groove on the high-voltage device area, forming a groove of a preset depth on the high-voltage device area on the substrate by an etching method, and removing the first photoresist layer; Step 2: forming shallow trench isolation on the substrate to define an active area, and forming a doped well in the high-voltage device area by ion implantation, wherein the shallow trench isolation for defining the active area of ​​the high-voltage device area is located at the edge of the trench, and its bottom end is deeper than the other shallow trench isolations; Step 3, forming a second photoresist layer covering the shallow trench isolation on the substrate, and photolithographically opening the second photoresist layer on the high-voltage device region to expose the substrate and the shallow trench isolation thereon; Step 4: using an etching process with a high selectivity ratio of the shallow trench isolation relative to the substrate, etching the shallow trench isolation exposed at the high-voltage area to a desired height, and removing the second photoresist layer.

2. The method for improving gate oxide layer buried process defects according to claim 1, characterized in that: The substrate in step one is a silicon substrate.

3. The method for improving gate oxide layer buried process defects according to claim 1, characterized in that: In step one, a hard mask layer is formed on the substrate before the first photoresist layer.

4. The method for improving gate oxide layer buried process defects according to claim 3, characterized in that: The hard mask layer in step one is an oxide layer.

5. The method for improving gate oxide layer buried process defects according to claim 1, characterized in that: The etching method in step one is dry etching.

6. The method for improving gate oxide layer buried process defects according to claim 1, characterized in that: In step one, the first photoresist layer is removed by using an ashing process and a wet cleaning method.

7. The method for improving gate oxide layer buried process defects according to claim 1, characterized in that: The material of the shallow trench isolation in step 2 is spin-on glass, dense oxide formed by high-density plasma chemical vapor deposition, silicon dioxide, or double filling of silicon dioxide and silicon nitride.

8. The method for improving gate oxide layer buried process defects according to claim 1, characterized in that: In step 4, the second photoresist layer is removed by using an ashing process and a wet cleaning method.

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