Method for manufacturing interconnection structure

Abstract

A method of fabricating an interconnect structure includes: forming a first patterned photoresist on a bottom metal layer; etching the bottom metal layer to form first and second lower metal patterns; partially anodizing the etched bottom metal layer; removing the first patterning photoresist to expose the surface part, which is not anodized, of the second lower metal pattern; depositing a conductive layer on the anodized bottom metal layer to contact the surface portion; and etching the conductive layer through a second patterned photoresist to form a first upper conductive pattern over the first lower metal pattern and electrically isolated from the first lower metal pattern and a second upper conductive pattern over the second lower metal pattern and contacting the surface portion, wherein the first and second upper conductive patterns completely cover all non-insulating top surfaces of the anodized bottom metal layer. And only two groups of PEP processes are adopted, so that the manufacturing cost can be obviously reduced, and the manufacturing efficiency can be effectively improved.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing an interconnect structure. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

[0003] Traditional display manufacturing is a standardized process. In recent years, new types of displays such as micro LED displays, mini LED displays, quantum dot LED displays, etc. have emerged and are expected to dominate the display field. The process of making a display includes many steps. Reducing one of the steps can reduce costs and improve efficiency. Summary of the invention

[0004] According to some embodiments of the present disclosure, a method for manufacturing an interconnect structure includes: forming a first patterned photoresist on a bottom metal layer having an aluminum atomic ratio greater than 80%, wherein the first patterned photoresist has a first shielding portion and a second shielding portion that is thicker than the first shielding portion; etching the bottom metal layer through the first patterned photoresist to form a first lower metal pattern and a second lower metal pattern respectively covered by the first shielding portion and the second shielding portion; removing the first shielding portion; anodizing the etched bottom metal layer, wherein the anodized bottom metal layer has an unanodized portion after anodization; removing the second shielding portion to expose The second lower metal pattern has a surface portion that is not anodized; a conductive layer is deposited on the anodized bottom metal layer, wherein the conductive layer contacts the surface portion of the second lower metal pattern; and the conductive layer is etched through a second patterned photoresist to form a first upper conductive pattern and a second upper conductive pattern, wherein the first upper conductive pattern is above the first lower metal pattern and is electrically isolated from the first lower metal pattern by the anodized portion of the bottom metal layer, the second upper conductive pattern is above the second lower metal pattern and contacts the surface portion of the second lower metal pattern, and the first upper conductive pattern and the second upper conductive pattern completely cover all non-insulated top surfaces of the anodized bottom metal layer.

[0005] In one or more embodiments of the present disclosure, anodizing the etched bottom metal layer is performed to achieve a termination voltage. The first upper conductive pattern and the second upper conductive pattern each have a thickness and a width. The termination voltage is less than the minimum of the thickness and the width in nm divided by 0.9 nm-V -1 .

[0006] In one or more embodiments of the present disclosure, the thickness of the unanodized portion of the etched bottom metal layer after anodization is equal to or greater than 1 / 10 of the thickness of the etched bottom metal layer before anodization.

[0007] In one or more embodiments of the present disclosure, the bottom metal layer includes a first sub-layer and a second sub-layer. The first sub-layer contains aluminum. The second sub-layer is on the first sub-layer and contacts the first sub-layer.

[0008] In one or more embodiments of the present disclosure, the method further includes: etching the second sub-layer selectively relative to the first sub-layer after removing the first shielding portion and before anodizing the etched bottom metal layer.

[0009] In one or more embodiments of the present disclosure, the second sub-layer contains molybdenum.

[0010] In one or more embodiments of the present disclosure, anodizing the etched bottom metal layer is performed by applying 0.05 mA / cm 2 With 5mA / cm 2 It is executed with a constant current between the

[0011] In one or more embodiments of the present disclosure, anodizing the etched bottom metal layer uses an electrolyte having a pH value between pH 5 and pH 8.

[0012] In one or more embodiments of the present disclosure, the etching selectivity of the conductive layer to the anodized portion of the etched bottom metal layer in etching is higher than 5.0. In one or more embodiments of the present disclosure, depositing the conductive layer includes: depositing a semiconductive layer on the anodized bottom metal layer; and depositing a top metal layer on the semiconductive layer. The method further includes: removing a portion of the second patterned photoresist to expose a surface portion of the top metal layer after etching the conductive layer; and anodizing the surface portion of the top metal layer until the top metal layer has an anodized segment extending from the surface portion of the top metal layer to a surface of the top metal layer in contact with the semiconductive layer.

[0013] In one or more embodiments of the present disclosure, the top metal layer includes a first sub-layer and a second sub-layer. The first sub-layer contains aluminum. The second sub-layer is on the first sub-layer and contacts the first sub-layer.

[0014] In one or more embodiments of the present disclosure, the second sub-layer contains copper.

[0015] In one or more embodiments of the present disclosure, the surface of the top metal layer in contact with the semiconductive layer contains aluminum.

[0016] In one or more embodiments of the present disclosure, the aluminum atomic ratio of the top metal layer is greater than 80%.

[0017] In one or more embodiments of the present disclosure, the method further comprises: annealing the semiconducting layer.

[0018] In one or more embodiments of the present disclosure, the thickness of the semiconductive layer is equal to or less than 100 μm.

[0019] In one or more embodiments of the present disclosure, depositing a conductive layer includes: depositing a semiconductive layer on the anodized bottom metal layer; and depositing a top metal layer on the semiconductive layer. The method further includes: before etching the conductive layer, anodizing the top metal layer through a first hollow portion of a second patterned photoresist; and after anodizing the top metal layer, forming a second hollow portion in the second patterned photoresist. Etching the conductive layer includes etching the conductive layer through the second hollow portion to form a first upper conductive pattern and a second upper conductive pattern.

[0020] The above description is only used to illustrate the problem to be solved by the present disclosure, the technical means to solve the problem, and the effects produced, etc. The specific details of the present disclosure will be described in detail in the following implementation methods and related drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows:

[0022] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H as well as Fig. 1I The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure.

[0023] Figure 2 Schematic diagrams showing cross-sections of the first lower metal pattern before and after anodization according to some embodiments of the present disclosure.

[0024] Figure 3A A partial top view of an interconnect structure according to some embodiments of the present disclosure is shown.

[0025] Figure 3B To illustrate some embodiments of the present disclosure Figure 3A A partial cross-sectional view of the interconnect structure along line segment 3B-3B.

[0026] Figure 3C A partial top view of an interconnect structure according to some embodiments of the present disclosure is shown.

[0027] Figure 3D To illustrate some embodiments of the present disclosure Figure 3C A local cross-sectional view of the interconnect structure along line segment 3D-3D.

[0028] Figure 4A , Figure 4B , Figure 4C , Figure 4D as well as Figure 4E The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure.

[0029] Figure 5 To illustrate some embodiments of the present disclosure Figure 4E A partial top view of the structure shown in FIG.

[0030] Fig. 6A To illustrate some embodiments of the present disclosure Figure 4E Another partial top view of the structure shown in .

[0031] Figure 6B To illustrate some embodiments of the present disclosure Figure 4E Another partial top view of the structure shown in .

[0032] Figure 6C To illustrate some embodiments of the present disclosure Figure 4E Another partial top view of the structure shown in .

[0033] Fig. 7A , Figure 7B , Figure 7C , Fig.7D as well as Fig. 7E The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure.

[0034] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E as well as Figure 8F The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure.

[0035] Fig.9A , Fig. 9B as well as Fig. 9C The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure.

[0036] Reference numerals:

[0037] A: Semiconductor layer

[0038] A1: Active area

[0039] A2: Inactive area

[0040] AD: Anodized part

[0041] BM, BM', BM-1, BM-1': bottom metal layer

[0042] C: Anodizing Section

[0043] DE: Drain

[0044] E1: First exposure dose

[0045] E2: Second exposure dose

[0046] H1: The first hollow part

[0047] H2: The second hollow part

[0048] LP1: First metal pattern

[0049] LP2: Second metal pattern

[0050] PR: Photoresist

[0051] PR1: First patterned photoresist

[0052] PR11, PR21: First shielding part

[0053] PR12, PR22: Second shielding position

[0054] PR2: Second patterned photoresist

[0055] S1, S2, S3, S4: surface area

[0056] SE: Source

[0057] SL1: First sublayer

[0058] SL2: Second sublayer

[0059] SL3: The third sublayer

[0060] SUB: Substrate

[0061] T1, T2, T3: thickness

[0062] TM: Top Metal Layer

[0063] UP1: First upper metal pattern

[0064] UP2: Second upper metal pattern

[0065] UP3: The third upper metal pattern

[0066] W1,W2: Width DETAILED DESCRIPTION

[0067] The following will disclose multiple embodiments of the present disclosure with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some known conventional structures and components will be depicted in a simple schematic manner in the drawings.

[0068] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be implemented without one or more of these specific details, or in combination with other known methods and configurations. In the following description, many specific details, such as specific configurations, dimensions, and processes, etc., are described to provide a thorough understanding of the present disclosure. In other cases, known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the present disclosure. References throughout this specification to "one embodiment", "some embodiments", etc. mean that specific features, structures, configurations, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, phrases "in one embodiment", "according to some embodiments", etc., which appear throughout this specification, do not necessarily refer to the same embodiment of the present disclosure. In addition, specific features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0069] Please refer to Figure 1A . Figure 1A Schematic cross-sectional view showing an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 1A As shown, a bottom metal layer BM is formed on a substrate SUB, and a photoresist PR is formed on the bottom metal layer BM. The atomic ratio of aluminum in the bottom metal layer BM is greater than 80%. The material of the photoresist PR is a positive photoresist. The first area of ​​the photoresist PR is exposed to light of a first exposure dose E1. The second area of ​​the photoresist PR is exposed to light of a second exposure dose E2 less than the first exposure dose E1. The third area of ​​the photoresist PR is not exposed. In some embodiments, UV light may be used to expose the photoresist PR, but the present disclosure is not limited thereto. In some embodiments, a grayscale mask (or halftone mask) may be used to expose the photoresist PR. For example, the halftone mask may include a fully exposed portion of the full intensity of the transmitted light (i.e., the first exposure dose E1), a halftone portion of the transmitted partial light (e.g., the second exposure dose E2, which may be 20% to 60% of the first exposure dose E1), and a full-tone portion that completely blocks the light.

[0070] Please refer to Figure 1B . Figure 1BThe diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 1A The intermediate stages shown can be followed in sequence by Figure 1B The intermediate stage shown. Figure 1B As shown, the exposed photoresist PR is then developed to form a first patterned photoresist PR1. The first patterned photoresist PR1 has a first shielding portion PR11 and a second shielding portion PR12. The second shielding portion PR12 is thicker than the first shielding portion PR11. It can be seen that the area where the photoresist PR is exposed with the first exposure dose E1 will be completely removed, the area where the photoresist PR is exposed with the second exposure dose E2 will be partially removed to form the first shielding portion PR11, and the area where the photoresist PR is not exposed will be retained originally to form the second shielding portion PR12.

[0071] Please refer to Figure 1C . Figure 1C The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 1B The intermediate stages shown can be followed in sequence by Figure 1C The intermediate stage shown. Figure 1C As shown, the bottom metal layer BM is etched through the first patterned photoresist PR1 to form a first lower metal pattern LP1 and a second lower metal pattern LP2 covered by the first shielding portion PR11 and the second shielding portion PR12 , respectively.

[0072] In some embodiments, a wet etching process may be performed to etch the bottom metal layer BM. In some embodiments, a PAN etchant (a mixture of phosphoric acid, acetic acid, nitric acid, and water) may be used in the wet etching process. For example, the mixing ratio of phosphoric acid, acetic acid, nitric acid, and water may be 16:1:1:2, but the present disclosure is not limited thereto. In some embodiments, hydrogen peroxide and sulfuric acid may be used in the wet etching process.

[0073] In some embodiments, a dry etching process may be performed to etch the bottom metal layer BM. For example, the dry etching process may be performed using, for example, Cl 2 and BCl 3 The invention relates to an enhanced capacitance coupled plasma (ECCP) process, but the present disclosure is not limited thereto.

[0074] Please refer to Figure 1D . Figure 1D The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 1C The intermediate stages shown can be followed in sequence by Figure 1D The intermediate stage shown. Figure 1D As shown, the first shielding portion PR11 is removed to expose the top surface of the first lower metal pattern LP1. In some embodiments, an ashing process is performed on the first shielding portion PR11 and the second shielding portion PR12 until the first shielding portion PR11 is completely removed and the second shielding portion PR12 still covers the top surface of the second lower metal pattern LP2. In some embodiments, oxygen plasma is used in the ashing process to perform etching of the first shielding portion PR11 and the second shielding portion PR12.

[0075] Please refer to Figure 1E . Figure 1E The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 1D The intermediate stages shown can be followed in sequence by Figure 1E The intermediate stage shown. Figure 1E As shown, the etched bottom metal layer BM' is anodized. The first lower metal pattern LP1 and the second lower metal pattern LP2 are partially anodized after anodization, and thus have an anodized portion AD (i.e., anodized). The anodized second lower metal pattern LP2 has a surface portion S1 that is not anodized and contacts the second shielding portion PR12.

[0076] In some embodiments, the etched bottom metal layer BM' is anodized to achieve a termination voltage. The first lower metal pattern LP1 and the second lower metal pattern LP2 each have a thickness T1 (e.g., the vertical length of the first lower metal pattern LP1 in FIG. 1D) and a width W1 (e.g., the lateral length of the first lower metal pattern LP1 in FIG. 1D) before being anodized, and the termination voltage is less than the smallest of the thickness T1 and the width W1 in nm divided by 0.9 nm-V -1 In this way, the etched bottom metal layer BM' will not be fully anodized and leave a conductive portion.

[0077] In some embodiments, the width W1 of the first lower metal pattern LP1 is greater than the thickness T1 of the first lower metal pattern LP1, but the present disclosure is not limited thereto. In some embodiments, the termination voltage reached by anodization of the etched bottom metal layer BM' is greater than 10 volts and less than 500 volts. It should be noted that if the etched bottom metal layer BM' is anodized to reach a termination voltage greater than 500 volts, the anodized portion AD of the etched bottom metal layer BM' (for example, the anodized portion AD of the first lower metal pattern LP1) may be too thick, resulting in a high operating voltage of the thin film transistor. In some embodiments, the etched bottom metal layer BM' is anodized by applying a voltage greater than 0.5 mA / cm 2In some embodiments, the constant current is 0.05 mA / cm 2 With 5mA / cm 2 between.

[0078] In some embodiments, the etched bottom metal layer BM' is anodized until a termination voltage is reached and maintained for at least 300 seconds. This makes the thickness of the anodized portion AD of the etched bottom metal layer BM' more uniform. In some embodiments, an annealing process may be performed on the anodized bottom metal layer BM'. In this way, the resistance of the anodized bottom metal layer BM' (for example, the anodized portion AD of the anodized first lower metal pattern LP1) to the second wet etching process (if any) can be increased. In some embodiments, the annealing temperature used in the annealing process is greater than 200°C, but the present disclosure is not limited to this.

[0079] In some embodiments, the etched bottom metal layer BM' is anodized using an electrolyte having a pH value between pH 5 and pH 8. It should be noted that if the pH value is less than pH 5 or greater than pH 8, more pores will appear in the anodized portion AD of the etched bottom metal layer BM'.

[0080] In some embodiments, the etched bottom metal layer BM' is anodized using an electrolyte containing less than 45 wt% of water. As a result, the hydrogen content in the anodized portion AD of the etched bottom metal layer BM' can be very small. The hydrogen content can reduce the breakdown voltage of the gate insulator. Hydrogen sometimes affects the semiconductor layer A (described below) and reduces its stability.

[0081] In some embodiments, the etched bottom metal layer BM' is anodized using an electrolyte containing water, ethylene glycol, and ammonium tartrate. For example, the electrolyte may contain about 68.5 wt% ethylene glycol, about 30 wt% water, and about 1.5 wt% ammonium tartrate, but the present disclosure is not limited thereto.

[0082] In some embodiments, the etched bottom metal layer BM' is anodized at a temperature below 15°C. In this way, the anodized portion AD of the etched bottom metal layer BM' is more dense, thereby improving the quality. Figure 2 . Figure 2 Schematic diagrams showing cross-sections of the first lower metal pattern LP1 before and after anodization according to some embodiments of the present disclosure. Figure 2As shown, in some embodiments, the thickness T2 of the unanodized portion of the anodized first lower metal pattern LP1 is equal to or greater than 1 / 10 of the thickness of the first lower metal pattern LP1 before the etched bottom metal layer BM' is anodized. In this way, the resistance of the etched bottom metal layer BM' will not be too large.

[0083] Please refer to Figure 1F . Figure 1F The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 1E The intermediate stages shown can be followed in sequence by Figure 1F The intermediate stage shown. Figure 1F As shown, the second shielding portion PR12 is removed to expose the unanodized surface portion S1 of the second lower metal pattern LP2.

[0084] Please refer to Figure 1G . Figure 1G The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 1F The intermediate stages shown can be followed in sequence by Figure 1G The intermediate stage shown. Figure 1G As shown, the top metal layer TM is deposited on the anodized bottom metal layer BM', wherein the top metal layer TM contacts the surface portion S1 of the second lower metal pattern LP2. In addition, the second patterned photoresist PR2 is deposited on the top metal layer TM. The second patterned photoresist PR2 has a first shielding portion PR21 and a second shielding portion PR22 above the first lower metal pattern LP1 and the second lower metal pattern LP2, respectively. In some embodiments, the surface portion S1 of the second lower metal pattern LP2 overlaps the vertical projection of the second shielding portion PR22 on the surface portion S1.

[0085] Please refer to Figure 1H . Figure 1H The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 1G The intermediate stages shown can be followed in sequence by Figure 1H The intermediate stage shown. Figure 1HAs shown, the top metal layer TM is etched through the second shielding portion PR22 to form a first upper metal pattern UP1 and a second upper metal pattern UP2. The first upper metal pattern UP1 is above the first lower metal pattern LP1 and is electrically isolated from the first lower metal pattern LP1 by the anodized portion AD therebetween. The second upper metal pattern UP2 is above the second lower metal pattern LP2 and contacts the surface portion S1 of the second lower metal pattern LP2. The first upper metal pattern UP1 and the second upper metal pattern UP2 completely cover all non-insulated top surfaces of the anodized bottom metal layer BM'.

[0086] In some embodiments, the etching selectivity ratio of the top metal layer TM to the etched anodized portion AD of the bottom metal layer BM′ in the step of etching the top metal layer TM is higher than 5.0.

[0087] Please refer to Fig. 1I . Fig. 1I The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 1H The intermediate stages shown can be followed in sequence by Fig. 1I The intermediate stage shown. Fig. 1I As shown, the second shielding portion PR22 is completely removed, so that the first lower metal pattern LP1 and the first upper metal pattern UP1 form a metal crossing structure, and the second lower metal pattern LP2 and the second upper metal pattern UP2 form a contact structure.

[0088] Please refer to Figure 3A as well as Figure 3B . Figure 3A A partial top view of an interconnect structure according to some embodiments of the present disclosure is shown. Figure 3B To illustrate some embodiments of the present disclosure Figure 3A A partial cross-sectional view of the interconnect structure along line segment 3B-3B. Figure 3A and Figure 3B As shown, the first lower metal pattern LP1 is separated and extends between the two second lower metal patterns LP2. The first upper metal pattern UP1 extends across the top of the first lower metal pattern LP1 and is located between the two second upper metal patterns UP2. The two second upper metal patterns UP2 respectively cover the two second lower metal patterns LP2 and contact the surface parts S1 of the two second lower metal patterns LP2 without exposing the surface parts S1. In this way, the two second lower metal patterns LP2 respectively located on the opposite sides of the first lower metal pattern LP1 can be electrically connected to the combination of the two second upper metal patterns UP2 through the upper first upper metal pattern UP1, so that an interconnection structure can be formed by the combination.

[0089] Please refer to Figure 3C as well as Figure 3D . Figure 3CA partial top view of an interconnect structure according to some embodiments of the present disclosure is shown. Figure 3D To illustrate some embodiments of the present disclosure Figure 3C A local cross-sectional view of the interconnect structure along line segment 3D-3D. Figure 3A and Figure 3B The interconnection structure shown in the figure is partially presented in Figure 3C and Figure 3D Specifically, Figure 3C and Figure 3D The first upper metal pattern UP1 of the interconnection structure is presented without the second upper metal pattern UP2. In addition, the anodized portion AD of the first lower metal pattern LP1 after anodization exposes two surface portions S2 of the first lower metal pattern LP1, and the first upper metal pattern UP1 is located between the two surface portions S2. The two third upper metal patterns UP3 respectively cover and contact the surface portions S2 of the first lower metal pattern LP1 without exposing the surface portions S2. It should be noted that the two third upper metal patterns UP3 can also be formed by the top metal layer TM. Figure 3A and Figure 3B Compared with the first lower metal pattern LP1 shown in FIG. 1 , the two third upper metal patterns UP3 can further increase Figure 3C and Figure 3D The conductivity of the first lower metal pattern LP1 is shown.

[0090] From this, it can be seen FIG. 1A to FIG. 1I The method for manufacturing the interconnection structure of the embodiment shown only uses two groups of PEP (Photo Engraving Process) processes, so the cost of manufacturing the interconnection structure can be significantly reduced and the manufacturing efficiency can be effectively improved.

[0091] In some embodiments, the method of manufacturing an interconnect structure disclosed herein can be used to manufacture a thin film transistor, which can be FIG. 4A to FIG. 4E Example.

[0092] Please refer to Figure 4A . Figure 4A A cross-sectional schematic diagram illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. In order to further manufacture a thin film transistor, Figure 1F The intermediate stages shown can be followed in sequence by Figure 4A The intermediate stage shown. Figure 4A As shown, the semiconductor layer A is deposited on the anodized bottom metal layer BM' to cover the first lower metal pattern LP1 and the second lower metal pattern LP2, so that the first lower metal pattern LP1 and the second lower metal pattern LP2 contact the semiconductor layer A. The first lower metal pattern LP1 serves as a gate electrode, and the anodized portion AD of the anodized first lower metal pattern LP1 serves as a gate insulator.

[0093] In some embodiments, the semiconductor layer A is an oxide semiconductor layer. In addition, the semiconductor layer A includes at least one element selected from aluminum, gallium, indium, zinc, tin, and zirconium, but the present disclosure is not limited thereto. In some embodiments, the semiconductor layer A includes MoS 2 .

[0094] In some embodiments, the semiconductor layer A may be deposited by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process.

[0095] In some embodiments, the semiconductor layer A may be a multilayer structure including different components. For example, the semiconductor layer A may be a double-layer structure including indium gallium zinc oxide (IZO) and indium gallium zinc tin oxide (IGZTO), but the present disclosure is not limited thereto. In this way, the channel mobility may be improved.

[0096] like Figure 4A As shown, the top metal layer TM is deposited on the semiconductor layer A. It should be noted that the surface of the top metal layer TM in contact with the semiconductor layer A contains a metal (such as aluminum) that can be anodized. The combination of the semiconductor layer A and the top metal layer TM serves as a conductive layer. The second patterned photoresist PR2 is formed on the top metal layer TM. The formation method of the second patterned photoresist PR2 can be the same as or similar to the formation method of the first patterned photoresist PR1, so the formation of the second patterned photoresist PR2 can refer to the relevant Figure 1A and Figure 1B The second patterned photoresist PR2 has a first hollow portion H1 exposing a surface portion S3 of the top metal layer TM.

[0097] In some embodiments, the step of depositing the semiconductor layer A and the step of depositing the top metal layer TM are performed continuously in a vacuum. That is, before depositing the top metal layer TM, the semiconductor layer A is not in contact with the atmosphere. In some embodiments, the step of depositing the semiconductor layer A and the step of depositing the top metal layer TM are performed in a chamber and transferred in a vacuum. In this way, the oxidized semiconductor layer A can be prevented from contacting the air.

[0098] Please refer to Figure 4B . Figure 4B The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 4A The intermediate stages shown can be followed in sequence by Figure 4B The intermediate stage shown. Figure 4B As shown, and refer to Figure 4A , the surface portion S3 of the top metal layer TM is anodized through the second patterned photoresist PR2 until the top metal layer TM has an anodized segment C (i.e., an anodic oxide) extending from the surface portion S3 of the top metal layer TM to the side of the top metal layer TM facing the semiconductor layer A. As described above, the surface of the top metal layer TM in contact with the semiconductor layer A contains an anodizable metal (e.g., aluminum), so the top metal layer TM can be anodized to extend the anodized segment C to the side of the top metal layer TM facing the semiconductor layer A.

[0099] In some embodiments, the surface portion S3 of the top metal layer TM is anodized to achieve a termination voltage. The top metal layer TM has a thickness T2 before being anodized. The termination voltage is greater than the thickness T2 in nm divided by 1.0 nm-V -1 In this way, it can be ensured that the anodized segment C can reach the side of the top metal layer TM facing the semiconductor layer A.

[0100] In some embodiments, Figure 4B As shown, the semiconductor layer A has an active area A1 and an inactive area A2. The active area A1 is covered and contacted by the anodized segment C. The active area A1 can be defined by the vertical projection of the anodized segment C onto the semiconductor layer A. The inactive area A2 is covered and contacted by other conductive segments of the top metal layer TM. In order to reduce the contact resistance of the inactive area A2 relative to the top metal layer TM, an annealing process can be performed to react the inactive area A2 with the aluminum in the top metal layer TM. Aluminum increases the oxygen vacancies in the inactive area A2 of the semiconductor layer A. The annealing process also improves the stability of the active area A1 of the semiconductor layer A.

[0101] Please refer to Figure 4C . Figure 4C The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 4B The intermediate stages shown can be followed in sequence by Figure 4C The intermediate stage shown. Figure 4C As shown, the second hollow portion H2 is formed in the second patterned photoresist PR2. In some embodiments, an ashing process is performed on the second patterned photoresist PR2 until the second hollow portion H2 is formed to expose a portion of the top metal layer TM. In some embodiments, oxygen plasma is used in the ashing process to perform etching of the second patterned photoresist PR2.

[0102] Please refer to Figure 4D . Figure 4D The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 4CThe intermediate stages shown can be followed in sequence by Figure 4D The intermediate stage shown. Figure 4D As shown, the top metal layer TM is etched through the second hollow portion H2 to form a first upper metal pattern UP1 and a second upper metal pattern UP2. The first upper metal pattern UP1 is above the anodized first lower metal pattern LP1 and has a drain DE and a source SE. The drain DE and the source SE are connected to the anodized segment C and are electrically isolated from each other by the anodized segment C. The anodized segment C serves as a channel protection structure. The second upper metal pattern UP2 is above the second lower metal pattern LP2. The second upper metal pattern UP2 forms a contact structure with the second lower metal pattern LP2.

[0103] In some embodiments, the etching selectivity ratio between the top metal layer TM and the anodized section C in the step of etching the top metal layer TM (as shown in FIG. 4D ) is higher than 2.0.

[0104] Please refer to Figure 4E . Figure 4E The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 4D The intermediate stages shown can be followed in sequence by Figure 4E The intermediate stage shown. Figure 4E As shown, the second patterned photoresist PR2 is removed to expose the first upper metal pattern UP1 and the second upper metal pattern UP2.

[0105] In some embodiments, the thickness of the semiconductor layer A is less than 100 nm. In this way, back channel leakage can be reduced in some cases. In addition, the problem of excessive contact resistance between the semiconductor layer A and other layers in contact with the semiconductor layer A (i.e., the second lower metal pattern LP2, the second upper metal pattern UP2, the drain DE and the source SE) can be avoided.

[0106] Please refer to Figure 5 as well as Fig. 6A . Figure 5 and Fig. 6A To illustrate some embodiments of the present disclosure Figure 4E A partial top view of the structure shown in FIG. Figure 5 A partial schematic diagram of the anodized first lower metal pattern LP1 (covered by the anodized portion AD) and the first upper metal pattern UP1 is presented. Fig. 6A A partial schematic diagram of an anodized second lower metal pattern LP2 (covered by the anodized portion AD and exposing the surface portion S1 ) and a second upper metal pattern UP2 forming the aforementioned contact structure is presented.

[0107] Please refer to Figure 6B . Figure 6BTo illustrate some embodiments of the present disclosure Figure 4E Another partial top view of the structure shown in FIG. Figure 6B As shown, the surface portion S1 of the second lower metal pattern LP2 exposed by the anodized portion AD has a Fig. 6A Smaller area shown.

[0108] Please refer to Figure 6C . Figure 6C To illustrate some embodiments of the present disclosure Figure 4E Another partial top view of the structure shown in FIG. Figure 6C As shown, the surface portion S1 of the second lower metal pattern LP2 exposed by the anodized portion AD and the second upper metal pattern UP2 covering the second lower metal pattern LP2 both extend along the second lower metal pattern LP2.

[0109] From this, it can be seen FIG. 1A to FIG. 1I and FIG. 4A to FIG. 4E The method for manufacturing an interconnect structure of the embodiment shown can manufacture a thin film transistor using only two sets of PEPs, thus significantly reducing the manufacturing cost of the thin film transistor and effectively improving the manufacturing efficiency.

[0110] Please refer to Fig. 7A . Fig. 7A Schematic cross-sectional view showing an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. In some embodiments, Figure 1F The intermediate stage shown can be followed directly by Fig. 7A The intermediate stage shown. Fig. 7A As shown, the semiconductor layer A is deposited on the anodized bottom metal layer BM', and the top metal layer TM is deposited on the semiconductor layer A. The deposition method of the semiconductor layer A and the top metal layer TM can be the same or similar to Figure 4A The embodiment shown in FIG. Figure 4A The description is not repeated here.

[0111] like Fig. 7A As shown, the second patterned photoresist PR2 is formed on the top metal layer TM. The method for forming the second patterned photoresist PR2 may be the same as or similar to the method for forming the first patterned photoresist PR1, so the formation of the second patterned photoresist PR2 may refer to the description of FIG. 1A and FIG. 1B, and will not be repeated here. The second patterned photoresist PR2 has a first hollow portion H1 that exposes the top metal layer TM.

[0112] Please refer to Figure 7B . Figure 7B The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Fig. 7AThe intermediate stages shown can be followed in sequence by Figure 7B The intermediate stage shown. Figure 7B As shown, the top metal layer TM is etched through the second patterned photoresist PR2 to form a first upper metal pattern UP1 and a second upper metal pattern UP2. The first upper metal pattern UP1 is above the anodized first lower metal pattern LP1 and is covered by the first shielding portion PR21 of the second patterned photoresist PR2. The second upper metal pattern UP2 is above the anodized second lower metal pattern LP2 and is covered by the second shielding portion PR22 of the second patterned photoresist PR2.

[0113] Please refer to Figure 7C . Figure 7C The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 7B The intermediate stages shown can be followed in sequence Figure 7C The intermediate stage shown. Figure 7C As shown, a portion of the first shielding portion PR21 of the second patterned photoresist PR2 is removed to form a second hollow portion H2. The second hollow portion H2 exposes the surface portion S3 of the first upper metal pattern UP1. In some embodiments, an annealing process is performed on the second patterned photoresist PR2 until the second hollow portion H2 is formed to expose the surface portion S3 of the first upper metal pattern UP1. In some embodiments, oxygen plasma is used in the ashing process to perform etching of the second patterned photoresist PR2.

[0114] Please refer to Fig.7D . Fig.7D The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 7C The intermediate stages shown can be followed in sequence by Fig.7D The intermediate stage shown. Fig.7D As shown, the surface portion S3 of the first upper metal pattern UP1 is anodized until the first upper metal pattern UP1 has a drain DE, a source SE, and an anodized segment C connected between the drain DE and the source SE and electrically isolating the drain DE from the source SE. The anodized segment C serves as a channel protection structure. In some embodiments, the etched bottom metal layer BM' is anodized to reach a termination voltage. The first lower metal pattern LP1 has a thickness T1 (e.g., the vertical length of the first lower metal pattern LP1 in FIG. 1D) before being anodized, and the termination voltage is less than the thickness T1 in nm divided by 0.9nm-V -1 In this way, the etched bottom metal layer BM' will not be fully anodized and leave a conductive portion.

[0115] In some embodiments, the surface portion S3 of the first upper metal pattern UP1 is anodized to achieve a termination voltage. The first upper metal pattern UP1 has a width W2 and a thickness T3 before being anodized, as shown in FIG. 7C. The termination voltage is greater than the minimum of the width W2 and the thickness T3 in nm divided by 1.0 nm-V -1 In this way, it can be ensured that the anodized segment C can reach the side of the first upper metal pattern UP1 facing the semiconductor layer A, as shown in FIG. 7D .

[0116] Please refer to Fig. 7E . Fig. 7E The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Fig.7D The intermediate stages shown can be followed in sequence by Fig. 7E The intermediate stage shown. Fig. 7E As shown, the second patterned photoresist PR2 is removed to expose the first upper metal pattern UP1 and the second upper metal pattern UP2.

[0117] Please refer to Fig. 8A . Fig. 8A Schematic cross-sectional view showing an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. In some embodiments, Figure 1A The intermediate stage shown can be followed directly by Fig. 8A In other words, Figure 1A The bottom metal layer BM in is replaced by Fig. 8A The bottom metal layer BM-1 in Fig. 8A As shown, the bottom metal layer BM-1 is a multi-layer structure. Specifically, the bottom metal layer BM-1 includes a first sub-layer SL1, a second sub-layer SL2 and a third sub-layer SL3. The first sub-layer SL1 contains aluminum. The second sub-layer SL2 is stacked on the first sub-layer SL1. The third sub-layer SL3 is stacked on the second sub-layer SL2.

[0118] In some embodiments, the second sub-layer SL2 contains molybdenum, but the present disclosure is not limited thereto. The second sub-layer SL2 containing molybdenum can prevent the first sub-layer SL1 containing aluminum from hillocking during subsequent high-temperature processes. Molybdenum has a poor anodizing effect, but can be used as a barrier metal.

[0119] In some embodiments, the third sub-layer SL3 contains copper, but the present disclosure is not limited thereto. The third sub-layer SL3 containing copper can increase the conductivity of the entire bottom metal layer BM-1. In some embodiments, the second sub-layer SL2 containing molybdenum can be used as a barrier layer to prevent copper diffusion from the third sub-layer SL3 containing copper.

[0120] In some embodiments, the third sub-layer SL3 may include a barrier metal, such as tantalum, titanium, or tungsten, but the present disclosure is not limited thereto.

[0121] In some embodiments, one of the second sub-layer SL2 and the third sub-layer SL3 may be omitted. For example, in some embodiments, the bottom metal layer BM-1 may be a double-layer structure including only the first sub-layer SL1 and the second sub-layer SL2 containing molybdenum. In some embodiments, the bottom metal layer BM-1 may be a double-layer structure including only the first sub-layer SL1 and the third sub-layer SL3 containing copper.

[0122] Please refer to Figure 8B . Figure 8B The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Fig. 8A The intermediate stages shown can be followed in sequence by Figure 8B The intermediate stage is shown in the figure. Figure 8B As shown, the bottom metal layer BM-1 is etched through the first patterned photoresist PR1, so that the etched bottom metal layer BM-1' includes a first lower metal pattern LP1 and a second lower metal pattern LP2 which are sequentially covered by the second sub-layer SL2 and the third sub-layer SL3. In addition, the first lower metal pattern LP1 and the second lower metal pattern LP2 are respectively covered by the first shielding portion PR11 and the second shielding portion PR12.

[0123] Please refer to Figure 8C . Figure 8C The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 8B The intermediate stages shown can be followed in sequence by Figure 8C The intermediate stage shown. Figure 8C As shown, the first shielding portion PR11 is removed to expose the top surface of the third sub-layer SL3 above the first lower metal pattern LP1. Figure 8C The steps of removing the first shielding portion PR11 are the same or similar to Figure 1D The steps shown in Figure 1D The description of Fig.8D . Fig.8D The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Figure 8C The intermediate stages shown can be followed in sequence by Fig.8D The intermediate stage is shown in the figure. Fig.8D As shown, the third sub-layer SL3 and the second sub-layer SL2 above the first lower metal pattern LP1 are selectively etched (relative to the first sub-layer SL1 ) to expose the top surface of the first lower metal pattern LP1 .

[0124] In some embodiments, the second sub-layer SL2 including molybdenum may be etched by using a solution including hydrogen peroxide and citric acid.

[0125] In some embodiments, an etching selectivity ratio of the second sub-layer SL2 to the first sub-layer SL1 in the selective etching is higher than 2.0.

[0126] In some embodiments, the second sub-layer SL2 may be omitted. That is, the bottom metal layer BM-1 may only include the first sub-layer SL1 including aluminum and the third sub-layer SL3 including copper.

[0127] Please refer to Fig. 8E . Fig. 8E The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Fig.8D The intermediate stages shown can be followed in sequence by Fig. 8E The intermediate stage shown. Fig. 8E As shown, the first lower metal pattern LP1 and the second lower metal pattern LP2 are anodized. Fig. 8E The steps of anodizing the first lower metal pattern LP1 and the second lower metal pattern LP2 are the same or similar to the steps shown in FIG. 1E , and thus the steps may be referred to in detail. Figure 1E The description of Figure 8F . Figure 8F The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Fig. 8E The intermediate stages shown can be followed in sequence by Figure 8F The intermediate stage shown. Figure 8F As shown, the second shielding portion PR12 is removed to expose the top surface of the third sub-layer SL3 above the second lower metal pattern LP2. Figure 8F The steps of removing the second shielding portion PR12 are the same or similar to Figure 1F The steps shown in Figure 1F The description of Figure 8F As shown, after the second shielding portion PR12 is removed, the second sublayer SL2 and the third sublayer SL3 of the second lower metal pattern LP2 are selectively etched (relative to the first sublayer SL1) to expose the unanodized top surface of the second lower metal pattern LP2. Figure 8F The steps of removing the second sub-layer SL2 and the third sub-layer SL3 are the same or similar to Fig.8D The steps shown in Fig.8D The description of is omitted here. In some implementations, Figure 8F The intermediate stages shown can be followed in sequence FIG. 4A to FIG. 4EThe intermediate stage is shown.

[0128] Please refer to Fig.9A . Fig.9A Schematic cross-sectional view showing an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. In some embodiments, Figure 1F The intermediate stage shown can be followed directly by Fig.9A The intermediate stage shown. Fig.9A As shown, the semiconductor layer A is deposited on the anodized bottom metal layer BM'. The top metal layer TM is deposited on the semiconductor layer A. The second patterned photoresist PR2 is formed on the top metal layer TM. In other words, Figure 4A The top metal layer TM in is replaced by Fig.9A The top metal layer TM in Fig.9A As shown, the top metal layer TM is a multilayer structure. Specifically, the top metal layer TM includes a first sublayer SL1, a second sublayer SL2, and a third sublayer SL3. The first sublayer SL1 contains aluminum. The second sublayer SL2 is stacked on the first sublayer SL1. The third sublayer SL3 is stacked on the second sublayer SL2. In addition, the second patterned photoresist PR2 has a first hollow portion H1 that exposes a surface portion S4 of the top metal layer TM. The surface portion S4 is a portion where the top surface of the third sublayer SL3 is located directly above the first lower metal pattern LP1.

[0129] In some embodiments, the second sub-layer SL2 contains molybdenum, but the present disclosure is not limited thereto. The second sub-layer SL2 containing molybdenum can prevent the first sub-layer SL1 containing aluminum from bulging during a subsequent high-temperature process.

[0130] In some embodiments, the third sub-layer SL3 contains copper, but the disclosure is not limited thereto.

[0131] In some embodiments, one of the second sub-layer SL2 and the third sub-layer SL3 may be omitted.

[0132] In some embodiments, Fig.9A The steps of depositing the semiconductor layer A are the same or similar to Figure 4A The steps shown in Figure 4A The description of is omitted here. In some embodiments, Fig.9A The steps of forming the second patterned photoresist PR2 are the same or similar to Figure 4A The steps shown in Figure 4A The description is not repeated here.

[0133] Please refer to Fig. 9B . Fig. 9BThe diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Fig.9A The intermediate stages shown can be followed in sequence by Fig. 9B The intermediate stage shown. Fig. 9B As shown, the third sub-layer SL3 and the second sub-layer SL2 in the first hollow portion H1 are selectively etched relative to the first sub-layer SL1 to expose the surface portion S3 of the first sub-layer SL1 in the first hollow portion H1.

[0134] In some embodiments, the second sub-layer SL2 including molybdenum may be etched by using a solution including hydrogen peroxide and citric acid.

[0135] In some embodiments, an etching selectivity ratio of the second sub-layer SL2 to the first sub-layer SL1 in the selective etching is higher than 2.0.

[0136] In some embodiments, the second sub-layer SL2 may be omitted. That is, the top metal layer TM may only include the first sub-layer SL1 containing aluminum and the third sub-layer SL3 containing copper.

[0137] Please refer to Fig. 9C . Fig. 9C The diagram is a cross-sectional view illustrating an intermediate stage of a method for manufacturing an interconnect structure according to some embodiments of the present disclosure. Fig. 9B The intermediate stages shown can be followed in sequence by Fig. 9C The intermediate stage shown. Fig. 9C As shown, and with reference Fig. 9B , the surface portion S3 of the first sub-layer SL1 exposed by the first hollow portion H1 is anodized by the second patterned photoresist PR2 until the top metal layer TM has an anodized segment C extending from the surface portion of the first sub-layer SL1 exposed by the first hollow portion H1 to the side of the first sub-layer SL1 facing the semiconductor layer A. In some embodiments, such as Fig. 9C The steps of anodizing the first sub-layer SL1 of the top metal layer TM shown in FIG. are the same or similar to Figure 4B The steps shown in Figure 4B The description is not repeated here.

[0138] In some embodiments, Fig. 7A The top metal layer TM shown can be replaced by Fig.9A The top metal layer TM shown, and the top metal layer TM is as shown Figure 7CAfter the second hollow portion H2 exposed by the second patterned photoresist PR2 is exposed, the third sublayer SL3 and the second sublayer SL2 in the second hollow portion H2 can be selectively etched relative to the first sublayer SL1 to expose the first sublayer SL1. Fig.7D The intermediate stage shown) and the step of removing the second patterned photoresist PR2.

[0139] From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that the method of manufacturing the interconnect structure disclosed herein only uses two sets of PEP processes. In addition, the method disclosed herein can also only use two sets of PEP processes to manufacture thin film transistors. Therefore, the manufacturing cost can be significantly reduced and the manufacturing efficiency can be effectively improved.

[0140] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application.

Claims

1. A method for manufacturing an interconnect structure, characterized in that: Include: forming a first patterned photoresist on the bottom metal layer having an aluminum atomic ratio greater than 80%, wherein the first patterned photoresist has a first shielding portion and a second shielding portion thicker than the first shielding portion; Etching the bottom metal layer through the first patterned photoresist to form a first lower metal pattern and a second lower metal pattern respectively covered by the first shielding portion and the second shielding portion; removing the first shielding portion; anodizing the etched bottom metal layer, wherein the anodized bottom metal layer has an unanodized portion after the anodizing; removing the second shielding portion to expose a surface portion of the second lower metal pattern that is not anodized; Depositing a conductive layer on the anodized bottom metal layer, wherein the conductive layer contacts the surface portion of the second lower metal pattern; as well as The conductive layer is etched by a second patterned photoresist to form a first upper conductive pattern and a second upper conductive pattern, wherein the first upper conductive pattern is above the first lower metal pattern and is electrically isolated from the first lower metal pattern by the anodized portion of the bottom metal layer, the second upper conductive pattern is above the second lower metal pattern and contacts the surface portion of the second lower metal pattern, and the first upper conductive pattern and the second upper conductive pattern completely cover all non-insulated top surfaces of the anodized bottom metal layer.

2. The method according to claim 1, characterized in that The anodizing of the etched bottom metal layer is performed to reach a termination voltage, the first upper conductive pattern and the second upper conductive pattern each have a thickness and a width, and the termination voltage is less than the minimum of the thickness and the width in nm divided by 0.9 nmV -1 .

3. The method according to claim 1, characterized in that The thickness of the non-anodized portion of the etched bottom metal layer after anodization is equal to or greater than 1 / 10 of the thickness of the etched bottom metal layer before anodization.

4. The method according to claim 1, characterized in that The bottom metal layer contains: A first sublayer comprising aluminum; and The second sub-layer is on and in contact with the first sub-layer.

5. The method according to claim 4, characterized in that Further including: After the removing of the first shielding portion and before the anodizing of the etched bottom metal layer, the second sub-layer is selectively etched relative to the first sub-layer.

6. The method according to claim 4, characterized in that The second sublayer contains molybdenum.

7. The method according to claim 1, characterized in that The anodized etched bottom metal layer was heated by applying 0.05 mA / cm 2 With 5m A / cm 2 It is executed with a certain current between.

8. The method according to claim 1, characterized in that The anodized etched bottom metal layer uses an electrolyte having a pH value between pH 5 and pH 8.

9. The method according to claim 1, characterized in that An etching selectivity ratio of the conductive layer to the etched anodized portion of the bottom metal layer in the etching is higher than 5.

0.

10. The method according to claim 1, characterized in that The depositing the conductive layer comprises: depositing a semi-conductive layer on the anodized bottom metal layer; and depositing a top metal layer on the semiconducting layer, Wherein the method further comprises: removing a portion of the second patterned photoresist to expose a surface portion of the top metal layer after the etching of the conductive layer; as well as The surface portion of the top metal layer is anodized until the top metal layer has an anodized segment extending from the surface portion of the top metal layer to a surface of the top metal layer in contact with the semiconductive layer.

11. The method according to claim 10, characterized in that The top metal layer contains: A first sublayer comprising aluminum; and The second sub-layer is on and in contact with the first sub-layer.

12. The method according to claim 11, characterized in that The second sublayer contains copper.

13. The method according to claim 10, characterized in that The surface of the top metal layer in contact with the semiconductive layer contains aluminum.

14. The method according to claim 13, characterized in that The aluminum atomic ratio of the top metal layer is greater than 80%.

15. The method according to claim 10, characterized in that Further including: The semiconducting layer is annealed.

16. The method according to claim 10, characterized in that The thickness of the semiconductive layer is equal to or less than 100 μm.

17. The method according to claim 1, wherein: The depositing the conductive layer comprises: depositing a semiconductive layer on the anodized bottom metal layer; and depositing a top metal layer on the semiconducting layer, Wherein the method further comprises: Prior to etching the conductive layer, anodizing the top metal layer through the first hollowed-out portion of the second patterned photoresist; and After anodizing the top metal layer, forming a second hollow portion in the second patterned photoresist, The etching of the conductive layer includes etching the conductive layer through the second hollow portion to form the first upper conductive pattern and the second upper conductive pattern.

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