3D package-on-package structure

Abstract

The invention discloses a three-dimensional (3D) stacked packaging structure, which comprises a first chip, a second chip, a through silicon via (TSV) and a multi-layer protection structure, the second chip is connected with the first chip, and the second chip comprises a plurality of metal layers and an interconnect structure which is formed by a plurality of dielectric layer windows which are respectively connected with an upper layer and a lower layer in the plurality of metal layers. The through silicon via penetrates through the second chip. The multi-layer protection structure is arranged in the second chip and surrounds the TSV. The multi-layer protection structure comprises a plurality of protection layers which are respectively provided with an opening for the through silicon vias to pass through; and the plurality of sealing rings are respectively connected with the upper layer and the lower layer in the plurality of protection layers and surround the TSV.

Description

Technical Field

[0001] The present invention relates to a 3D stacked packaging structure, and in particular to a 3D stacked packaging structure including a through-silicon via (TSV) completely surrounded by a multi-layer protection structure. Background Art

[0002] Through-Silicon Via (TSV) is a technology that integrates multiple chips into a single stacked three-dimensional integrated circuit.

[0003] However, TSVs may be damaged due to moisture erosion, stress damage or electrostatic discharge (ESD), which reduces the reliability of TSVs. Therefore, how to protect the TSV structure to maintain its reliability is a goal of continuous efforts. Summary of the invention

[0004] The present invention provides a 3D stacked packaging structure which can be used for WoW (wafer on wafer) packaging and effectively protects the structure of silicon vias to avoid structural damage caused by water vapor erosion, stress damage or electrostatic discharge.

[0005] A 3D stacked packaging structure of the present invention includes: a first chip, a second chip, a through-silicon via (TSV) and a multi-layer protection structure. The second chip is bonded to the first chip, and the second chip includes an interconnect structure composed of multiple metal layers and multiple vias respectively connecting the upper and lower layers of the multiple metal layers. The through-silicon via runs through the second chip. The multi-layer protection structure is arranged in the second chip and surrounds the through-silicon via, wherein the multi-layer protection structure includes multiple protective layers and multiple sealing rings. The multiple protective layers each have an opening for the through-silicon via to pass through. Multiple sealing rings respectively connect the upper and lower layers of the multi-layer protection layer and surround the through-silicon via.

[0006] In one embodiment of the present invention, the plurality of sealing rings and the plurality of vias in the interconnect structure are formed in the same manufacturing process.

[0007] In one embodiment of the present invention, the multi-layer protection layer and the multi-layer metal layer in the interconnect structure are formed in the same manufacturing process.

[0008] In one embodiment of the present invention, the multi-layer protection layer is in direct contact with the TSV.

[0009] In an embodiment of the present invention, the first chip includes a first redistribution layer, the second chip includes a second redistribution layer, and the through silicon via connects the first redistribution layer and the second redistribution layer.

[0010] In an embodiment of the present invention, the first chip is hybrid-bonded to the second chip.

[0011] In one embodiment of the present invention, the first chip is bonded to the second chip by oxide-oxide bonding.

[0012] In an embodiment of the present invention, the second chip may further include a device isolation structure, and the TSV passes through the device isolation structure.

[0013] The present invention further provides a 3D stacked packaging structure, comprising: a first chip, a plurality of second chips, a through silicon via (TSV) and a plurality of multi-layer protection structures. The first chip comprises a first substrate and a first semiconductor structure formed on the first substrate. The plurality of second chips respectively comprise a second substrate and a second semiconductor structure formed on the second substrate, wherein the second semiconductor structure comprises an interconnect structure composed of a plurality of metal layers and a plurality of vias respectively connecting the upper and lower layers of the plurality of metal layers, and the plurality of second chips are bonded to each other. The first semiconductor structure of the first chip is bonded to the second semiconductor structure of the second chip. The through silicon via runs through all the second chips. The plurality of multi-layer protection structures are respectively arranged in the plurality of second chips and surround the through silicon via. Each multi-layer protection structure comprises a plurality of protective layers and a plurality of sealing rings, wherein the plurality of protective layers respectively have an opening for the through silicon via to pass through, and the plurality of sealing rings respectively connect the upper and lower layers of the plurality of protective layers and surround the through silicon via.

[0014] In another embodiment of the present invention, the plurality of seal rings in each second chip and the plurality of vias in the interconnect structure are formed in the same manufacturing process.

[0015] In another embodiment of the present invention, the multi-layer protection layers in each second chip and the multi-layer metal layers in the interconnect structure are formed in the same manufacturing process.

[0016] In another embodiment of the present invention, the multi-layer protection layer in each second chip is in direct contact with the TSV.

[0017] In another embodiment of the present invention, the first chip includes a first redistribution layer, the outermost second chip among the plurality of second chips includes a second redistribution layer, and the through silicon via connects the first redistribution layer and the second redistribution layer.

[0018] In another embodiment of the present invention, the plurality of second chips are bonded to each other by oxide-oxide bonding.

[0019] In another embodiment of the present invention, the first chip is bonded to the second chip by oxide-oxide bonding.

[0020] In another embodiment of the present invention, each second chip may further include a device isolation structure, and the TSV passes through the device isolation structure.

[0021] Based on the above, the 3D stacked packaging structure of the present invention has a protective layer and a sealing ring, which can completely surround the silicon via, effectively protect the structure of the silicon via, avoid structural damage caused by water vapor erosion, stress damage or electrostatic discharge, so as to maintain the reliability of the above-mentioned silicon via.

[0022] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A is a cross-sectional view of a 3D stacked package structure according to a first embodiment of the present invention;

[0024] Figure 1B In the first embodiment Figure 1A A partial plan view of the structure;

[0025] Figure 1C yes Figure 1A A partially enlarged stereoscopic schematic diagram of

[0026] Figure 2 is a cross-sectional view of a 3D stacked package structure according to a second embodiment of the present invention;

[0027] Figure 3 is a cross-sectional view of a 3D stacked package structure according to a third embodiment of the present invention;

[0028] Figure 4 is a cross-sectional view of a 3D stacked package structure according to a fourth embodiment of the present invention;

[0029] Figure 5 is a cross-sectional view of a 3D stacked package structure according to a fifth embodiment of the present invention;

[0030] FIG. 6A to FIG. 6E FIG. 4 is a cross-sectional schematic diagram of the manufacturing process of the 3D stacked packaging structure according to the sixth embodiment of the present invention.

[0031] Explanation of symbols

[0032] 10, 20, 30, 40, 50, 60: 3D stacking packaging structure

[0033] 100: First base

[0034] 1000: First Chip

[0035] 102: first dielectric layer

[0036] 104: First semiconductor element

[0037] 106a: first metal joint

[0038] 106b: first oxide layer

[0039] 108: First element isolation structure

[0040] 110: First metal layer

[0041] 112: First interlayer window

[0042] 114: First internal connection structure

[0043] 116: First redistribution layer

[0044] 200: Second base

[0045] 2000: Second Chip

[0046] 202: Second dielectric layer

[0047] 204: Second semiconductor element

[0048] 206a: second metal joint

[0049] 206b: Second oxide layer

[0050] 208: Second component isolation structure

[0051] 210: Second metal layer

[0052] 212: Second interlayer window

[0053] 214: Second internal connection structure

[0054] 216a, 216b: second redistribution layer

[0055] 218, 318, 418: pads

[0056] 220, 320, 420: insulation layer

[0057] 300: Third base

[0058] 3000: The third chip

[0059] 302: third dielectric layer

[0060] 304: Third semiconductor element

[0061] 306b: Third oxide layer

[0062] 308: Third component isolation structure

[0063] 310: The third metal layer

[0064] 312: Third Interlayer Window

[0065] 314: Third internal connection structure

[0066] 316: The third redistribution layer

[0067] 400: Fourth base

[0068] 4000: The fourth chip

[0069] 402: fourth dielectric layer

[0070] 404: Fourth semiconductor element

[0071] 408: Fourth component isolation structure

[0072] 410: Fourth metal layer

[0073] 412: Fourth interlayer window

[0074] 414: Fourth internal connection structure

[0075] 600, 602: dielectric layer

[0076] BRDL: Backside redistribution layer

[0077] CSa, CSa', CSa': first protection layer

[0078] CSb, CSb': Second protection layer

[0079] CSc': The third protective layer

[0080] OP: Opening

[0081] PSa, PSa', PSa": first protection structure

[0082] PSb, PSb': Second protection structure

[0083] PSc': Third protection structure

[0084] SRa, SRa', SRa": first sealing ring

[0085] SRb, SRb': Second sealing ring

[0086] SRc': Third sealing ring

[0087] TSVa, TSVa': First Through Silicon Via

[0088] TSVb: Second Through Silicon Via

[0089] TSVc:Third Silicon Via DETAILED DESCRIPTION

[0090] The present invention can be understood by referring to the following detailed description and in conjunction with the accompanying drawings. It should be noted that in order to make it easy for readers to understand and for the simplicity of the drawings, the multiple drawings in the present invention only depict a part of the structure, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the figure are only for illustration and are not used to limit the scope of the present invention. Furthermore, the directional terms such as "on", "upper", etc. mentioned in the text are only used to refer to the direction of the drawings and are not used to limit the present invention. In the following, "including" or similar terms should be interpreted as "including but not limited to...". Moreover, although the terms "first", "second", etc. are used in the text to describe different elements, components, regions, film layers and / or blocks, these elements, components, regions, film layers and / or blocks should not be limited to these terms. Instead, these terms are only used to distinguish one element, component, region, film layer or block from another element, component, region, film layer or block. As for the " / " in the text, it has the meaning of including all of the relevant listed items.

[0091] Figure 1A FIG. 1 is a cross-sectional view of a 3D stacked package structure 10 according to a first embodiment of the present invention.

[0092] Please refer to Figure 1AThe 3D stacked package structure 10 of the first embodiment includes: a first chip 1000, a second chip 2000, a first through silicon via TSVa and a first multi-layer protection structure PSa, wherein the second chip 2000 is bonded to the first chip 1000. The aforementioned "chip" refers in a broad sense to a wafer or a cut die that has completed the front-end circuit manufacturing process in a semiconductor device. Therefore, in one embodiment, the first chip 1000 and the second chip 2000 can be regarded as a first wafer and a second wafer; and so on. The second chip 2000 includes a second interconnect structure 214 composed of a plurality of second metal layers 210 and a plurality of second vias 212 respectively connecting the upper and lower layers of the plurality of second metal layers 210. The first through silicon via TSVa runs through the second chip 2000. The first multi-layer protection structure PSa is disposed in the second chip 2000 and surrounds the first silicon through-via TSVa, wherein the first multi-layer protection structure PSa includes: a multi-layer first protection layer CSa and a plurality of first sealing rings SRa, wherein the first sealing rings SRa respectively connect the upper and lower layers of the multi-layer first protection layer CSa and surround the first silicon through-via TSVa, and the multi-layer first protection layer CSa respectively has an opening OP for the first silicon through-via TSVa to pass through. Figure 1B Partial floor plan and Figure 1C As shown in the stereogram.

[0093] exist Figure 1B In FIG. 1 , the first protection layer CSa is in a square shape, the opening OP is in a circular shape, the area between the dotted circles is the location of the first sealing ring SRa, and the first sealing ring SRa surrounds the first through silicon via TSVa and is spaced a distance therefrom. Figure 1C In the embodiment, the first multi-layer protection structure PSa surrounds the first through silicon via TSVa, and the unenclosed portion of the first through silicon via TSVa is disposed in the second chip 2000. In addition, the size of the opening OP may be equal to or slightly larger than the size of the first through silicon via TSVa. Even if the size of the opening OP is smaller than the predetermined size of the first through silicon via TSVa, as long as the etching process can pass through the first protection layer CSa, in this case, the first protection layer CSa will be in direct contact with the first through silicon via TSVa.

[0094] Please continue to refer to Figure 1AThe materials of the interconnect 214 of the second chip 2000 and the first multi-layer protection structure PSa may be conductive materials, such as titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride, or a combination thereof, but not limited thereto. The materials of the multiple first sealing rings SRa and the multiple first protection layers CSa in the first multi-layer protection structure PSa may be the same or different. The materials of the multiple second metal layers 210 and the multiple second vias 212 may be the same or different. The first through silicon via TSVa may be a conductive material, such as copper, tungsten, polysilicon, or a combination thereof, but not limited thereto.

[0095] The second chip 2000 may further include: a second substrate 200, a second dielectric layer 202, a second redistribution layer (DRL) 216a, a second semiconductor element 204 and other components, but is not limited thereto. Since the second chip 2000 and the first chip 1000 are bonded to each other, Figure 1A The second chip 2000 is presented in an inverted state. The second interconnect structure 214 is formed in the second dielectric layer 202 on the second substrate 200, and the second redistribution layer 216a is formed on the interconnect structure 214 and connected to the first silicon via TSVa. The first silicon via TSVa penetrates the second substrate 200. The second substrate 200 may also include a second element isolation structure 208, and the first silicon via TSVa may be formed by etching through the second element isolation structure 208 and continuously etching through the second dielectric layer 202. Figure 1A In the embodiment, a first sealing ring SRa in the first protection structure PSa is connected to the second redistribution layer 216a. The second semiconductor device 204 is disposed on the second substrate 200 and connected to other components, such as the second redistribution layer 216a, through the second interconnect structure 214.

[0096] Please continue to refer to Figure 1A , the first chip 1000 may also include: a first substrate 100, a first dielectric layer 102, a first semiconductor element 104, a first interconnect structure 114 and a first redistribution layer 116. The first dielectric layer 102 and the first semiconductor element 104 are formed on the first substrate 100. The first interconnect structure 114 is composed of a plurality of first metal layers 110 and a plurality of first vias 112 respectively connecting the upper and lower layers of the plurality of first metal layers 110, wherein the material of the first interconnect structure 114 may be a conductive material, such as titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride or a combination thereof, but is not limited thereto. The first redistribution layer 116 is disposed on the first interconnect structure 114, although Figure 1AThe relationship between the first redistribution layer 116 and the first internal connection structure 114 thereunder is not shown, but it should be known that the first redistribution layer 116 changes the contact positions in the original first internal connection structure 114 according to needs so that it can be electrically connected to the second semiconductor element 204 of the second chip 2000, so the first redistribution layer 116 and the first internal connection structure 114 thereunder will be connected through lines in other cross sections.

[0097] Since the 3D stacked package structure 10 of the first embodiment can bond the first chip 1000 and the second chip 2000 by hybrid bonding, a first metal bonding portion 106a is formed on the bonding surfaces of the first chip 1000 and the second chip 2000, respectively, and the hybrid bonding is achieved by bonding the first metal bonding portion 106a of the first chip 1000 and the first metal bonding portion 106a of the second chip 2000, and bonding the first dielectric layer 102 of the first chip 1000 and the second dielectric layer 202 of the second chip 2000. However, the present invention is not limited thereto, and different bonding manufacturing processes may be used in other embodiments.

[0098] Please continue to refer to Figure 1A The 3D stacked package structure 10 of the first embodiment may further include: a back-side redistribution layer (BRDL), a pad 218 and an insulating layer 220. The back-side redistribution layer BRDL is disposed on the second substrate 200 relative to the second semiconductor element 204, and the first through silicon via TSVa may be connected to the back-side redistribution layer BRDL. The pad 218 is disposed on the back-side redistribution layer BRDL, and the insulating layer 220 covers the back-side redistribution layer BRDL and exposes a portion of the surface of the pad 218 for connection with other devices or circuit boards (not shown).

[0099] In some embodiments, the first substrate 100 and the second substrate 200 may be silicon or other suitable materials, but are not limited thereto. The aforementioned other suitable materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, etc. The materials of the insulating layer 220, the first dielectric layer 102 and the second dielectric layer 202 include, but are not limited to, silicon oxide, silicon oxynitride, silicon nitride, high dielectric constant dielectric metal oxides (such as hafnium oxide, zirconium oxide, hafnium zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, aluminum oxide, etc.) or a combination thereof. The first semiconductor element 104 and the second semiconductor element 204 may include active elements, passive elements or a combination thereof, such as transistors, diodes, capacitors, resistors, inductors, etc. The materials of the back side redistribution layer BRDL, the pad 218, the first redistribution layer 116 and the second redistribution layer 216a may be conductive materials, such as tungsten, titanium, tantalum, platinum, copper, gold, aluminum, titanium nitride or a combination thereof, but are not limited thereto.

[0100] Please continue to refer to Figure 1A The multiple first sealing rings SRa in the first multi-layer protection structure PSa and the multiple second vias 212 in the second internal connection structure 214 can be formed by the same manufacturing process. For example, a second via 212 and a first sealing ring SRa are formed simultaneously by the same photomask manufacturing process. Therefore, the second via 212 and the first sealing ring SRa are formed on the same plane and are made of the same material. Therefore, no additional photolithography and etching manufacturing processes are required, so that the present embodiment has the effect of simple manufacturing process and cost saving.

[0101] Please continue to refer to Figure 1A The multi-layer first protective layer CSa in the first multi-layer protective structure PSa can also be formed by the same manufacturing process as the multi-layer second metal layer 210 in the second internal connection structure 214. For example, a first protective layer CSa and a second metal layer 210 are formed at the same time using the same photomask manufacturing process. Therefore, the first protective layer CSa and the second metal layer 210 will be formed on the same plane and are made of the same material. Therefore, no additional photolithography and etching manufacturing processes are required, which makes this embodiment simple in manufacturing process and saves cost.

[0102] In the present embodiment, the first through silicon via TSVa is completely surrounded by the first protective layer CSa and the first sealing ring SRa, except for the area that passes through the second substrate 200 and is surrounded by the second substrate 200. Therefore, the first multi-layer protection structure PSa can effectively protect the first through silicon via TSVa to avoid structural damage caused by water vapor erosion, stress damage or electrostatic discharge, so as to maintain the reliability of the first through silicon via TSVa.

[0103] Figure 2 It is a cross-sectional view of a 3D stacked packaging structure 20 according to a second embodiment of the present invention, wherein the same element symbols as those of the first embodiment are used to represent the same or similar parts and components, and the relevant contents of related or similar parts and components can also refer to the contents of the first embodiment and will not be repeated.

[0104] Specifically, the second embodiment is different from the first embodiment mainly in that the second chip 2000 of the present embodiment further includes a second through silicon via TSVb and a second multi-layer protection structure PSb. The second through silicon via TSVb penetrates the second chip 2000 and is connected to the first redistribution layer 116 in the first chip 1000. The second multi-layer protection structure PSb is arranged in the second chip 2000 and surrounds the second through silicon via TSVb, wherein the second multi-layer protection structure PSb includes: a multi-layer second protection layer CSb and a plurality of second sealing rings SRb, wherein the second sealing rings SRb respectively connect the upper and lower layers of the multi-layer second protection layer CSb and surround the second through silicon via TSVb.

[0105] Please continue to refer to Figure 2 , the 3D stacked package structure 20 may include a first oxide layer 106b, which is disposed at the bonding surface between the first chip 1000 and the second chip 2000, so that oxide-oxide bonding can be achieved through the first oxide layer 106b. In this embodiment, the second through silicon via TSVb may penetrate the first oxide layer 106b to connect the first redistribution layer 116. In addition, the first substrate 100 may also include a first device isolation structure 108.

[0106] It should be noted that a person skilled in the art may adjust the specific number and spatial configuration of the TSVs according to product requirements, and the present invention is not limited thereto.

[0107] Figure 3 It is a cross-sectional view of a 3D stacked packaging structure 30 according to a third embodiment of the present invention, wherein the same element symbols as those of the first embodiment are used to represent the same or similar parts and components, and the relevant contents of related or similar parts and components can also refer to the contents of the first embodiment and will not be repeated here.

[0108] Please refer to Figure 3 The 3D stacked package structure 30 of the third embodiment includes: a first chip 1000, a second chip 2000, a third chip 3000 and a fourth chip 4000. The structures of the first chip 1000 and the second chip 2000 are detailed in the first embodiment. The third chip 3000 includes a third substrate 300, a third dielectric layer 302, a third semiconductor element 304, a third internal connection structure 314 and a first multi-layer protection structure PSa' and other components. The third internal connection structure 314 is composed of a plurality of third metal layers 310 and a plurality of third vias 312 respectively connecting the upper and lower layers of the plurality of third metal layers 310, and the remaining components are similar to the second chip 2000. The fourth chip 4000 includes components such as a fourth substrate 400, a fourth dielectric layer 402, a fourth semiconductor element 404, a fourth interconnect structure 414, and a first multi-layer protection structure PSa". The fourth interconnect structure 414 is composed of a plurality of fourth metal layers 410 and a plurality of fourth vias 412 respectively connecting the upper and lower layers of the plurality of fourth metal layers 410, and the remaining components are similar to the second chip 2000. In this embodiment, since the second chip 2000, the third chip 3000 and the fourth chip 4000 have the same structure, for example, the same semiconductor structure is provided on the substrate, the second chip 2000, the third chip 3000 and the fourth chip 4000 can be regarded as the same plurality of chips, but the present invention is not limited thereto. In another embodiment, the second chip 2000, the third chip 3000 and the fourth chip 4000 may have differences, for example, the third semiconductor element 304 and the fourth semiconductor element 404 are different elements; and so on.

[0109] exist Figure 3 In the embodiment, the first through silicon via TSVa' passes through the second chip 2000, the third chip 3000 and the fourth chip 4000, connecting the back side redistribution layer BRDL and the first redistribution layer 116. The first multi-layer protection structure PSa / PSa' / PSa" is respectively arranged in the second chip 2000, the third chip 3000 and the fourth chip 4000 and surrounds the first through silicon via TSVa', wherein each first multi-layer protection structure PSa / PSa' / PSa" includes: a multi-layer first protection layer CSa / CSa' / CSa" and a plurality of first sealing rings SRa / SRa' / SRa". The first protection layer CSa' and the first protection layer CSa" can be the same as the first protection layer CSa, and both have an opening OP for the first through silicon via TSVa' to pass through. The first sealing ring SRa / SRa' / SRa" respectively connects the upper and lower layers in the first protection layer CSa / CSa' / CSa" and surrounds the first through silicon via TSVa'.

[0110] It should be noted that a person skilled in the art can still adjust the specific number of stacked chips according to product requirements, and the present invention is not limited thereto.

[0111] Please continue to refer to Figure 3 , the second metal layer 210 may be connected to the first protective layer CSa, the third metal layer 310 may be connected to the first protective layer CSa', and the fourth metal layer 410 may be connected to the first protective layer CSa", but is not limited thereto. In another embodiment, the second metal layer 210 may not be connected to the first protective layer CSa; and so on.

[0112] In this embodiment, the first chip 1000, the second chip 2000, the third chip 3000 and the fourth chip 4000 can be bonded to each other by oxide-oxide bonding, so the 3D stacked package structure 30 can also include a first oxide layer 106b, a second oxide layer 206b and a third oxide layer 306b, which are respectively disposed on the bonding surface between the two chips. The third substrate 300 and the fourth substrate 400 can also include a third device isolation structure 308 and a fourth device isolation structure 408, so as to be used in the etching process of forming the first through silicon via TSVa'.

[0113] Figure 4 It is a cross-sectional view of a 3D stacked packaging structure 40 according to the fourth embodiment of the present invention, wherein the same element symbols as the third embodiment are used to represent the same or similar parts and components, and the relevant contents of related or similar parts and components can also refer to the contents of the third embodiment and will not be repeated.

[0114] Specifically, the difference between this embodiment and the third embodiment is that the number of chips becomes three, and there is one more second through silicon via TSVb in the second chip 2000 and the third chip 3000, and one more third through silicon via TSVc in the third chip 3000. A second multi-layer protection structure PSb / PSb' is arranged around the second through silicon via TSVb. A third multi-layer protection structure PSc' is arranged around the third through silicon via TSVc. The second multi-layer protection structure PSb includes a second sealing ring SRb and a second protection layer CSb, the second multi-layer protection structure PSb' includes a second sealing ring SRb' and a second protection layer CSb', and the third multi-layer protection structure PSc' includes a third sealing ring SRc' and a third protection layer CSc'.

[0115] exist Figure 4 In the embodiment, the second chip 2000 may further include a second redistribution layer 216a, and the third chip 3000 may further include a third redistribution layer 316. The first through silicon via TSVa connects the first redistribution layer 116, the second redistribution layer 216a, the third redistribution layer 316, and the back redistribution layer BRDL. The second through silicon via TSVb connects the second redistribution layer 216a, the third redistribution layer 316, and the back redistribution layer BRDL. The third through silicon via TSVc connects the third redistribution layer 316 and the back redistribution layer BRDL.

[0116] Figure 5 It is a cross-sectional view of a 3D stacked packaging structure 50 according to the fifth embodiment of the present invention, wherein the same element symbols as the third embodiment are used to represent the same or similar parts and components, and the relevant contents of related or similar parts and components can also refer to the contents of the third embodiment and will not be repeated.

[0117] Specifically, the present embodiment is different from the third embodiment in that the number of chips is changed to three, and the second chip 2000 in the present embodiment may include a second through silicon via TSVb and a second multi-layer protection structure PSb. The second multi-layer protection structure PSb is disposed on the second chip 2000 and surrounds the second through silicon via TSVb, wherein the second multi-layer protection structure PSb includes a second sealing ring SRb and a second protection layer CSb.

[0118] exist Figure 5In the embodiment, the second chip 2000 further includes two second redistribution layers 216a / 216b, the second redistribution layer 216a is arranged on one side of the second substrate 200, and the second redistribution layer 216b is arranged on the side close to the first chip 1000. The third chip 3000 includes a third redistribution layer 316 close to the second chip 2000. The second through silicon via TSVb connects the second redistribution layer 216a and the second redistribution layer 216b. The first through silicon via TSVa connects the first redistribution layer 116, the second redistribution layer 216a, the second redistribution layer 216b, the third redistribution layer 316 and the back redistribution layer BRDL.

[0119] Please continue to refer to Figure 5 The first chip 1000, the second chip 2000 and the third chip 3000 are bonded together by hybrid bonding, so the bonding surface of the first chip 1000 and the second chip 2000 can be provided with a first metal bonding portion 106a, and the bonding surface of the second chip 2000 and the third chip 3000 can be provided with a second metal bonding portion 206a. Since the hybrid bonding manufacturing process is an existing technology, it will not be further described here.

[0120] FIG. 6A to FIG. 6E It is a cross-sectional schematic diagram of the manufacturing process of the 3D stacked packaging structure 60 according to the sixth embodiment of the present invention, wherein the same element symbols as the third embodiment are used to represent the same or similar parts and components, and the relevant contents of related or similar parts and components can also refer to the contents of the third embodiment and will not be repeated.

[0121] Please refer to Fig. 6A , a second semiconductor element 204 is formed on a second substrate 200 including a second element isolation structure 208, and a dielectric layer 600 is formed to cover the second semiconductor element 204, and then a second via 212 and a first sealing ring SRa are formed in the dielectric layer 600, wherein the first sealing ring SRa can be formed directly above the second element isolation structure 208, and the second via 212 can be electrically connected to the second semiconductor element 204. The second via 212 and the first sealing ring SRa can be opened by first forming an opening through the same photomask manufacturing process, and then filled with metal material, so the first sealing ring SRa and the second via 212 will be formed on the same plane and made of the same material, and no additional manufacturing process is required to form the first sealing ring SRa.

[0122] Next, please refer to Figure 6B, another dielectric layer 602 is formed on the dielectric layer 600, and then a second metal layer 210 and a first protective layer CSa are formed in the dielectric layer 602. The second metal layer 210 and the first protective layer CSa can be opened by the same photomask manufacturing process and then filled with metal materials, so the second metal layer 210 and the first protective layer CSa are formed on the same plane and are made of the same material, and no additional manufacturing process is required to form the first protective layer CSa.

[0123] Then, please refer to Figure 6C Repeat the above steps according to the device design to form a second interconnect structure 214 consisting of a plurality of second metal layers 210 and a plurality of second vias 212 respectively connecting the upper and lower layers of the plurality of second metal layers 210, and at the same time form a first protection structure PSa consisting of a plurality of first protection layers CSa and a plurality of first sealing rings SRa respectively connecting the upper and lower layers of the plurality of first protection layers CSa. Figure 6C The second dielectric layer 202 in the embodiment is a multi-layer dielectric layer (eg Figure 6B Then, a first oxide layer 106b is formed on the second dielectric layer 202 to obtain a second chip 2000.

[0124] Next, please refer to Fig.6D ,Will Figure 6C The second chip 2000 is flipped and bonded to the first chip 1000 , wherein the bonding method is, for example, oxide-oxide bonding. The first chip 1000 can refer to the first embodiment, but does not have the first metal bonding portion ( 106 a ) and includes a first device isolation structure 108 in the first substrate 100 .

[0125] Then, please refer to Fig. 6E, the above steps can be repeated according to product requirements to join multiple chips, such as the first chip 1000, the second chip 2000, the third chip 3000 and the fourth chip 4000. The structures of the third chip 3000 and the fourth chip 4000 can refer to the third embodiment. Afterwards, a first through silicon via TSVa is formed that penetrates the second chip 2000, the third chip 3000 and the fourth chip 4000, and the steps thereof are, for example, to continuously etch through the fourth chip 4000, the third chip 3000 and the second chip 2000 in accordance with the opening OP, wherein the second device isolation structure 208, the third device isolation structure 308 and the fourth device isolation structure 408 are all silicon oxide, and have similar materials to the second dielectric layer 202, the third dielectric layer 302 and the fourth dielectric layer 402, so a through hole that penetrates the fourth chip 4000, the third chip 3000 and the second chip 2000 can be continuously etched, and then a conductive material is formed therein, so that the first through silicon via TSVa can be formed. Afterwards, a backside redistribution layer BRDL is formed on the outermost fourth chip 4000, and then an insulating layer 420 and a pad 418 are formed. Other manufacturing processes may be included in the subsequent steps, which will not be described here.

[0126] In summary, in the 3D stacked packaging structure of the present invention, the silicon via is completely surrounded by the protective layer and the sealing ring in the plane and vertical direction, which can effectively protect the structure of the silicon via and avoid structural damage caused by water vapor erosion, stress damage or electrostatic discharge, so as to maintain the reliability of the silicon via. In addition, if the protective layer and the sealing ring are formed in the same manufacturing process as the metal layer and the via in the chip, no additional photomask manufacturing process is required, thereby achieving the effect of simple manufacturing process and cost saving.

[0127] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Any ordinary technician in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. A 3D stacked packaging structure, include: First chip; A second chip is bonded to the first chip, wherein the second chip includes an interconnect structure consisting of a plurality of metal layers and a plurality of vias respectively connecting upper and lower layers of the plurality of metal layers; Through-Silicon Via (TSV), penetrating the second chip; as well as A multi-layer protection structure is disposed in the second chip and surrounds the through silicon via, wherein the multi-layer protection structure comprises: The multiple protective layers each have an opening for the silicon via to pass through; as well as A plurality of sealing rings respectively connect the upper and lower layers of the multi-layer protection layer and surround the silicon through-hole. 2 . The 3D stacked package structure as claimed in claim 1 , wherein the plurality of sealing rings and the plurality of vias in the interconnect structure are formed in the same manufacturing process. 3 . The 3D stacked package structure as claimed in claim 1 , wherein the multi-layer protection layer and the multi-layer metal layer in the interconnect structure are formed in the same manufacturing process. 4 . The 3D stacked package structure according to claim 1 , wherein the multi-layer protection layer is in direct contact with the TSV. 5 . The 3D stacked package structure according to claim 1 , wherein the first chip comprises a first redistribution layer, the second chip comprises a second redistribution layer, and the through silicon via connects the first redistribution layer and the second redistribution layer. The 3D stacked package structure according to claim 1 , wherein the first chip is hybrid-bonded to the second chip. 7 . The 3D stacked package structure according to claim 1 , wherein the first chip is bonded to the second chip by oxide-oxide bonding. 8 . The 3D stacked package structure according to claim 1 , wherein the second chip further comprises a device isolation structure, and the TSV penetrates the device isolation structure.

9. A 3D stacked packaging structure, include: A first chip, comprising a first substrate and a first semiconductor structure formed on the first substrate; A plurality of second chips, each comprising a second substrate and a second semiconductor structure formed on the second substrate, wherein the second semiconductor structure comprises an interconnect structure consisting of a plurality of metal layers and a plurality of vias respectively connecting upper and lower layers of the plurality of metal layers, the plurality of second chips are bonded to each other, and the first semiconductor structure of the first chip is bonded to the second semiconductor structure of the second chip; Through-Silicon Via (TSV), penetrating the plurality of second chips; as well as A plurality of multi-layer protection structures are respectively disposed in the plurality of second chips and surround the through silicon vias, wherein each of the multi-layer protection structures comprises: The multiple protective layers each have an opening for the silicon via to pass through; as well as A plurality of sealing rings respectively connect the upper and lower layers of the multi-layer protection layer and surround the silicon through-hole. 10 . The 3D stacked package structure as claimed in claim 9 , wherein the plurality of seal rings in each of the second chips and the plurality of vias in the interconnect structure are formed in the same manufacturing process. 11 . The 3D stacked package structure as claimed in claim 9 , wherein the multi-layer protection layer in each of the second chips and the multi-layer metal layer in the interconnect structure are formed in the same manufacturing process. 12 . The 3D stacked package structure according to claim 9 , wherein the multi-layer protection layer in each of the second chips is in direct contact with the TSV.

13. The 3D stacked packaging structure as described in claim 9, wherein the first chip includes a first redistribution layer, the outermost second chip among the plurality of second chips includes a second redistribution layer, and the silicon through-hole connects the first redistribution layer and the second redistribution layer. 14 . The 3D stacked package structure as claimed in claim 9 , wherein the plurality of second chips are bonded to each other by oxide-oxide bonding. 15 . The 3D stacked package structure according to claim 9 , wherein the first chip is bonded to the second chip by oxide-oxide bonding. 16 . The 3D stacked package structure according to claim 9 , wherein each of the second chips further comprises a device isolation structure, and the through silicon via penetrates the device isolation structure.

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