Semiconductor device, manufacturing method and testing method thereof, and storage system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method and a testing method thereof, and a storage system. The semiconductor device comprises a semiconductor layer, a first dielectric layer and a second dielectric layer which are sequentially arranged in a stacked mode in the first direction. A semiconductor structure in the semiconductor layer; the first conductive structure is located in the first dielectric layer; the first conductive structure is connected with the semiconductor structure; the second conductive structure penetrates through the second dielectric layer along the first direction and extends into the first dielectric layer, and the second conductive structure is connected with one end, far away from the semiconductor structure, of the first conductive structure along the first direction; the liner structure is located in the second dielectric layer; the pad structure is connected with the second conductive structure, and the pad structure is isolated from the first conductive structure; the opening is located in the second dielectric layer; the opening exposes the liner structure. Therefore, the reliability of the semiconductor device can be improved, the difficulty of a manufacturing process is reduced, the manufacturing speed is improved, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method and a testing method thereof, and a storage system. Background Art

[0002] With the development of large-scale integrated circuits, semiconductor devices are developing in the three-dimensional direction and entering the post-Moore era to meet the requirements of high integration, fast transmission speed, low power consumption, etc. Multiple chips stacked in the three-dimensional direction in semiconductor devices are mainly connected vertically through silicon via (TSV) technology.

[0003] However, with the miniaturization of semiconductor devices, there are still many problems to be solved in the interconnection structure used to achieve vertical connection of semiconductor devices. Summary of the invention

[0004] In view of this, in order to solve one or more of the existing technical problems, the embodiments of the present disclosure propose a semiconductor device and a manufacturing method and a testing method thereof, and a storage system; wherein the semiconductor device includes: a semiconductor layer, a first dielectric layer, and a second dielectric layer stacked in sequence along a first direction; a semiconductor structure, located in the semiconductor layer; a first conductive structure, located in the first dielectric layer; the first conductive structure is connected to the semiconductor structure; a second conductive structure, penetrating the second dielectric layer along the first direction and extending into the first dielectric layer, the second conductive structure is connected to an end of the first conductive structure away from the semiconductor structure along the first direction; a pad structure, located in the second dielectric layer; the pad structure is connected to the second conductive structure, and the pad structure and the first conductive structure are isolated from each other; an opening, located in the second dielectric layer; the opening exposes the pad structure.

[0005] In some embodiments, when the material of the pad structure is copper, the semiconductor device further includes: a filling structure located at the opening; a top surface of the filling structure is flush with a top surface of the second dielectric layer along a second direction; and the second direction is perpendicular to the first direction.

[0006] In some embodiments, the semiconductor device further includes: a barrier layer; the barrier layer covers the sidewalls and the bottom surface of the second conductive structure; wherein a portion of the barrier layer is located between the second conductive structure and the pad structure.

[0007] In some embodiments, the material of the barrier layer includes at least one of tantalum, tantalum nitride, titanium and titanium nitride; the material of the second conductive structure includes at least one of gold, silver, copper, iron, nickel and tin.

[0008] In some embodiments, the semiconductor device further includes: a third conductive structure, which penetrates the second dielectric layer along the first direction and extends into the first dielectric layer, and the third conductive structure and the second conductive structure are arranged at intervals along the second direction; and a fourth conductive structure, which is located in the first dielectric layer; the fourth conductive structure is respectively connected to the third conductive structure and the semiconductor structure; the fourth conductive structure and the first conductive structure are arranged at intervals along the second direction.

[0009] In some embodiments, the semiconductor device also includes: a first insulating layer, located in the first dielectric layer and located on a side of the first conductive structure away from the semiconductor structure in the first direction; wherein the second conductive structure penetrates the first insulating layer along the first direction and is connected to the first conductive structure.

[0010] In some embodiments, the semiconductor device further includes: a second insulating layer, located on a side of the second dielectric layer away from the first dielectric layer along the first direction; the second insulating layer covers the top surface of the second conductive structure, and the top surface and the bottom surface are two opposite surfaces of the second conductive structure in the first direction.

[0011] In some embodiments, the semiconductor device further includes: a third dielectric layer located on a side of the second insulating layer away from the second dielectric layer along the first direction; and an interconnect structure penetrating the third dielectric layer and the second insulating layer along the first direction; the interconnect structure is connected to the second conductive structure.

[0012] A storage system proposed in an embodiment of the present disclosure includes a semiconductor device as described in the above embodiment of the present disclosure; and a memory controller coupled to the semiconductor device and used to control the semiconductor device.

[0013] A method for manufacturing a semiconductor device proposed in an embodiment of the present disclosure includes: forming a semiconductor layer, a first dielectric layer, and a second dielectric layer stacked in sequence along a first direction; forming a semiconductor structure in the semiconductor layer; forming a first conductive structure in the first dielectric layer, and connecting the first conductive structure to the semiconductor structure; forming a second conductive structure that penetrates the second dielectric layer and extends into the first dielectric layer along the first direction, and connecting the second conductive structure to an end of the first conductive structure that is away from the semiconductor structure along the first direction; forming a pad structure in the second dielectric layer, and connecting the pad structure to the second conductive structure, and isolating the pad structure from the first conductive structure; forming an opening in the second dielectric layer, and exposing the pad structure through the opening.

[0014] In some embodiments, the method further includes: when the material of the pad structure is copper, after testing the semiconductor structure using the pad structure, forming a filling structure at the opening.

[0015] In some embodiments, the method further includes: when the material of the pad structure is aluminum, after testing the semiconductor structure using the pad structure, removing the pad structure; and forming a filling structure at the original position of the pad structure and at the opening.

[0016] In some embodiments, forming a pad structure in the second dielectric layer includes: forming a pad structure on a portion of the surface of the first dielectric layer away from the semiconductor layer along the first direction; forming a dielectric material layer on the remaining surface of the first dielectric layer away from the semiconductor layer along the first direction and on the surface of the pad structure; and planarizing the dielectric material layer to form a second dielectric layer.

[0017] In some embodiments, the forming of the second conductive structure that penetrates the second dielectric layer along the first direction and extends into the first dielectric layer includes: forming a groove that penetrates the second dielectric layer along the first direction and extends into the first dielectric layer; the groove exposes the top surface of the first conductive structure in the first direction and exposes a side surface of the pad structure in the second direction; the first direction is perpendicular to the second direction; and the second conductive structure is formed in the groove.

[0018] In some embodiments, forming the second conductive structure in the groove includes: forming a barrier layer on the sidewall and bottom of the groove; and forming the second conductive structure in the groove having the barrier layer formed thereon.

[0019] In some embodiments, the method further includes: forming a third conductive structure that penetrates the second dielectric layer along the first direction and extends into the first dielectric layer, and the third conductive structure and the second conductive structure are arranged at intervals along the second direction; and forming a fourth conductive structure in the first dielectric layer, and the fourth conductive structure is respectively connected to the third conductive structure and the semiconductor structure, and the fourth conductive structure and the first conductive structure are arranged at intervals along the second direction.

[0020] In some embodiments, the method further includes: forming a first insulating layer in the first dielectric layer and on a side of the first conductive structure away from the semiconductor structure along the first direction; wherein the second conductive structure penetrates the first insulating layer along the first direction and connects to the first conductive structure.

[0021] In some embodiments, the method further includes: forming a second insulating layer on a side of the second dielectric layer away from the first dielectric layer along the first direction, and making the second insulating layer cover a top surface of the second conductive structure.

[0022] In some embodiments, the method further includes: forming a third dielectric layer on a side of the second insulating layer away from the second dielectric layer along the first direction; forming an interconnect structure that penetrates the third dielectric layer and the second insulating layer along the first direction, and connecting the interconnect structure to the second conductive structure.

[0023] An embodiment of the present disclosure provides a method for testing a semiconductor device, wherein the semiconductor device includes the semiconductor device as described in the above embodiment of the present disclosure; the method includes: contacting a pad structure at an opening with a probe to test the semiconductor structure.

[0024] In the embodiment of the present disclosure, a semiconductor structure is formed in a semiconductor layer, a first conductive structure is formed in a first dielectric layer, a second conductive structure penetrating the first dielectric layer and extending into the second dielectric layer is formed in the first dielectric layer and the second dielectric layer, and the semiconductor structure is connected to one end of the first conductive structure, and the other end of the first conductive structure is connected to the second conductive structure, and then a pad structure connected to the second conductive structure is formed in the second dielectric layer; in this way, on the one hand, the electrical test of the semiconductor structure can be achieved through the pad structure, and the reliability of the second conductive structure will not be affected by damage to the pad structure during the test; on the other hand, the pad structure and the second conductive structure are arranged in the same dielectric layer, so as to avoid the occurrence of problems such as delamination caused by irreversible deformation in subsequent process when the two are arranged in multiple layers; on the other hand, when the pad structure and the first conductive structure can be electrically connected, the two can be electrically isolated from each other, and then if the pad structure is removed, the first conductive structure will not be damaged, thereby improving the reliability of the semiconductor device, reducing the difficulty of the manufacturing process, increasing the manufacturing rate, and reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of an electronic device provided by an embodiment of the present disclosure; Figure 2a A schematic diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 2b A schematic diagram of a semiconductor device provided by another embodiment of the present disclosure; Figure 3 A schematic diagram of a manufacturing process of a semiconductor device provided by an embodiment of the present disclosure; Figure 4 A schematic cross-sectional view of a semiconductor layer and a semiconductor structure provided in one embodiment of the present disclosure; Figure 5 A schematic cross-sectional view of a first dielectric layer and a first conductive structure provided in one embodiment of the present disclosure; Figure 6 A cross-sectional schematic diagram of a pad structure provided by an embodiment of the present disclosure; Figure 7 A schematic cross-sectional view of a second dielectric layer provided in one embodiment of the present disclosure; Figure 8 A schematic cross-sectional view of a first etched hole and a second etched hole provided in an embodiment of the present disclosure; Fig. 9 A schematic cross-sectional view of a groove and a contact hole provided in an embodiment of the present disclosure; Fig.10 A schematic cross-sectional view of a barrier layer provided in one embodiment of the present disclosure; Fig.11 A schematic cross-sectional view of a second conductive structure and a third conductive structure provided in one embodiment of the present disclosure; Fig.12 A schematic cross-sectional view of a second insulating layer provided in one embodiment of the present disclosure; Fig.13 A cross-sectional schematic diagram of an opening provided in an embodiment of the present disclosure; Fig.14 A cross-sectional schematic diagram of testing a semiconductor structure using a testing device (such as a probe) provided in an embodiment of the present disclosure; Fig.15 A cross-sectional schematic diagram of a filling structure provided in one embodiment of the present disclosure; Fig.16 A schematic cross-sectional view of a third dielectric layer and an interconnect structure provided in one embodiment of the present disclosure; Fig.17 A cross-sectional schematic diagram of testing a semiconductor structure using a testing device (such as a probe) provided in another embodiment of the present disclosure; Fig.18 A schematic cross-sectional view of an opening and a window provided in an embodiment of the present disclosure; Fig.19 A cross-sectional schematic diagram of a filling structure provided by another embodiment of the present disclosure; Fig. 20 A schematic cross-sectional view of a third dielectric layer and an interconnect structure provided in accordance with another embodiment of the present disclosure.

[0026] In the above drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0027] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0028] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0029] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0031] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0034] Figure 1 Schematic diagram of an electronic device provided for an embodiment of the present disclosure. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein.

[0035] like Figure 1As shown, the electronic device 1 may include a storage system 10 and a host 20, and the storage system 10 may include a memory controller 110 and a memory device 120. The host 20 may include a processor, such as a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)). The memory controller 110 is coupled to both the host 20 and the memory device 120, and the memory controller 110 may be configured to communicate with the host 20 and control the memory device 120.

[0036] In some embodiments, the memory controller 110 may be configured to control operations of the memory device 120, such as a read operation, a write operation, an erase operation, a refresh operation, etc. In some embodiments, the memory controller 110 is further configured to process an error correction code (ECC) on data read from or written to the memory device 120. In other embodiments, the memory controller 110 may also be configured to perform any other suitable operations, such as formatting the memory device 120.

[0037] In some embodiments, the memory controller 110 may receive data, commands, and addresses from the host 20, and may send data, commands, and addresses to the memory device 120. Specifically, the memory controller 110 may include a command generator 111, an address generator 112, a device interface 113, and a host interface 114. The memory controller 110 may receive data, commands, and addresses from the host 20 through the host interface 114, decode the command received from the host 20 through the command generator 111 to generate an access command CMD, and may provide the access command CMD to the memory device 120 through the device interface 113. The memory controller 110 may generate an address ADDR to be accessed in the memory cell array 121 by decoding the address received from the host interface 114 through the address generator 112, and may provide the address ADDR to be accessed to the memory device 120 through the device interface 113. The access command CMD may be a signal instructing the memory device 120 to write or read data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR. In addition, the memory controller 110 may also send a refresh command to the memory device 120 . The refresh command may be a signal instructing the memory device 120 to read and rewrite data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR.

[0038] In some embodiments, reference Figure 1The memory device 120 includes a memory cell array 121 and a peripheral circuit 122. The memory cell array 121 may include a plurality of memory cells arranged in an array, and the peripheral circuit 122 may include a sense amplifier circuit, a row decoder, a column decoder, a data input / output buffer, etc. The peripheral circuit 122 is used to receive an access command CMD and an address ADDR. Based on the analysis of the access command CMD and the address ADDR, each memory cell in the memory cell array 121 may be independently accessed, and a read operation, a write operation, an erase operation, or a refresh operation, etc. may be performed on the data stored in the accessed memory cell.

[0039] In some specific examples, the memory device 120 can be a NAND Flash, a random access memory (RAM), such as a dynamic random access memory, a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a double data rate SDRAM (DDR SDRAM), a phase-change random access memory (PRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), etc.

[0040] With the development of semiconductor technology, the integration level of integrated circuit chips has reached the scale of hundreds of millions or even billions of semiconductor devices. Due to different requirements, the wiring design of integrated circuit chips has become more and more complicated. In order to meet the requirements, multiple semiconductor devices in an integrated circuit can be interconnected through a multi-layer interconnection structure. In practical applications, the design of the interconnection structure is limited by many aspects such as manufacturing process and component materials.

[0041] In some embodiments, the constituent materials of the interconnect structure may include various conductive materials such as gold (Au), silver (Ag), copper (Cu), and aluminum (Al). Aluminum is widely used in the integrated circuit manufacturing industry because of its high electrical conductivity and good corrosion resistance; compared with other metal materials such as gold, silver, and copper, aluminum has a lower cost, which makes it more cost-effective in large-scale production. In addition, aluminum is relatively soft, which makes it more effective and reliable in the bonding process, especially when used in conjunction with traditional bonding technologies such as gold wire ball bonding. The aluminum interconnection process is a relatively mature technology, and its stable process and mature technology can be widely used in ultra-large-scale integrated circuits.

[0042] However, although aluminum interconnect structures have good stability, they are relatively poor in resistivity and interconnect density. On the other hand, aluminum interconnect structures are easy to etch and may cause over-etching, which in turn affects the reliability of other structures connected to them; on the other hand, after the probe test, due to needle marks, lifting and other reasons, the subsequent removal of aluminum interconnect structures is usually accompanied by incomplete removal, which may lead to circuit failure, such as open circuit.

[0043] Based on this, in order to solve one or more of the above problems, a semiconductor device is provided in an embodiment of the present disclosure, referring to Figure 2a , Figure 2a A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present disclosure, such as Figure 2a As shown, the semiconductor device includes: a semiconductor layer 201, a first dielectric layer 202, and a second dielectric layer 203 stacked in sequence along a first direction; a semiconductor structure 204, located in the semiconductor layer 201; a first conductive structure 205, located in the first dielectric layer 202; the first conductive structure 205 is connected to the semiconductor structure 204; a second conductive structure 206, penetrating the second dielectric layer 203 along the first direction and extending into the first dielectric layer 202; here, the second conductive structure 206 is connected to an end of the first conductive structure 205 away from the semiconductor structure 204 along the first direction; a pad structure 207, located in the second dielectric layer 203; the pad structure 207 is connected to the second conductive structure 206, and the pad structure 207 and the first conductive structure 205 are isolated from each other; an opening 208, located in the second dielectric layer 203, and the opening 208 exposes the pad structure 207.

[0044] Based on this, by forming a semiconductor structure in the semiconductor layer, forming a first conductive structure in the first dielectric layer, forming a second conductive structure that penetrates the first dielectric layer and extends into the second dielectric layer in the first dielectric layer and the second dielectric layer, and connecting the semiconductor structure to one end of the first conductive structure, and connecting the other end of the first conductive structure to the second conductive structure, and then forming a pad structure connected to the second conductive structure in the second dielectric layer; in this way, on the one hand, the electrical test of the semiconductor structure can be realized through the pad structure, and the reliability of the second conductive structure will not be affected by the damage to the pad structure during the test; on the other hand, the pad structure and the second conductive structure are arranged in the same dielectric layer, so as to avoid the occurrence of problems such as delamination caused by irreversible deformation in the subsequent process when the two are arranged in multiple layers; on the other hand, when the pad structure and the first conductive structure can be electrically connected, the two can be electrically isolated from each other, and then if the pad structure is removed, the first conductive structure will not be damaged, thereby improving the reliability of the semiconductor device, reducing the difficulty of the manufacturing process, improving the manufacturing rate, and reducing the manufacturing cost.

[0045] In addition, it needs to be explained in detail that the second conductive structure can be used to realize functional interaction between the semiconductor structure and external devices, such as bonding and signal interaction; the pad structure can be used to realize testing of the semiconductor structure at different operating speeds.

[0046] The following is a detailed description Figure 2a Before illustrating the semiconductor device, various directions that may be used in the following description are defined. In the present disclosure, the stacking direction of multiple layers in the semiconductor device is defined as a first direction (i.e., the Z-axis direction). In a plane perpendicular to the Z-direction, an intersecting second direction (i.e., the X-axis direction) and a third direction (i.e., the Y-axis direction) are defined. In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction may be perpendicular to each other.

[0047] refer to Figure 2a The material of the semiconductor layer 201 includes silicon (Si); the material of the first dielectric layer 202 includes silicon oxide (SiO 2); the material of the second dielectric layer 203 includes silicon oxide, silicon carbide (SiC) or silicon carbon nitride (SiCN), etc.; the thickness of the semiconductor layer 201, the first dielectric layer 202 and the second dielectric layer 203 along the Z-axis direction can be set according to actual needs, and the present disclosure does not limit this. The method of forming the semiconductor layer 201, the first dielectric layer 202 and the second dielectric layer 203 includes but is not limited to a deposition process, and the deposition process includes chemical vapor deposition (Chemical Vapor Deposition, CVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD) process, etc.

[0048] A semiconductor structure 204 is provided in the semiconductor layer 201, and the semiconductor structure 204 may include a peripheral circuit and / or a memory cell array. The peripheral circuit may include a plurality of CMOS transistors and control circuits related to the CMOS transistors, such as control logic, sensing amplifier circuit, row decoder, column decoder, data input / output buffer, driver, and read / write circuit, etc., wherein, when the control logic receives a read / write operation command and address data, under the action of the control logic, the row decoder or column decoder may apply the corresponding voltage generated by the driver to the corresponding bit line and word line based on the decoded address to realize data reading or writing, and perform data interaction with an external device through the data input / output buffer. The memory cell array may include a plurality of memory cells, which may be NAND memory cells, PCM memory cells, DRAM memory cells, etc.

[0049] A first conductive structure 205 is provided in the first dielectric layer 202, and a second conductive structure 206 is provided in the first dielectric layer 202 and the second dielectric layer 203; wherein one end of the first conductive structure 205 along the Z-axis direction is connected to one end of the semiconductor structure 204 along the Z-axis direction; the other end of the first conductive structure 205 along the Z-axis direction is connected to one end of the second conductive structure 206 along the Z-axis direction; in other words, the first conductive structure 205 is located between the semiconductor structure 204 and the second conductive structure 206, and the first conductive structure 205 and the second conductive structure 206 can be used to lead out or lead in the electrical signal of the semiconductor structure 204. Here, the shapes of the first conductive structure 205 and the second conductive structure 206 can be set according to actual needs, and the present disclosure does not limit this.

[0050] The materials of the first conductive structure 205 and the second conductive structure 206 may be the same or different. Exemplarily, the materials of the first conductive structure 205 and / or the second conductive structure 206 include conductive materials, such as at least one of gold (Au), silver (Ag), copper (Cu), iron (Fe), nickel (Ni) and tin (Sn). The methods for forming the first conductive structure 205 and the second conductive structure 206 include but are not limited to deposition processes, etching processes, chemical mechanical polishing (CMP), etc.; deposition processes include CVD, LPCVD, PECVD, PVD, ALD processes, etc.; etching processes include photolithography etching, etc.

[0051] A pad structure 207 is also provided in the second dielectric layer 203, and the pad structure 207 is connected to the second conductive structure 206 and isolated from the first conductive structure 205. Here, one side of the pad structure 207 along the X-axis direction is connected to the second conductive structure 206. In this way, the electrical test of the semiconductor structure can be implemented through the pad structure, and the reliability of the second conductive structure will not be affected by the damage to the pad structure during the test process; in addition, the pad structure is electrically isolated from the first conductive structure, and then in the process of removing the pad structure, the first conductive structure will not be damaged, thereby improving the reliability of the semiconductor device, reducing the difficulty of the manufacturing process, increasing the manufacturing rate, and reducing the manufacturing cost.

[0052] The material of the pad structure 207 includes but is not limited to conductive materials, such as copper (Cu), etc. The thickness of the pad structure 207 along the Z-axis direction ranges from 0.5 to 3.0 micrometers (um). The method of forming the pad structure 207 includes but is not limited to a deposition process.

[0053] refer to Figure 2a , an opening 208 is also provided in the second dielectric layer 203; the method of forming the opening 208 includes but is not limited to an etching process. Here, the opening 208 can expose the pad structure 207; thus, the electrical property test of the semiconductor structure 204 can be implemented by contacting the pad structure 207 with a probe through the opening 208. Furthermore, the pad structure can be used to perform a variety of electrical property tests on the semiconductor structure at different stages, so that problematic semiconductor structures can be removed before packaging, saving packaging costs.

[0054] It should be noted that the number of semiconductor structures, first conductive structures, second conductive structures and pad structures in the semiconductor device can be one or more, and their arrangement can be set arbitrarily, which is not limited in the present disclosure.

[0055] In some embodiments, reference Figure 2a, the semiconductor device further includes: a barrier layer 209; the barrier layer 209 covers the sidewalls and the bottom surface of the second conductive structure 206; wherein a portion of the barrier layer 209 is located between the second conductive structure 206 and the pad structure 207. Here, the etching rate of the barrier layer 209 is lower than the etching rate of the pad structure 207; in other words, under the same etching conditions, the barrier layer 209 is less likely to be etched than the pad structure 207, so that the barrier layer 209 can protect the second conductive structure 206 from being etched during the removal of the pad structure 207, that is, the reliability of the second conductive structure 206 is guaranteed.

[0056] Continue to refer Figure 2a The barrier layer 209 is also located between the second conductive structure 206 and the first conductive structure 205, so that the conductivity of the second conductive structure 206 and the first conductive structure 205 can be increased. The material of the barrier layer 209 includes at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti) and titanium nitride (TiN). The method of forming the barrier layer 209 includes but is not limited to a deposition process.

[0057] In some embodiments, reference Figure 2a The semiconductor device further includes: a third conductive structure 210; the third conductive structure 210 penetrates the second dielectric layer 203 along the Z-axis direction and extends into the first dielectric layer 202, and the third conductive structure 210 and the second conductive structure 206 are arranged at intervals along the X-axis direction. The third conductive structure 210 and the second conductive structure 206 have the same material and the same formation method, and can be formed in the same process, which has been mentioned above and will not be repeated here.

[0058] In some embodiments, reference Figure 2a The semiconductor device further includes: a fourth conductive structure 211; the fourth conductive structure 211 is located in the first dielectric layer 202; the fourth conductive structure 211 and the first conductive structure 205 are arranged at intervals along the X-axis direction; one end of the fourth conductive structure 211 along the Z-axis direction is connected to the third conductive structure 210, and the other end of the fourth conductive structure 211 along the Z-axis direction is connected to the semiconductor structure 204. The fourth conductive structure 211 and the first conductive structure 205 have the same material and the same formation method, and can be formed in the same process technology, which has been mentioned before and will not be repeated here. Figure 2a The fourth conductive structure 211 is located between the third conductive structure 210 and the semiconductor structure 204. In this way, electrical signal communication of the semiconductor structure 204 can be achieved through the fourth conductive structure 211 and the third conductive structure 210.

[0059] In some embodiments, reference Figure 2aThe sidewall and bottom surface of the third conductive structure 210 are also conformally provided with a barrier layer 209 ; the barrier layer 209 can be used to increase the conductivity between the third conductive structure 210 and the fourth conductive structure 211 .

[0060] In some embodiments, reference Figure 2a , the semiconductor device further includes: a first insulating layer 213; the first insulating layer 213 is located in the first dielectric layer 202 and is located on the side of the first conductive structure 205 and the fourth conductive structure 211 away from the semiconductor structure 204 in the Z-axis direction; here, the second conductive structure 206 penetrates the first insulating layer 213 along the Z-axis direction and is connected to the first conductive structure 205, and the third conductive structure 210 penetrates the first insulating layer 213 along the Z-axis direction and is connected to the fourth conductive structure 211. The first insulating layer 213 is used to prevent the diffusion of materials of the first conductive structure 205 and the fourth conductive structure 211 to further improve the reliability of the semiconductor device. The material of the first insulating layer 213 includes but is not limited to silicon nitride (SiN). The method of forming the first insulating layer 213 includes but is not limited to a deposition process.

[0061] In some embodiments, reference Figure 2a , the semiconductor device further includes: a second insulating layer 214; the second insulating layer 214 is located on a side of the second dielectric layer 203 away from the first dielectric layer 202 along the Z-axis direction; the second insulating layer 214 covers the top surfaces of the second conductive structure 206 and the third conductive structure 210, where the top surface of the second conductive structure 206 and the bottom surface of the second conductive structure 206 are two surfaces of the second conductive structure 206 opposite to each other along the Z-axis direction, and the top surface of the third conductive structure 210 and the bottom surface of the third conductive structure 210 are two surfaces of the third conductive structure 210 opposite to each other along the Z-axis direction. The second insulating layer 214 is used to prevent the diffusion of materials of the second conductive structure 206 and the third conductive structure 210, so as to further improve the reliability of the semiconductor device. Here, the second insulating layer 214 is also used to form a dense buffer protection layer located above the pad structure 207 to protect the pad structure 207 from pressure damage. The material of the second insulating layer 214 includes but is not limited to silicon nitride. The method of forming the second insulating layer 214 includes but is not limited to a deposition process.

[0062] In other embodiments, reference Figure 2bThe semiconductor device further includes: a filling structure 212, located at the opening 208; the filling structure 212 covers the exposed surface of the pad structure 207 to enhance the reliability of the semiconductor device. When the second insulating layer 214 is not provided in the semiconductor structure, the top surface of the filling structure 212 can be flush with the top surface of the second dielectric layer 203 along the X-axis direction. When the second insulating layer 214 is provided in the semiconductor structure, the top surface of the filling structure 212 can be flush with the top surface of the second insulating layer 214 along the X-axis direction. The material of the filling structure 212 includes silicon oxide. The method of forming the filling structure 212 includes, but is not limited to, a deposition process.

[0063] In some embodiments, reference Figure 2b , the semiconductor device further includes: a third dielectric layer 215; the third dielectric layer 215 is located on a side of the second insulating layer 214 away from the second dielectric layer 203 along the Z-axis direction. The material of the third dielectric layer 215 can be the same as or different from the material of the filling structure 212; for example, the material of the third dielectric layer 215 includes silicon nitride, silicon oxide, silicon, etc. The method of forming the third dielectric layer 215 includes but is not limited to a deposition process. It should be noted that when the material of the third dielectric layer 215 is the same as the material of the filling structure 212, the filling structure 212 and the third dielectric layer 215 can be formed in the same process.

[0064] In some embodiments, reference Figure 2b The semiconductor device further includes: an interconnection structure 216; the interconnection structure 216 penetrates the third dielectric layer 215 and the second insulating layer 214 along the Z-axis direction; the interconnection structure 216 is respectively connected to one end of the second conductive structure 206 and the third conductive structure 210. The material of the interconnection structure 216 includes at least one of gold, silver, copper, iron, nickel tin and aluminum. The method of forming the interconnection structure 216 includes but is not limited to a deposition process. In this way, the electrical signal communication between the semiconductor structure 204 and the external device can be realized through the interconnection structure 216.

[0065] Based on the above semiconductor device, the present disclosure also provides a method for manufacturing a semiconductor device. Figure 3 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device in an embodiment of the present disclosure; Figure 3 As shown, the manufacturing method comprises the following steps: Step S301: forming a semiconductor layer, a first dielectric layer, and a second dielectric layer stacked in sequence along a first direction.

[0066] Step S302: forming a semiconductor structure in the semiconductor layer.

[0067] Step S303: forming a first conductive structure in the first dielectric layer, and connecting the first conductive structure to the semiconductor structure.

[0068] Step S304: forming a second conductive structure that penetrates the second dielectric layer along the first direction and extends into the first dielectric layer, and connecting the second conductive structure to an end of the first conductive structure that is away from the semiconductor structure along the first direction.

[0069] Step S305: forming a liner structure in the second dielectric layer, and connecting the liner structure to the second conductive structure, and isolating the liner structure from the first conductive structure.

[0070] Step S306: forming an opening in the second dielectric layer, and exposing the pad structure through the opening.

[0071] It should be understood that Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 3 The steps shown in the figure can be adjusted in sequence according to actual needs. Figures 4 to 20 The manufacturing process of the semiconductor device provided in the embodiment of the present disclosure is shown below. Figures 3 to 20 The manufacturing method of the semiconductor device provided by the embodiment of the present disclosure is introduced. The first direction is the Z-axis direction, the second direction is the X-axis direction, and the third direction is the Y-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction can be perpendicular to each other.

[0072] In some embodiments, reference Figure 4 , the method includes: providing a semiconductor layer 401; forming a semiconductor structure 402 in the semiconductor layer. Here, the material of the semiconductor layer includes silicon. The semiconductor structure includes a peripheral circuit and / or a memory cell array. The peripheral circuit may include a plurality of CMOS transistors and control circuits related to the CMOS transistors, such as control logic, a sense amplifier circuit, a row decoder, a column decoder, a data input / output buffer, a driver, and a read / write circuit, etc., wherein, when the control logic receives a read / write operation command and address data, under the action of the control logic, the row decoder or the column decoder may apply the corresponding voltage generated by the driver to the corresponding bit line and word line based on the decoded address to realize data reading or writing, and perform data interaction with an external device through the data input / output buffer. The memory cell array may include a plurality of memory cells, which may be NAND memory cells, PCM memory cells, DRAM memory cells, etc. The method of forming a peripheral circuit or a memory cell array in a semiconductor layer is relatively mature and will not be repeated here.

[0073] The method further comprises: referring to Figure 5, a first dielectric layer 403 is formed on one of the two opposite sides of the semiconductor layer 401 along the Z-axis direction. A first conductive structure 404 and a fourth conductive structure 405 are formed in the first dielectric layer 403, and a first insulating layer 406 is formed in the first dielectric layer 403 and on the side of the first conductive structure 404 and the fourth conductive structure 405 away from the semiconductor structure 402 in the Z-axis direction. Here, the first conductive structure 404 and the fourth conductive structure 405 are arranged along the X-axis direction; the first insulating layer 406 is used to prevent the material diffusion of the first conductive structure 404 and the fourth conductive structure 405. The specific formation process includes: depositing a layer of dielectric material on the surface of the semiconductor layer 401, etching the layer of dielectric material to form a plurality of grooves arranged along the X-axis direction, and filling the plurality of grooves with conductive material to form the first conductive structure 404 and the fourth conductive structure 405 arranged along the X-axis direction. A first insulating layer 406 is formed on the top surface of the first conductive structure 404 and the fourth conductive structure 405 and the surface of the dielectric material; then, a layer of dielectric material is deposited on the surface of the first insulating layer 406 to form the first dielectric layer 403. The method of depositing the first dielectric layer 403, the first conductive structure 404, the fourth conductive structure 405 and the first insulating layer 406 includes but is not limited to a deposition process, and the deposition process includes a CVD, LPCVD, PECVD, PVD, ALD process, etc. The material of the first dielectric layer 403 includes silicon oxide, the material of the first insulating layer 406 includes silicon nitride, and the material of the first conductive structure 404 and the fourth conductive structure 405 includes a conductive material, such as at least one of gold, silver, copper, iron, nickel and tin. The shapes of the first conductive structure 404 and the fourth conductive structure 405 can be the same or different, and the present disclosure is not limited to this.

[0074] It should be noted that both the first conductive structure 404 and the fourth conductive structure 405 may be connected to the semiconductor structure 402 to achieve electrical signal communication between the semiconductor structure 402 and other devices.

[0075] In some embodiments, reference Figure 6 , the method further includes: depositing a conductive material layer on the surface of one side away from the semiconductor layer 401 on two opposite sides of the first dielectric layer 403 along the Z-axis direction, and removing part of the conductive material layer by photolithography and etching to form a pad structure 407. The pad structure 407 and the first conductive structure 404, and the pad structure 407 and the fourth conductive structure 405 are electrically isolated from each other. The method for forming the pad structure 407 includes but is not limited to a deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc. Here, the thickness of the pad structure 407 along the Z-axis direction ranges from 0.5 to 3.0 micrometers (um). The material of the pad structure 407 includes conductive materials such as copper and aluminum.

[0076] It should be noted that the aluminum pad structure can be used on a large scale in integrated circuits, but the aluminum pad structure is easily damaged during the testing process. Based on this, after subsequent testing, the pad structure can choose a suitable retention method according to the different materials; there is a detailed description in the following text and will not be repeated here.

[0077] In some embodiments, reference Figure 7 The method further includes: forming a dielectric material layer on the remaining surface of the first dielectric layer 403 on the side away from the semiconductor layer 401 along the Z-axis direction and on the surface of the pad structure 407 that is exposed. The dielectric material layer is planarized to form a second dielectric layer 408. The material of the second dielectric layer 408 includes silicon oxide, silicon carbide or silicon carbon nitride, etc.; the method for forming the second dielectric layer 408 includes but is not limited to a deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc. The planarization process is but is not limited to chemical mechanical polishing.

[0078] In some embodiments, reference Figure 8 , the method further includes: forming a first etching hole 409 and a second etching hole 410 that penetrate the second dielectric layer 408 along the Z-axis direction and extend into the first dielectric layer 403; the first etching hole 409 and the second etching hole 410 are arranged at intervals along the X and / or Y-axis directions; here, the first etching hole 409 is closer to the pad structure 407 than the second etching hole 410. The formation process can adopt a Damascus copper wire process. Here, the first insulating layer 406 can serve as an etching stop layer for the first etching hole 409 and the second etching hole 410.

[0079] In some embodiments, reference Fig. 9 , the method further includes: using the first etching hole to remove part of the second dielectric layer 408 and part of the first insulating layer 406 to form a groove 411; the groove 411 exposes the top surface of the first conductive structure 404 in the Z-axis direction and exposes one side of the pad structure 407 in the X-axis direction. In other embodiments, the groove 411 can also expose part of the surface of the pad structure 407 in the Z-axis direction. At the same time, using the second etching hole to remove part of the second dielectric layer 408 and part of the first insulating layer 406 to form a contact hole 412. The contact hole 412 exposes the top surface of the fourth conductive structure 405 in the Z-axis direction. Here, the method of removing the second dielectric layer 408 and the first insulating layer 406 includes but is not limited to etching.

[0080] In some embodiments, reference Fig.10 The method further includes: forming a barrier layer 413 on the sidewalls and bottom surfaces of the groove 411 and the contact hole 412. Forming a seed layer ( Fig.10(not shown in the figure), that is, the seed layer covers the surface of the barrier layer. And, a conductive material layer 414 is deposited in the groove 411 and the contact hole 412 formed with the barrier layer 413 and the seed layer, and on the surface of the second dielectric layer 408. The material of the barrier layer 413 includes but is not limited to at least one of tantalum, tantalum nitride, titanium and titanium nitride; the material of the seed layer includes, for example, at least one of gold, silver, copper, iron, nickel and tin; the conductive material layer 414 includes at least one of gold, silver, copper, iron, nickel and tin; usually the material of the seed layer is the same as that of the conductive material layer. The method of forming the barrier layer 413, the seed layer and the conductive material layer 414 includes but is not limited to a deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0081] In some embodiments, reference Fig.11 The method further includes: performing a planarization process on the conductive material layer 414 to form a second conductive structure 415 in the groove formed with the barrier layer 413 and the seed layer, and forming a third conductive structure 416 in the contact hole formed with the barrier layer 413 and the seed layer. The second conductive structure 415 and the third conductive structure 416 are arranged at intervals along the X-axis direction, and the top surfaces of the second conductive structure 415 and the third conductive structure 416 are flush with the top surface of the second dielectric layer 408 along the X-axis direction. Here, the second conductive structure 415 is connected to the first conductive structure 404 through the barrier layer 413, and the third conductive structure 416 is connected to the fourth conductive structure 405 through the barrier layer 413.

[0082] It should be noted that, in conjunction with the reference Fig. 9 , Fig.10 and Fig.11 In the above process, the groove 411 exposes part of the surface of the pad structure 407, so that after the barrier layer 413 is formed, part of the barrier layer 413 covers the exposed surface of the pad structure 407. In other words, after the second conductive structure 415 is formed, the barrier layer 413 exists between the second conductive structure 415 and the pad structure 407. Based on the conductive properties of the barrier layer 413, the second conductive structure 415 and the pad structure 407 can be electrically connected.

[0083] In some embodiments, the etching rate of the barrier layer 413 is lower than the etching rate of the pad structure 407; in other words, under the same etching conditions, the barrier layer 413 is less likely to be etched than the pad structure 407, so that the barrier layer 413 can protect the second conductive structure 415 from being etched during the removal of the pad structure 407, thereby ensuring the reliability of the second conductive structure 415. In addition, the barrier layer 413 is also used to increase the conductivity between the second conductive structure 415 and the first conductive structure 404; and to increase the conductivity between the third conductive structure 416 and the fourth conductive structure 405.

[0084] In some embodiments, reference Fig.12 , the method further includes: forming a second insulating layer 417 on the top surface of the second conductive structure 415 and the third conductive structure 416 and the surface of the second dielectric layer 408. The second insulating layer 417 is used to prevent the material diffusion of the second conductive structure 415 and the third conductive structure 416. Based on the material properties of the second insulating layer 417, the second insulating layer 417 can also be used as a dense buffer protection layer to protect the pad structure, the second conductive structure, and the third conductive structure from damage. The material of the second insulating layer 417 includes but is not limited to silicon nitride. The method of forming the second insulating layer 417 includes but is not limited to a deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0085] In some embodiments, reference Fig.13 The method further includes: removing a portion of the second insulating layer 417 and a portion of the second dielectric layer 408 to form an opening 418. The opening 418 exposes the pad structure 407. The removal process includes but is not limited to dry etching. Based on this, in the above-mentioned semiconductor device of the present disclosure, reference Fig.14 The test device 500 (such as a probe) can be used to contact the pad structure 407 to implement electrical testing of the semiconductor structure 402 through the second conductive structure 415 and the first conductive structure 404. The electrical testing includes but is not limited to WAT testing (Wafer Acceptance Test) and CP testing (Chip Probing).

[0086] It should be noted that the reference Fig.13 or Fig.14 In the semiconductor device, a pad structure 407 and a high-density metal wiring layer (including a second conductive structure 415 and a third conductive structure 416) are formed in the same dielectric layer. In this way, the subsequent test packaging requirements of the semiconductor device can be met while having a high wiring density. Furthermore, the pad structure 407 and the metal wiring layer (including a second conductive structure 415 and a third conductive structure 416) are integrated in a dielectric layer, so that the structure that originally needs to be wired in two or more layers can be integrated in one layer, avoiding the occurrence of problems such as delamination of two or more layers due to irreversible deformation in the subsequent process. In addition, the overall dielectric layer thickness of the semiconductor device is reduced, which can also reduce the difficulty of warping management of the semiconductor device and the difficulty of the cutting process.

[0087] It should be noted that when the material of the pad structure 407 is copper, the damage caused by the probe 500 to the pad structure 407 during the test is small and can be ignored. In this way, after the semiconductor structure is tested using the pad structure, a filling structure can be directly formed at the opening 418, such as Fig.15 .

[0088] Specifically, refer to Fig.15 The method further includes: when the material of the pad structure 407 is copper, after testing the semiconductor structure 402 using the pad structure 407, forming a filling structure 419 at the opening. The top surface of the filling structure 419 is flush with the top surface of the second insulating layer 417 along the X-axis direction. The material of the filling structure 419 includes silicon oxide, and the method of forming the filling structure 419 includes but is not limited to a deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0089] In some embodiments, reference Fig.16 The method further includes: forming a third dielectric layer 420 on a side of the second insulating layer 417 away from the second dielectric layer 408 along the Z-axis direction; the material of the third dielectric layer 420 includes silicon oxide, and the method of forming the third dielectric layer 420 includes but is not limited to a deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc. In some specific embodiments, the filling structure 419 and the third dielectric layer 420 can be formed in the same process. In this way, the process flow can be saved and the manufacturing time can be saved.

[0090] Continue to refer Fig.16 , the method further includes: forming an interconnection structure 421 that penetrates the third dielectric layer 420 and the second insulating layer 417 along the Z-axis direction, and connecting the interconnection structure 421 to the second conductive structure 415 and the third conductive structure 416 respectively. In this way, the electrical signal communication between the semiconductor structure 402 and the external device can be achieved through the interconnection structure 421. The material of the interconnection structure 421 includes at least one of gold, silver, copper, iron, nickel, tin and aluminum. The method of forming the interconnection structure 421 includes but is not limited to a deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0091] In other embodiments, when the material of the pad structure 407 is aluminum, refer to Fig.17 During the test, the probe 500 may cause damage to the pad structure 407, such as warping 600, needle marks, etc. In this case, in order not to affect the subsequent formation of other structures, such as packaging, the damaged pad structure 407 needs to be removed, and then a filling structure is formed at the original position of the removed pad structure and the opening 418, such as Fig.18 , Fig.19 .

[0092] Specifically: Reference Fig.18 and Fig.19 , the method further includes: when the material of the pad structure is aluminum, after testing the semiconductor structure using the pad structure, removing the pad structure to form an opening 422 in situ of the pad structure; next, forming a filling structure 423 in situ of the pad structure (i.e., at the opening 422) and at the opening 418. Here, the removal process includes wet etching, and the etchant can be hydrofluoric acid (HF). It should be understood that after removing the pad structure, there will be no other failure risks caused by the pad structure to the etching process; in addition, the selection of the etchant should follow the removal of the pad structure (such as metal aluminum) while ensuring the integrity of the second conductive structure (such as metal copper) or the barrier layer.

[0093] In some embodiments, reference Fig. 20 The method further includes: forming a third dielectric layer 424 on a side of the second insulating layer 417 away from the second dielectric layer 408 along the Z-axis direction; and forming an interconnection structure 425 that penetrates the third dielectric layer 424 and the second insulating layer 417 along the Z-axis direction, and connecting the interconnection structure 425 to the second conductive structure 415 and the third conductive structure 416 respectively. Similarly, the third dielectric layer 424 and the filling structure 423 can be formed in the same process to save process flow and manufacturing time.

[0094] The material and formation method of the filling structure 423 described here are the same as the material and formation method of the filling structure 419 described in the aforementioned embodiment, the third dielectric layer 424 described here is the same as the third dielectric layer 420 described in the aforementioned embodiment, and the interconnection structure 425 described here is the same as the interconnection structure 421 described in the aforementioned embodiment, which have been described above and will not be repeated here. It should be noted that the method may also include: continuing to complete subsequent processes on the above-mentioned semiconductor device, such as a three-dimensional integrated hybrid bonding process, etc., which is not limited in this disclosure.

[0095] Based on this, in the embodiment of the present disclosure, a semiconductor structure is formed in a semiconductor layer, a first conductive structure is formed in a first dielectric layer, a second conductive structure is formed in the first dielectric layer and the second dielectric layer, and the semiconductor structure is connected to one end of the first conductive structure, and the other end of the first conductive structure is connected to the second conductive structure, and then a pad structure connected to the second conductive structure is formed in the second dielectric layer; in this way, on the one hand, the electrical test of the semiconductor structure can be achieved through the pad structure; on the other hand, the reliability of the second conductive structure will not be affected by damage to the pad structure during the test; on the other hand, when the pad structure and the first conductive structure can be electrically connected, the two can be electrically isolated from each other, and then in the subsequent process of removing the pad structure, the first conductive structure will not be damaged, thereby improving the reliability of the semiconductor device, reducing the difficulty of the manufacturing process, increasing the manufacturing rate, and reducing the manufacturing cost.

[0096] Based on the above-mentioned semiconductor device and its manufacturing method, the embodiment of the present disclosure also provides a storage system, including the semiconductor device as described in the above-mentioned embodiment of the present disclosure; and a memory controller coupled to the semiconductor device and used to control the semiconductor device.

[0097] Based on the above-mentioned semiconductor device and its manufacturing method, the embodiment of the present disclosure also provides a method for testing a semiconductor device, wherein the semiconductor device includes the semiconductor device as described in the above-mentioned embodiment of the present disclosure; the method includes: using a probe to contact a pad structure at an opening to test the semiconductor structure.

[0098] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0099] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor layer, a first dielectric layer, and a second dielectric layer are sequentially stacked along a first direction; A semiconductor structure located in the semiconductor layer; A first conductive structure, located in the first dielectric layer; The first conductive structure is connected to the semiconductor structure; a second conductive structure, penetrating the second dielectric layer along the first direction and extending into the first dielectric layer, the second conductive structure being connected to an end of the first conductive structure away from the semiconductor structure along the first direction; A liner structure, located in the second dielectric layer; The pad structure is connected to the second conductive structure, and the pad structure and the first conductive structure are isolated from each other; an opening located in the second dielectric layer; The opening exposes the pad structure.

2. The semiconductor device according to claim 1, characterized in that When the material of the pad structure is copper, the semiconductor device further comprises: a filling structure located at the opening; a top surface of the filling structure is flush with a top surface of the second dielectric layer along a second direction; and the second direction is perpendicular to the first direction.

3. The semiconductor device according to claim 2, characterized in that The semiconductor device further comprises: a barrier layer; the barrier layer covers the sidewalls and the bottom surface of the second conductive structure; Part of the barrier layer is located between the second conductive structure and the pad structure.

4. The semiconductor device according to claim 3, characterized in that The material of the barrier layer includes at least one of tantalum, tantalum nitride, titanium and titanium nitride; the material of the second conductive structure includes at least one of gold, silver, copper, iron, nickel and tin.

5. The semiconductor device according to claim 3, characterized in that The semiconductor device further includes: a third conductive structure, penetrating the second dielectric layer along the first direction and extending into the first dielectric layer, the third conductive structure and the second conductive structure being arranged at intervals along the second direction; and A fourth conductive structure is located in the first dielectric layer; the fourth conductive structure is connected to the third conductive structure and the semiconductor structure respectively; the fourth conductive structure and the first conductive structure are arranged at intervals along the second direction.

6. The semiconductor device according to claim 3, characterized in that The semiconductor device further includes: a first insulating layer, located in the first dielectric layer and located on a side of the first conductive structure away from the semiconductor structure in the first direction; The second conductive structure penetrates the first insulating layer along the first direction and is connected to the first conductive structure.

7. The semiconductor device according to claim 6, characterized in that The semiconductor device also includes: a second insulating layer, located on a side of the second dielectric layer away from the first dielectric layer along the first direction; the second insulating layer covers the top surface of the second conductive structure, and the top surface and the bottom surface are two opposite surfaces of the second conductive structure in the first direction.

8. The semiconductor device according to claim 7, characterized in that The semiconductor device further includes: a third dielectric layer located on a side of the second insulating layer away from the second dielectric layer along the first direction; and An interconnection structure penetrates the third dielectric layer and the second insulating layer along the first direction; the interconnection structure is connected to the second conductive structure.

9. A storage system, characterized in that: A semiconductor device comprising any one of claims 1 to 8; and The memory controller is coupled to the semiconductor device and is used to control the semiconductor device.

10. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Forming a semiconductor layer, a first dielectric layer, and a second dielectric layer sequentially stacked along a first direction; forming a semiconductor structure in the semiconductor layer; forming a first conductive structure in the first dielectric layer, and connecting the first conductive structure to the semiconductor structure; forming a second conductive structure penetrating the second dielectric layer along the first direction and extending into the first dielectric layer, and connecting the second conductive structure to an end of the first conductive structure away from the semiconductor structure along the first direction; forming a pad structure in the second dielectric layer, connecting the pad structure to the second conductive structure, and isolating the pad structure from the first conductive structure; An opening is formed in the second dielectric layer, and the pad structure is exposed through the opening.

11. The manufacturing method according to claim 10, characterized in that: The method further comprises: When the material of the pad structure is copper, a filling structure is formed at the opening after the semiconductor structure is tested using the pad structure.

12. The manufacturing method according to claim 10, characterized in that: The method further comprises: When the material of the pad structure is aluminum, after the semiconductor structure is tested using the pad structure, the pad structure is removed; and a filling structure is formed at the original position of the pad structure and at the opening.

13. The manufacturing method according to claim 11 or 12, characterized in that: The step of forming a liner structure in the second dielectric layer comprises: forming a pad structure on a portion of the surface of the first dielectric layer away from the semiconductor layer along the first direction; forming a dielectric material layer on the remaining surface of the first dielectric layer away from the semiconductor layer along the first direction and on the surface of the pad structure; The dielectric material layer is planarized to form a second dielectric layer.

14. The manufacturing method according to claim 13, characterized in that: The forming of a second conductive structure penetrating through the second dielectric layer along the first direction and extending into the first dielectric layer comprises: A groove is formed along the first direction, penetrating the second dielectric layer and extending into the first dielectric layer; the groove exposes the top surface of the first conductive structure in the first direction and exposes a side surface of the pad structure in the second direction; the first direction is perpendicular to the second direction; The second conductive structure is formed in the groove.

15. The manufacturing method according to claim 14, characterized in that: The forming the second conductive structure in the groove comprises: forming a barrier layer on the sidewall and bottom surface of the groove; The second conductive structure is formed in the groove where the barrier layer is formed.

16. The manufacturing method according to claim 15, characterized in that: The method further comprises: forming a third conductive structure penetrating the second dielectric layer along the first direction and extending into the first dielectric layer, and arranging the third conductive structure and the second conductive structure at intervals along the second direction; and A fourth conductive structure is formed in the first dielectric layer, and the fourth conductive structure is connected to the third conductive structure and the semiconductor structure respectively, and the fourth conductive structure and the first conductive structure are arranged at intervals along the second direction.

17. The manufacturing method according to claim 15, characterized in that: The method further comprises: A first insulating layer is formed in the first dielectric layer and on a side of the first conductive structure away from the semiconductor structure along the first direction; wherein the second conductive structure penetrates the first insulating layer along the first direction and is connected to the first conductive structure.

18. The manufacturing method according to claim 17, characterized in that: The method further comprises: A second insulating layer is formed on a side of the second dielectric layer away from the first dielectric layer along the first direction, and the second insulating layer covers a top surface of the second conductive structure.

19. The manufacturing method according to claim 18, characterized in that: The method further comprises: forming a third dielectric layer on a side of the second insulating layer away from the second dielectric layer along the first direction; An interconnection structure is formed along the first direction and penetrates the third dielectric layer and the second insulating layer, and the interconnection structure is connected to the second conductive structure.

20. A method for testing a semiconductor device, characterized in that: The semiconductor device comprises the semiconductor device as claimed in claim 1; the method comprises: The semiconductor structure is tested by contacting the pad structure at the opening with a probe.

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