Chip packaging structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a chip packaging structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to improve the reliability of the chip packaging structure. The chip packaging structure comprises a packaging substrate, a first chip, a supporting structure and a semiconductor chip set. The package substrate includes a first surface having a plurality of etch-back openings. The first chip is arranged on the first surface. The supporting structure is arranged on the first surface of the packaging substrate and located on at least one side of the first chip. The support structure covers the at least one etch-back opening, and the support structure fills the etch-back opening. The semiconductor chip set comprises a plurality of second chips which are stacked in the direction perpendicular to the first surface, the semiconductor chip set is arranged on the sides, away from the packaging substrate, of the first chips and the supporting structure, and the second chip closest to the first surface is connected with the first chips and the supporting structure. The chip packaging structure is used for chip packaging.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a chip packaging structure and a preparation method thereof, a storage system and an electronic device. Background Art

[0002] Multi-chip package (MCP) is an important step in the chip manufacturing process. It integrates multiple chips with different functions (such as storage chips and control chips, etc.) on a package substrate and fixes the multiple chips through a package layer (also called a package shell). In order to reduce the size of the chip package structure, the above-mentioned multiple chips can be stacked vertically. How to improve the reliability of the chip package structure is a problem that needs to be solved urgently in current chip packaging. Summary of the invention

[0003] Embodiments of the present disclosure provide a chip packaging structure and a preparation method thereof, a storage system and an electronic device, aiming to improve the reliability of the chip packaging structure.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a chip packaging structure is provided. The chip packaging structure includes a packaging substrate, a first chip, a support structure and a semiconductor chip group. The packaging substrate includes a first surface, and the first surface has a plurality of etch-back openings. The first chip is arranged on the first surface of the packaging substrate. The support structure is arranged on the first surface of the packaging substrate and is located on at least one side of the first chip. The support structure covers at least one etch-back opening, and the support structure fills the at least one etch-back opening. The semiconductor chip group includes a plurality of second chips stacked in a direction perpendicular to the first surface, the semiconductor chip group is arranged on a side of the first chip and the support structure away from the packaging substrate, and the second chip closest to the first surface is connected to the first chip and the support structure.

[0006] In the chip packaging structure provided by the embodiment of the present disclosure, the support structure and the first chip jointly support the semiconductor chipset, and the support structure can be used to support the portion of the semiconductor chipset extending out of the edge of the first chip, thereby reducing the risk of collapse of the portion of the semiconductor chipset extending out of the edge of the first chip. Moreover, the support structure can fill the etch-back opening of the first surface covered by the support structure, that is, the support structure can discharge the air in the etch-back opening, thereby reducing the risk of bubbles in the chip packaging structure at high temperature that may explode the chip packaging structure, thereby improving the reliability of the chip packaging structure.

[0007] In some embodiments, the material of the support structure includes epoxy resin. Compared with the use of blank chips to form a support structure between a semiconductor chipset and a package substrate in the related art, the material of the support structure provided by the embodiments of the present disclosure includes epoxy resin. Based on this, a filler curing process can be used to prepare the support structure, which can greatly reduce the preparation cost of the support structure.

[0008] In some embodiments, the support structure has a thickness D1, 20 μm≤D1≤150 μm.

[0009] In some embodiments, the support structure is away from a surface of the packaging substrate and is flush with a surface of the first chip away from the packaging substrate.

[0010] In some embodiments, the support structure includes a second surface connected to the semiconductor chipset, the second surface includes a plurality of corners, and at least a corner overlapping with a second chip closest to the first surface includes an obtuse angle and / or a curved angle.

[0011] In some embodiments, the support structure includes a plurality of support blocks, the plurality of support blocks surround the first chip, and a gap is provided between two adjacent support blocks.

[0012] In some embodiments, the plurality of support blocks include two first support blocks and two second support blocks. Along the first direction, the two first support blocks are respectively located on two opposite sides of the first chip, and the two first support blocks extend along the second direction, and at least parts of the two first support blocks are arranged oppositely along the first direction. Along the second direction, the two second support blocks are respectively located on two opposite sides of the first chip, and the two second support blocks extend along the first direction, and at least parts of the two second support blocks are arranged oppositely along the second direction. The first direction intersects with the second direction.

[0013] In some embodiments, an edge of at least one of the supporting blocks that is away from the first chip extends out from an edge of the second chip that is closest to the first chip.

[0014] In some embodiments, the first chip includes a control chip; and / or the second chip includes a memory chip.

[0015] On the other hand, a method for preparing a chip packaging structure is provided. The preparation method comprises: preparing a packaging substrate; the packaging substrate comprises a first surface, and the first surface comprises a plurality of etch-back openings. A mold is installed on the first surface of the packaging substrate; the mold comprises at least one mesh hole, the mesh hole exposes a portion of the first surface and exposes at least one etch-back opening. A filler is printed in the mold; the filler fills the at least one etch-back opening exposed by the mesh hole. The filler is cured to form a support structure, and the mold is removed. A first chip and a semiconductor chipset are installed on the first surface; the semiconductor chipset is arranged on a side of the first chip and the support structure away from the packaging substrate, and the semiconductor chipset comprises a plurality of second chips stacked in a direction perpendicular to the first surface, and the second chip closest to the first surface is connected to the first chip and the support structure.

[0016] In some embodiments, the mounting of the first chip and the semiconductor chipset on the first surface comprises: binding the first chip on the first surface, the first chip being connected to the package substrate. Filling an insulating structure at the bottom of the first chip. Arranging a plurality of second chips on a side of the first chip and the support structure away from the package substrate to form a semiconductor chipset. Connecting the plurality of second chips to the package substrate. Forming a package structure away from the support structure, the first chip, and the semiconductor chipset.

[0017] On the other hand, a storage system is provided, comprising the chip packaging structure as described above.

[0018] In another aspect, an electronic device is provided, comprising a processor and the storage system as described above, wherein the storage system is connected to the controller. Alternatively, the electronic device comprises a circuit board and the chip packaging structure as described above, wherein the chip packaging structure is connected to the circuit board.

[0019] It can be understood that the beneficial effects that can be achieved by the chip packaging structure preparation method, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the chip packaging structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 is a top view of a chip packaging structure according to some embodiments;

[0022] Figure 2 For along Figure 1 A cross-sectional view of the chip packaging structure along the section line AA;

[0023] Figure 3 is a structural diagram of a packaging substrate according to some embodiments;

[0024] Figure 4 is another top view of a chip packaging structure according to some embodiments;

[0025] Figure 5A to Figure 13 It is a process step diagram for preparing a chip packaging structure;

[0026] Fig.14 is a block diagram of a storage system according to some embodiments;

[0027] Fig.15 is a block diagram of an electronic device according to some embodiments;

[0028] Fig.16 is another block diagram of an electronic device according to some embodiments. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0030] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0031] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0032] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0033] When describing some embodiments, the expression "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0034] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0035] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0036] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0037] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0038] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0039] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0040] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0041] Some embodiments of the present disclosure provide a chip packaging structure 100. Figure 1 and Figure 2 The chip package structure 100 includes a package substrate 110 , a first chip 120 , a support structure 130 and a semiconductor chip group 140 .

[0042] The package substrate 110 has a certain rigidity to provide rigid support for the first chip 120, the support structure 130 and the semiconductor chip group 140. The package substrate 110 also has a certain elasticity to produce elastic deformation to reduce stress when the chip package structure 100 is bent or twisted.

[0043] The package substrate 110 includes a first surface 101 ( Figure 2 The first surface 101 is an upper surface of the package substrate 110 , and has a plurality of etch back openings (English: Etch Back Open) 102 .

[0044] For example, Figure 3As shown, the package substrate 110 includes a substrate body 11 , a conductive layer 12 and an insulating layer 13 disposed on the substrate body 11 .

[0045] Exemplarily, the material of the substrate body 11 may include an insulating material. For example, the substrate body 11 may be an epoxy resin-based substrate, a resin-based bismaleimide triazine (BT) substrate, or the like.

[0046] The conductive layer 12 can be used, for example, to lay out metal wiring and circuits, so as to connect with the first chip 120 and the semiconductor chipset 140. The material of the conductive layer includes, but is not limited to, metals such as gold, silver, copper, and aluminum.

[0047] For example, Figure 3 As shown, the conductive layer 12 may include a plurality of bonding contacts 14, and the surface of the bonding contacts 14 includes at least one electroplated metal layer. For example, the surface of the bonding contacts 14 includes a first metal layer 15 and a second metal layer 16. For example, the material of the first metal layer 15 may include nickel, and the material of the second metal layer 16 may include gold. The first metal layer 15 and the second metal layer 16 may be prepared by a surface electroplating process. After the electroplating is completed, in order to avoid leakage or static electricity accumulation on the package substrate 110, a metal etching back process is required. During the metal etching back process, an etching back opening 102 is formed on the first surface 101 of the package substrate 110.

[0048] Continue reading Figure 2 The first chip 120 is disposed on the first surface 101 of the package substrate 110. In some embodiments, the first chip 120 may include a control chip (also referred to as a controller), the first chip 120 is connected to the package substrate 110, and the first chip 120 is configured to control the semiconductor chipset 140.

[0049] An insulating structure 150 may be further included between the first chip 120 and the packaging substrate 110 . The insulating structure 150 may be, for example, insulating glue. The insulating glue may connect the first chip 120 to the packaging substrate 110 to reduce the risk of the first chip 120 falling off the first surface 101 .

[0050] The semiconductor chipset 140 is disposed on a side of the first chip 120 away from the packaging substrate 110 . That is, the first chip 120 and the semiconductor chipset 140 adopt a vertical packaging structure, which is beneficial to reducing the volume of the chip packaging structure 100 .

[0051] The semiconductor chipset 140 includes a plurality of second chips 41 stacked in a direction perpendicular to the package substrate 110. By way of example, the semiconductor chipset 140 may include 2, 4, 5, 8 or any other number of second chips 41, and the embodiments of the present disclosure are no longer listed one by one. In the following embodiments of the present disclosure, the semiconductor chipset 140 includes 4 second chips 41 as an example for schematic illustration. It can be understood that the embodiments of the present disclosure are not limited to this, as long as the same technical concept is adopted. In addition, the second chip 41 may include a memory chip. By way of example, the second chip 41 may be a chip such as 3D NAND or DRAM.

[0052] Exemplarily, the chip packaging structure 100 provided in the embodiment of the present disclosure may be a flash memory packaging product, such as a universal flash storage (UFS) or an embedded multimedia storage (eMMC). Based on this, the first chip 120 may be, for example, a control chip, and the plurality of second chips 41 included in the semiconductor chipset 140 may be storage chips such as 3D NAND or DRAM. Of course, in some other chip packaging products, the chip packaging structure 100 may also include but is not limited to a controller chip, a FR radio frequency chip, a positioning chip, a Bluetooth chip, a sensor chip or any other combination, as long as the same technical ideas as those of the present application are adopted.

[0053] like Figure 1 and Figure 2 As shown, the area of ​​the second chip 41 is generally larger than that of the first chip 120 , based on which the edge of the second chip 41 will extend beyond the edge of the first chip 120 , and the portion of the second chip 41 extending beyond the edge of the first chip 120 will form a cantilever structure.

[0054] In the related art, in order to prevent the portion of the second chip 41 extending out of the edge of the first chip 120 from bending or collapsing, a blank chip (English: Space Chip) is usually arranged between the second chip 41 and the packaging substrate 110. The blank chip may also be called a dummy chip (Dummy Die). The blank chip may be, for example, a silicon substrate. In the above solution provided by the related art, voids or bubbles may appear between the blank chip and the etched back opening of the packaging substrate. During the subsequent preparation or use of the chip packaging structure, the gas in the void may expand with temperature changes, thereby causing delamination between the blank chip and the packaging substrate, and may cause the semiconductor chipset to bulge or rupture, resulting in poor reliability of the chip packaging structure.

[0055] In order to solve the above technical problems, Figure 1and Figure 2 As shown, the chip package structure 100 provided in the embodiment of the present disclosure further includes a support structure 130. The support structure 130 is disposed on the first surface 101 of the package substrate 110. The semiconductor chipset 140 is also disposed on the side of the support structure 130 away from the package substrate 110, and the second chip 41 closest to the first surface 101 is connected to the support structure 130, that is, the support structure 130 is disposed between the first surface 101 of the package substrate 110 and the semiconductor chipset 140, and is connected to the second chip 41 of the semiconductor chipset 140 closest to the first surface 101, so that the support structure 130 can support the portion of the second chip 41 extending out of the edge of the first chip 120, thereby reducing the risk of bending or collapse of the second chip 41.

[0056] And, if Figure 2 and Figure 3 As shown, the support structure 130 also covers and fills at least one etch-back opening 102 covered by the support structure 130. In this way, the risk of generating voids and bubbles at the etch-back opening 102 between the support structure 130 and the first surface 101 of the packaging substrate 110 can be reduced, thereby reducing the risk of bulging or cracking of the semiconductor chip group 140, which is beneficial to improving the reliability of the chip packaging structure 100.

[0057] It should be noted that the preparation process of blank chips at least includes grinding, thinning, cutting and bonding, and the above processes require special equipment. Therefore, the method of forming a support structure from blank chips will greatly increase the preparation cost of the chip packaging structure, and the preparation efficiency of the chip packaging structure is low. In addition, in some other related connection technologies, the second chip adopts a chip wrapping film (English: Film Over Die; abbreviated as: FOD) structure, but this solution also faces the problem of high cost.

[0058] In some embodiments, the material of the support structure 130 includes epoxy resin, based on which the support structure 130 can be prepared by a filler curing process. Compared with the use of blank chips, not only can the step of processing the blank chips be omitted, thereby saving production costs, but also the production efficiency of the chip packaging structure can be improved. Moreover, compared with the use of the FOD process, the cost of epoxy resin itself is relatively low, thereby greatly reducing the material cost. Among them, the filler curing process refers to the preparation method of the chip packaging structure below.

[0059] It should be noted that when blank chips are used in chip packaging structures, the thickness of the blank chips usually needs to be customized, and there are certain restrictions on the thickness of blank chips. For example, when the thickness of the blank chips is too large (for example, greater than 75 μm), the risk of blank chips being broken is greater. When the thickness of the blank chips is too small (for example, less than 30 μm), a high-viscosity die attach film (English: Die Attach Film; abbreviated as: DAF) is required. It can be seen that the process window of blank chips is small, which is not conducive to improving the preparation efficiency of chip packaging structures.

[0060] like Figure 2 As shown, in the embodiment of the present disclosure, along the direction perpendicular to the first surface 101 ( Figure 2 The vertical direction in the support structure 130), the thickness of the support structure 130 is D1, wherein 20μm≤D1≤150μm. The support structure 130 is prepared by a filler curing process, and the molding thickness range of the support structure 130 is larger, and it can be applied to more types of chip packaging structures. In other words, the support structure 130 has higher compatibility. Moreover, in the case where the thickness of the support structure 130 is required to be larger (for example, the thickness is greater than 75μm), the structure of the support structure 130 is stable and will not cause the problem of fragmentation. In the case where the thickness of the support structure 130 is required to be smaller (for example, less than 30μm), the preparation process of the support structure 130 will hardly be affected. Exemplarily, the value of the thickness D1 of the support structure 130 can be 20μm, 30μm, 45μm, 80μm or 150μm, etc. Of course, the thickness D1 of the support structure 130 can also take other values, which are not specifically limited here, as long as the same technical ideas are adopted.

[0061] In some embodiments, see Figure 2 The surface of the support structure 130 away from the packaging substrate 110 (the upper surface of the support structure 130) is flush with the surface of the first chip 120 away from the packaging substrate 110 (the upper surface of the first chip 120). In this way, the second chip 41 included in the semiconductor chip group 140 can be arranged in a straight state (will not be bent or subjected to bending stress) on the surface of the first chip 120 and the support structure 130 away from the packaging substrate 110, which is beneficial to reduce the risk of bending or deformation of the second chip 41, improve the structural stability of the second chip 41, and reduce the risk of bending and breaking of the second chip 41.

[0062] It can be understood that due to the existence of measurement errors and process errors, the surface of the support structure 130 away from the packaging substrate 110 and the surface of the first chip 120 away from the packaging substrate 110 are flush, which may mean that the surface of the support structure 130 away from the packaging substrate 110 and the surface of the first chip 120 away from the packaging substrate 110, the height difference in the direction perpendicular to the first surface 101 is less than a preset value, and the preset value can be designed according to actual needs. For example, the preset value can be 0.5μm, 1μm or 2μm, etc., which is not specifically limited here, as long as the same technical idea is adopted.

[0063] In some embodiments, see Figure 4 The support structure 130 includes a second surface 131 connected to the semiconductor chipset 140, and the second surface 131 includes a plurality of corners. At least the corner overlapping with the second chip 41 closest to the package substrate 110 includes an obtuse angle and / or an arc angle. In this way, the contact stress between the semiconductor chipset 140 and the corner of the second surface 131 can be reduced, and the risk of stress concentration at the corner of the semiconductor chipset 140 (the second chip 41 closest to the package substrate 110) in contact with the second surface 131 can be reduced, and the risk of cracking of the semiconductor chipset 140 can be reduced.

[0064] Exemplarily, the support structure 130 includes a plurality of support blocks, and the plurality of support blocks are arranged around the first chip 120. In this case, the second surface includes the upper surfaces of the plurality of support blocks, and the shape of each upper surface is, for example, rectangular. In this case, the second surface 131 may include a plurality of corners, such as Figure 4 As shown, the shape of the second surface 131 of each support block 30 can be approximately rectangular, and the second surface 131 includes four corners. The four corners can all be arc-shaped corners, or the four corners can all be obtuse corners, or some of the four corners are arc-shaped corners and some are obtuse corners. Alternatively, when the support structure 130 includes multiple support blocks 30, the corner settings of the second surfaces 131 of the multiple support blocks 30 can be the same or different. For example, all corners of the second surfaces 131 of the multiple support blocks 30 are arc-shaped corners (such as Figure 4 As shown), or, the corners of the second surface 131 of some support blocks 30 include arc corners, and the corners of some support blocks 30 include obtuse corners. Of course, the multiple corners of the second surface 131 of multiple support blocks 30 can also be combined in other ways, as long as the same technical ideas are adopted. Alternatively, in some other embodiments, the support block 30 can even be set as a polygonal structure, such as a regular hexagon or octagon, etc.; or, the support block 30 can also be set as a circular or elliptical structure, etc.

[0065] In some embodiments, see Figure 4The support structure 130 includes a plurality of support blocks 30, and the plurality of support blocks 30 surround the first chip 120. Based on this, the four edges of the semiconductor chipset 140 extending out of the first chip 120 can be connected to the support structure 130, which is conducive to improving the support effect of the support structure 130 and further reducing the risk of bending or collapse of the semiconductor chipset 140. In addition, the geometric center of the projection of the semiconductor chipset 140 on the package substrate 110 can be roughly coincident with the geometric center of the orthographic projection of the first chip 120 on the package substrate 110, which is conducive to arranging the first chip 120 and the semiconductor chipset 140 in the central area of ​​the chip package structure 100, so that the first chip 120 and the semiconductor chipset 140 are subjected to uniform force. There is a gap 33 between two adjacent support blocks 30. Based on this, the mold used to prepare the support blocks 30 (see the preparation method of the chip package structure below) can be set as an integral structure to reduce the difficulty of preparing the support structure 130.

[0066] Continue reading Figure 4 , the plurality of support blocks 30 include two first support blocks 31 and two second support blocks 32. Along the first direction X, the two first support blocks 31 are respectively located on opposite sides of the first chip 120. In other words, the two first support blocks 31 and the first chip 120 are arranged along the first direction X, and the first chip 120 is located between the two first support blocks 31. Both of the two first support blocks 31 extend along the second direction Y, and at least parts of the two first support blocks 31 are arranged opposite to each other along the first direction X, that is, at least part of any first support block 31 is opposite to at least part of another first support block 31 in the first direction X; in this way, it is beneficial to improve the force uniformity of the semiconductor chip group 140. Wherein, the first direction X intersects with the second direction Y. Exemplarily, the first direction X and the second direction Y are perpendicular to each other.

[0067] Along the second direction Y, the two second support blocks 32 are respectively located on opposite sides of the first chip 120. In other words, the two second support blocks 32 and the first chip 120 are arranged along the second direction Y, and the first chip 120 is located between the two second support blocks 32. Both the two second support blocks 32 extend along the first direction X, and at least parts of the two second support blocks 32 are relatively arranged along the second direction Y, which is conducive to improving the force uniformity of the semiconductor chipset 140.

[0068] In one example, if Figure 4As shown, the two first support blocks 31 are relatively arranged in the first direction X, and the two first support blocks 31 are symmetrically arranged about the first chip 120. And / or, the two second support blocks 32 are relatively arranged in the second direction Y, and the two second support blocks 32 are symmetrically arranged about the first chip 120. In this way, the structural uniformity of the chip packaging structure 100 can be improved to the greatest extent, and the force uniformity of the chip packaging structure 100 can be improved. Of course, the embodiments of the present disclosure are not limited to this. For example, in some other embodiments, the sizes of the two first support blocks 31 may also be different, or the two first support blocks 31 may be partially staggered in the second direction Y, or the sizes of the two first support blocks 31 may also be different. The two second support blocks 32 may be partially staggered in the first direction X, and the sizes of the two second support blocks 32 may also be different, as long as the same technical ideas are adopted. In other words, Figure 4 The illustrated structure is merely an exemplary structure of the support structure 130 , and is not intended to limit the support structure 130 .

[0069] In some embodiments, Figure 4 As shown, the edge of at least one of the multiple support blocks 30, which is away from the first chip 120, extends out from the edge of the second chip 41 in the semiconductor chip group 140 that is closest to the first chip 120, that is, the outer boundary (the boundary away from the first chip) of at least one support block 30 is farther away from the first chip 120 than the boundary of the second chip 41 that is closest to the first chip 120. In this way, the edge of the second chip 41 that is closest to the first chip 120 can be within the range of the support block 30 and be supported by the support block 30, which can avoid the second chip 41 from forming a cantilever structure, and improve the support effect of the support structure 130 on the semiconductor chip group 140.

[0070] For example, Figure 4 As shown, the edges of the plurality of support blocks 30 away from the first chip 120 all extend out from the edge of the second chip 41 closest to the first chip 120 .

[0071] In addition, if Figure 2As shown, the chip packaging structure 100 may further include a plurality of connection wires 160 and a packaging layer 170. The plurality of second chips 41 and the first chip 120 included in the semiconductor chipset 140 may be connected to the packaging substrate 110 through the connection wires 160, and the first chip 120 may be connected to the semiconductor chipset 140 through the packaging substrate 110 to control the second chips included in the semiconductor chipset 140. The packaging layer 170 covers and wraps the first surface 101 of the packaging substrate 110, the first chip 120, the support structure 130, the semiconductor chipset 140 and the plurality of connection wires 160 to isolate the first surface 101 of the packaging substrate 110, the first chip 120, the support structure 130, the semiconductor chipset 140 and the plurality of connection wires 160 from the outside, and protect the first surface 101 of the packaging substrate 110, the first chip 120, the support structure 130 and the semiconductor chipset 140. The material of the packaging layer 170 includes but is not limited to epoxy molding compound (English: Epoxy Molding Compound, abbreviated: EMC).

[0072] Some other embodiments of the present disclosure further provide a method for preparing a chip packaging structure 100 . The method may include steps S00 to S500 .

[0073] S100, see Figure 5A , prepare a packaging substrate 110.

[0074] The package substrate 110 may be a substrate for forming one chip package structure 100. Alternatively, the package substrate 110 may also be a motherboard for forming multiple chip package structures 100. In the case where the package substrate 110 is used to form multiple chip package structures 100, Figure 5A As shown, the packaging substrate 110 includes a plurality of target regions 103 , and adjacent target regions 103 may include to-be-cut regions 104 . By cutting the to-be-cut regions of the packaging substrate 110 , each target region 103 may be cut to form an independent packaging substrate.

[0075] Based on Figure 5A When the chip packaging structure is prepared by the packaging substrate 110 shown in the figure, after the chip is packaged on the packaging substrate 110, a cutting process can be used to obtain multiple chip packaging structures, which is conducive to improving the preparation efficiency of the chip packaging structure. Figure 5A The packaging substrate 110 shown is taken as an example to exemplarily illustrate the present disclosure.

[0076] See also Figure 5B The package substrate 110 includes a first surface 101, and the first surface 101 includes a plurality of etch-back openings 102. The reason for the etch-back openings 102 is as described above, and other structures of the package substrate 110 are referred to above, which will not be repeated here.

[0077] S200, see Fig. 6A and Figure 6B , a mold 200 is installed on the first surface 101 of the packaging substrate 110 .

[0078] The mold 200 includes at least one mesh hole 210 , and the mesh hole 210 exposes a portion of the first surface 101 and exposes at least one etch-back opening 102 .

[0079] Exemplarily, the mold 200 includes at least one mesh hole 210 in each target region 103 , and the mesh hole 210 exposes a portion of the first surface 101 of the target region 103 and exposes at least one etch-back opening 102 .

[0080] In one example, if Fig. 6A As shown, the mold 200 includes four meshes 210 in each target area 103. The four meshes 210 are arranged along the circumference of the target area 103, and there is a gap between two adjacent meshes 210. The meshes 210 cannot separate the mold 200 into multiple separate parts. In other words, the mold 200 can be connected as a whole through the gaps between the meshes 210. This is convenient for the installation and removal of the mold 200.

[0081] Exemplarily, the mold 200 can be a wire mesh, which can also be called a steel mesh. Of course, the mold can also be other structures as long as the same technical concept is adopted.

[0082] S300, see Fig. 7A and Figure 7B , a filler 300 is printed in the mesh 210 of the mold 200 .

[0083] like Figure 7B As shown, the filler 300 fills at least one etch-back opening 102 exposed by the mesh 210. For example, the material of the filler 300 may include epoxy resin. That is, the filler may be printed on the package substrate 110 by screen printing technology.

[0084] S400, see Fig. 8A and Figure 8B , the mold 200 is removed, and the filler 300 is cured to form the support structure 130 .

[0085] For example, the filler 300 may be cured by heat curing to form the support structure 130, such as by baking. The filler 300 in each mesh 210 forms a support block 30, and multiple support blocks 30 in a target area 103 together form the support structure 130.

[0086] In the embodiment of the present disclosure, the support structure 130 is prepared by a filler curing method, so that the etch-back opening 102 covered by the support structure 130 can be filled, thereby reducing the risk of voids and bubbles between the support structure 130 and the package substrate 110. Moreover, compared with the use of blank chips to form a support structure in the related art, the preparation method of the support structure 130 provided in the embodiment of the present disclosure can significantly reduce the preparation cost of the support structure and significantly improve the preparation efficiency of the support structure 130.

[0087] S500 , mounting the first chip 120 and the semiconductor chip group 140 on the first surface 101 .

[0088] The semiconductor chipset 140 is disposed on a side of the first chip 120 and the support structure 130 away from the packaging substrate 110, and the semiconductor chipset 140 includes a plurality of second chips 41 stacked in a direction perpendicular to the first surface 101, and the second chip 41 closest to the packaging substrate 110 is connected to the first chip 120 and the support structure 130.

[0089] In some embodiments, the above S500 of mounting the first chip 120 and the semiconductor chipset 140 on the first surface 101 may include S510 to S540.

[0090] S510, see Fig.9A and Fig. 9B , the first chip 120 is bonded to the first surface 101 .

[0091] The first chip 120 is connected to the package substrate 110, illustratively, as Fig.9A As shown, when the support structure 130 includes a plurality of support blocks 30 , the first chip 120 is disposed in the middle of the plurality of support blocks 30 included in the support structure 130 , that is, the plurality of support blocks 30 are disposed around the first chip 120 .

[0092] S520, see Fig.10 , an insulating structure 150 is filled at the bottom of the first chip 120 .

[0093] Exemplarily, the insulating structure 150 may include insulating glue, which can not only fill the gap between the first chip 120 and the packaging substrate 110, but also help to increase the connection stability between the first chip 120 and the packaging substrate 110, and reduce the risk of breakage of connecting solder joints due to different thermal expansion of various materials during the preparation process of the chip packaging structure.

[0094] S530, see Fig.11A and Fig. 11BA plurality of second chips 41 are disposed on a side of the first chip 120 and the support structure 130 away from the package substrate 110 to form a semiconductor chip group 140 .

[0095] Exemplarily, the plurality of second chips 41 may be staggered so that the second chip 41 far from the package substrate 110 can expose the pad of the second chip 41 close to the package substrate 110, so as to facilitate the subsequent connection between the second chip 41 and the package substrate 110. Two adjacent second chips 41 may be bonded by an adhesive layer, and the second chip 41 closest to the package substrate 110 may also be bonded to the first chip 120 and the support structure 130 by an adhesive layer. The adhesive layer may be DAF (full name: Die Attach Film) glue.

[0096] S540, see Fig.12 , connecting the plurality of second chips 41 to the packaging substrate 110 .

[0097] Exemplarily, the second chips 41 may be connected in sequence through the connection wires 160 , and connected to the package substrate 110 through the connection wires 160 .

[0098] S550, see Fig.13 , a packaging layer 170 is formed on the support structure 130 , the first chip 120 and the semiconductor chip group 140 .

[0099] Exemplarily, the material of the encapsulation layer 170 may include but is not limited to epoxy molding compound (English: Epoxy Molding Compound; abbreviated: EMC).

[0100] Some embodiments of the present disclosure also provide a storage system 400. Fig.14 As shown, the storage system includes the chip packaging structure 100 and a controller 410 in any of the above embodiments.

[0101] The storage system can be integrated into various types of storage devices, such as a universal flash storage package UFS or an embedded multimedia card package eMMC. That is, the storage system can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0102] In some embodiments, the storage system may be integrated into a memory card, wherein the memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0103] In other embodiments, the storage system may also be integrated into a solid state drive (SSD).

[0104] In the storage system 400, in some embodiments, the controller 410 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0105] In other embodiments, the controller 410 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0106] In some embodiments, the controller 410 may be configured to manage data stored in the chip package structure 100 and communicate with an external device (e.g., a host). In some embodiments, the controller 410 may also be configured to control operations of the chip package structure 100, such as read, erase, and program operations. In some embodiments, the controller 410 may also be configured to manage various functions regarding data stored or to be stored in the chip package structure 100, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 410 is also configured to process error correction codes for data read from or written to the chip package structure 100.

[0107] Of course, the controller 410 may also perform any other suitable functions, such as formatting the chip package structure 100 ; for example, the controller 410 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0108] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0109] Some embodiments of the present disclosure also provide an electronic device 500. Fig.15 The electronic device 500 may include the storage system 400 described above, and may also include at least one of a processor (Central Processing Unit: CPU) 510 and a cache. The storage system 400 is connected to the processor 510, and the processor 510 is used to control the storage system 400. Alternatively, refer to Fig.16 The electronic device 500 may further include the chip packaging structure 100 and a circuit board 520 as described above. The circuit board 520 is connected to the chip packaging structure 100 to control the chip packaging structure 100 .

[0110] The above-mentioned electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0111] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, It is characterized in that include: A packaging substrate, comprising a first surface, wherein the first surface has a plurality of etch-back openings; A first chip is disposed on a first surface of the packaging substrate; A support structure, disposed on the first surface of the package substrate and located on at least one side of the first chip, the support structure covering at least one etch-back opening, and the support structure filling the at least one etch-back opening; A semiconductor chipset comprises a plurality of second chips stacked in a direction perpendicular to the packaging substrate. The semiconductor chipset is arranged on a side of the first chip and the support structure away from the packaging substrate, and the second chip closest to the first surface is connected to the first chip and the support structure.

2. The chip packaging structure according to claim 1, It is characterized in that The material of the support structure includes epoxy resin.

3. The chip packaging structure according to claim 1, It is characterized in that The thickness of the support structure is D1, 20 μm≤D1≤150 μm.

4. The chip packaging structure according to claim 1, It is characterized in that The support structure is away from a surface of the packaging substrate and is flush with a surface of the first chip away from the packaging substrate.

5. The chip packaging structure according to claim 1, It is characterized in that The support structure includes a second surface connected to the semiconductor chip group, the second surface includes a plurality of corners, and at least a corner of the plurality of corners overlapping with a second chip closest to the first surface includes an obtuse angle and / or a curved angle.

6. The chip packaging structure according to any one of claims 1 to 5, It is characterized in that The support structure includes a plurality of support blocks, the plurality of support blocks surround the first chip, and a gap is provided between two adjacent support blocks.

7. The chip packaging structure according to claim 6, It is characterized in that The plurality of support blocks include: Two first support blocks, along a first direction, the two first support blocks are respectively located on two opposite sides of the first chip, and the two first support blocks extend along a second direction, and at least parts of the two first support blocks are arranged opposite to each other along the first direction; the first direction intersects with the second direction; Two second support blocks are respectively located on two opposite sides of the first chip along the second direction, and both of the two second support blocks extend along the first direction, and at least parts of the two second support blocks are relatively arranged along the second direction.

8. The chip packaging structure according to claim 7, It is characterized in that An edge of at least one of the supporting blocks that is away from the first chip extends out from an edge of a second chip that is closest to the first chip.

9. The chip packaging structure according to claim 1, It is characterized in that The first chip includes a control chip; and / or the second chip includes a storage chip.

10. A method for preparing a chip packaging structure, It is characterized in that The preparation method comprises: Prepare a packaging substrate; the packaging substrate comprises a first surface, and the first surface comprises a plurality of etch-back openings; A mold is mounted on the first surface of the package substrate; the mold comprises at least one mesh hole, the mesh hole exposes a portion of the first surface and exposes at least one etch-back opening; Printing a filler in the mesh of the mold; the filler fills at least one etch-back opening exposed by the mesh; removing the mold and curing the filler to form a support structure; A first chip and a semiconductor chipset are mounted on the first surface; the semiconductor chipset is disposed on a side of the first chip and the support structure away from the packaging substrate, and the semiconductor chipset includes a plurality of second chips stacked in a direction perpendicular to the first surface, and the second chip closest to the first surface is connected to the first chip and the support structure.

11. The preparation method according to claim 10, It is characterized in that The step of mounting the first chip and the semiconductor chipset on the first surface comprises: Binding the first chip on the first surface, wherein the first chip is connected to the packaging substrate; Filling an insulating structure at the bottom of the first chip; Arrange a plurality of second chips on a side of the first chip and the support structure away from the packaging substrate to form a semiconductor chip group; connecting a plurality of second chips to the packaging substrate; A packaging structure is formed on the support structure, the first chip and the semiconductor chip group.

12. A storage system, It is characterized in that The invention comprises a chip packaging structure as claimed in any one of claims 1 to 9.

13. An electronic device, It is characterized in that comprising a processor and the storage system according to claim 12, wherein the storage system is connected to the controller; or, The electronic device comprises a circuit board and a chip packaging structure according to any one of claims 1 to 9, wherein the chip packaging structure is connected to the circuit board.

Images