Inverter

Abstract

The invention relates to the technical field of inverters, in particular to an inverter. The invention aims to solve the problem that the voltage stress of the switching tube on the third bridge arm is increased to influence the normal work of the third bridge arm. The embodiment of the invention provides an inverter. The inverter comprises a first bridge arm, a second bridge arm, a third bridge arm and a voltage absorption circuit. The first bridge arm comprises a first switching tube and a second switching tube which are connected in series, and the second bridge arm comprises a third switching tube and a fourth switching tube which are connected in series. The third bridge arm is connected between the first node and the second node. The third bridge arm comprises a fifth switch tube and a sixth switch tube which are connected in series. In the switching-on process of the first bridge arm or the second bridge arm, the voltage absorption circuit can absorb electric energy of the input end of the fifth switch tube or the input end of the sixth switch tube and release the absorbed electric energy to the negative direct current bus, so that voltage stress at the two ends of the fifth switch tube and the sixth switch tube is reduced, and normal work of the third bridge arm is guaranteed.

Description

Technical Field

[0001] The present application relates to the technical field of inverters, and in particular to an inverter. Background Art

[0002] The inverter includes an inverter circuit, and the inverter circuit includes a first bridge arm and a second bridge arm for connecting a positive DC bus and a negative DC bus, and a third bridge arm connected between the first bridge arm and the second bridge arm. During the opening of the first bridge arm and the second bridge arm, the switch tube on the third bridge arm is in an alternately turned-on state, and the switch tube on the third bridge arm is turned on and off at a high speed. During the high-speed on and off of the switch tube, the rate of change of the current passing through the third bridge arm is accelerated, which will generate a large overvoltage on the switch tube on the third bridge arm, resulting in an increase in the voltage stress of the switch tube on the third bridge arm, affecting the normal operation of the third bridge arm. Summary of the invention

[0003] The embodiments of the present application relate to the technical field of inverters, and specifically to an inverter that can reduce the voltage stress at both ends of a switch tube on a third bridge arm to ensure the normal operation of the third bridge arm.

[0004] In a first aspect, an embodiment of the present application provides an inverter, comprising a first bridge arm, a second bridge arm, a third bridge arm and a voltage absorption circuit. The first bridge arm is used to connect between a positive DC bus and a negative DC bus, and the first bridge arm comprises a first switch tube and a second switch tube connected in series. The second bridge arm is used to connect between a positive DC bus and a negative DC bus, and the second bridge arm comprises a third switch tube and a fourth switch tube connected in series. The third bridge arm is connected between a first node and a second node, the first node is a connection point between the first switch tube and the second switch tube, and the second node is a connection point between the third switch tube and the fourth switch tube; the third bridge arm comprises a fifth switch tube and a sixth switch tube connected in series.

[0005] The voltage absorption circuit is connected to the input end of the fifth switch tube and the input end of the sixth switch tube, and is used to connect to the positive DC bus and the negative DC bus; the voltage absorption circuit is used to absorb the electric energy of the input end of the fifth switch tube or the input end of the sixth switch tube during the process of opening the first bridge arm or the second bridge arm, and release the absorbed electric energy to the negative DC bus.

[0006] The voltage absorption circuit provided in the embodiment of the present application is connected to the positive DC bus and the negative DC bus, and the operating voltage of the voltage absorption circuit can be limited to the bus voltage. When the voltage on the third bridge arm is less than the bus voltage, the voltage absorption circuit does not work, and does not affect the opening current of the first bridge arm and the second bridge arm; when the voltage on the third bridge arm is greater than the bus voltage, the voltage absorption circuit works, and can absorb the electric energy exceeding the bus voltage (i.e., the overvoltage part) and release it to the bus, thereby reducing the voltage stress at both ends of the fifth switch tube and the sixth switch tube, and ensuring the normal operation of the third bridge arm.

[0007] In addition, the voltage absorption circuit provided in the embodiment of the present application can reduce the turn-on current on the first bridge arm and the second bridge arm, thereby reducing the turn-on loss. At the same time, in the embodiment of the present application, the electrical energy of the overvoltage part is released back to the busbar, which can avoid energy loss and improve energy utilization.

[0008] In some embodiments that may include the above embodiments, the voltage absorption circuit includes a first subcircuit and a second subcircuit. The input end of the fifth switch tube is connected to the first node, the input end of the sixth switch tube is connected to the second node, and the output end of the fifth switch tube is connected to the output end of the sixth switch tube. The first subcircuit includes a first diode and a first capacitor, the anode of the first diode is connected to the input end of the fifth switch tube, the cathode of the first diode is connected to the first end of the first capacitor, the first end of the first capacitor is also connected to the positive DC bus, and the second end of the first capacitor is connected to the negative DC bus.

[0009] The second subcircuit includes a second diode and a second capacitor, the anode of the second diode is connected to the input end of the sixth switch tube, the cathode of the second diode is connected to the first end of the second capacitor, the first end of the second capacitor is also connected to the positive DC bus, and the second end of the second capacitor is connected to the negative DC bus.

[0010] The first diode can ensure that when there is an overvoltage on the fifth switch tube, the first capacitor absorbs the overvoltage on the fifth switch tube. The second diode can ensure that when there is an overvoltage on the sixth switch tube, the second capacitor absorbs the overvoltage on the sixth switch tube. The first capacitor and the second capacitor can release the electrical energy of the overvoltage part to the bus, so that the electrical energy of the overvoltage part is recovered, thereby reducing the energy loss of the inverter.

[0011] In some embodiments that may include the above embodiments, the voltage absorption circuit further includes a third diode. The anode of the third diode is connected to the second end of the first capacitor and the second end of the second capacitor, and the cathode of the third diode is connected to the output end of the fifth switch tube and the output end of the sixth switch tube.

[0012] The second end of the first capacitor is connected to the output end of the fifth switch tube through the third diode, which can ensure that the first capacitor is directly connected in parallel at both ends of the fifth switch tube, shortening the absorption loop, so that the first capacitor absorbs the overvoltage at both ends of the fifth switch tube, ensuring the effect of the voltage absorption circuit.

[0013] At the same time, since the voltage value of the output end of the fifth switch tube is not equal to the voltage value of the negative DC bus, the output end of the fifth switch tube cannot be directly connected to the second end of the first capacitor. The anode of the third diode is connected to the second end of the first capacitor, and the cathode of the third diode is connected to the input end of the fifth switch tube, which can avoid the output end of the fifth switch tube from being connected to the negative DC bus, avoid the short circuit of the wire between the two, and ensure the normal operation of the voltage absorption circuit.

[0014] Similarly, the third diode can also ensure that the second capacitor is directly connected in parallel to the two ends of the sixth switch tube, shortening the absorption loop, so that the second capacitor absorbs the overvoltage at the two ends of the sixth switch tube, ensuring the effect of the voltage absorption circuit. At the same time, the third diode can also prevent the output end of the sixth switch tube from being connected to the negative DC bus, avoiding a short circuit of the wire between the two, and ensuring the normal operation of the voltage absorption circuit.

[0015] In some embodiments that may include the above embodiments, the voltage absorption circuit further includes a first resistor. One end of the first resistor is connected to the second end of the first capacitor and the second end of the second capacitor, and the other end of the first resistor is connected to the negative DC bus.

[0016] The first resistor is arranged on the cathode side of the first diode and the second diode, which can limit the current passing through the first diode and the second diode, and prevent the first diode and the second diode from being broken down by excessive current and voltage when they are turned on, thereby preventing the first diode and the second diode from being damaged.

[0017] In some embodiments that may include the above embodiments, the voltage absorption circuit further includes a first resistor and a second resistor. The first resistor is connected between the second end of the first capacitor and the negative DC bus, and the second resistor is connected between the second end of the second capacitor and the negative DC bus.

[0018] The first resistor is located on the cathode side of the first diode, which can limit the current passing through the first diode, and can prevent the first diode from being broken down by excessive current and voltage when it is turned on, thereby ensuring the normal use of the first diode. The second resistor is located on the cathode side of the second diode, which can limit the current passing through the second diode, and can prevent the second diode from being broken down by excessive current and voltage when it is turned on, thereby ensuring the normal use of the second diode.

[0019] In some embodiments that may include the above embodiments, the voltage absorption circuit further includes a third resistor and a fourth resistor. The third resistor is connected between the first end of the first capacitor and the positive DC bus, and the fourth resistor is connected between the first end of the second capacitor and the positive DC bus.

[0020] The third resistor can prevent the first diode from being broken down by excessive current and voltage when it is turned on, thereby ensuring the normal use of the first diode. The fourth resistor can prevent the second diode from being broken down by excessive current and voltage when it is turned on, thereby ensuring the normal use of the second diode.

[0021] In some embodiments that may include the above embodiments, the voltage absorption circuit includes a third subcircuit and a fourth subcircuit, the input end of the fifth switch tube is connected to the input end of the sixth switch tube, the output end of the fifth switch tube is connected to the first node, and the output end of the sixth switch tube is connected to the second node. The third subcircuit includes a fourth diode and a third capacitor, the anode of the fourth diode is connected to the input end of the fifth switch, the cathode of the fourth diode is connected to the first end of the third capacitor, the first end of the third capacitor is also connected to the positive DC bus, and the second end of the third capacitor is connected to the negative DC bus;

[0022] The fourth subcircuit includes a fourth diode and a fourth capacitor, the anode of the fourth diode is connected to the input end of the sixth switch tube, the cathode of the fourth switch tube is connected to the first end of the fourth capacitor, the first end of the fourth capacitor is also connected to the positive DC bus, and the second end of the fourth capacitor is connected to the negative DC bus.

[0023] The fourth diode can ensure that when there is an overvoltage on the fifth switch tube, the third capacitor absorbs the overvoltage on the fifth switch tube. The fourth diode can also ensure that when there is an overvoltage on the sixth switch tube, the fourth capacitor absorbs the overvoltage on the sixth switch tube. The third capacitor and the fourth capacitor can release the electrical energy of the overvoltage part to the bus, so that the electrical energy of the overvoltage part is recovered, thereby reducing the energy loss of the inverter.

[0024] In some embodiments that may include the above embodiments, the voltage absorption circuit further includes a fifth diode and a sixth diode. The anode of the fifth diode is connected to the second end of the third capacitor, and the cathode of the fifth diode is connected to the first node; the anode of the sixth diode is connected to the second end of the fourth capacitor, and the cathode of the sixth diode is connected to the second node.

[0025] The fifth diode can ensure that the third capacitor is directly connected in parallel to the two ends of the fifth switch tube, absorb the overvoltage at the two ends of the fifth switch tube, and ensure the effect of the voltage absorption circuit. In addition, since the voltage value of the output end of the fifth switch tube is not equal to the voltage value of the negative DC bus, the output end of the fifth switch tube cannot be directly connected to the second end of the first capacitor. The anode of the fifth diode is connected to the second end of the third capacitor, and the cathode of the fifth diode is connected to the input end of the fifth switch tube, which can avoid the output end of the fifth switch tube from being connected to the negative DC bus, avoid the short circuit of the wire between the two, and ensure the normal operation of the voltage absorption circuit.

[0026] Similarly, the sixth diode can ensure that the fourth capacitor is directly connected in parallel to the two ends of the sixth switch tube, absorb the overvoltage at the two ends of the sixth switch tube, and ensure the effect of the voltage absorption circuit. The sixth diode can also prevent the output end of the sixth switch tube from being connected to the negative DC bus, avoid the short circuit of the wire between the two, and ensure the normal operation of the voltage absorption circuit.

[0027] In some embodiments that may include the above embodiments, the voltage absorption circuit further includes a fifth resistor and a sixth resistor. The fifth resistor is connected between the second end of the third capacitor and the negative DC bus, and the sixth resistor is connected between the second end of the fourth capacitor and the negative DC bus.

[0028] The fifth resistor and the sixth switch tube are located on the cathode side of the fourth switch tube, which can limit the current passing through the fourth switch tube, prevent the fourth switch tube from being broken down by excessive current and voltage when it is turned on, and ensure the normal use of the fourth switch tube.

[0029] In some embodiments that may include the above embodiments, the voltage absorption circuit further includes a seventh resistor. One end of the seventh resistor is connected to the first end of the third capacitor and the first end of the fourth capacitor, and the other end of the seventh resistor is connected to the positive DC bus.

[0030] The seventh resistor is located on the cathode side of the fourth switch tube, and can limit the current passing through the fourth switch tube, prevent the fourth switch tube from being broken down by excessive current and voltage when it is turned on, and ensure the normal use of the fourth switch tube.

[0031] In some embodiments that may include the above embodiments, the voltage absorption circuit further includes a seventh resistor and an eighth resistor. The seventh resistor is connected between the first end of the third capacitor and the positive DC bus, and the eighth resistor is connected between the first end of the fourth capacitor and the positive DC bus.

[0032] The seventh resistor and the eighth resistor are located on the cathode side of the fourth switch tube, which can limit the current passing through the fourth switch tube, prevent the fourth switch tube from being broken down by excessive current and voltage when it is turned on, and ensure the normal use of the fourth switch tube.

[0033] In some embodiments that may include the above embodiments, the inverter further includes a filter circuit, the filter circuit includes an inverter inductor and an inverter capacitor connected in series, and the filter circuit is connected between the first node and the second node.

[0034] The inverter inductor and the inverter capacitor can form an LC filter circuit to reduce the noise of the output voltage of the HERIC inverter circuit and improve the output quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a structural schematic diagram of a photovoltaic power generation system;

[0036] Figure 2 is a circuit diagram of a voltage absorption circuit in the related art;

[0037] Figure 3 Circuit of the voltage absorption circuit provided in the embodiment of the present application Figure 1 ;

[0038] Figure 4 Circuit of the voltage absorption circuit provided in the embodiment of the present application Figure 2 ;

[0039] Figure 5 Circuit of the voltage absorption circuit provided in the embodiment of the present application Figure 3 ;

[0040] Figure 6 Circuit of the voltage absorption circuit provided in the embodiment of the present application Figure 4 ;

[0041] Figure 7 Circuit of the voltage absorption circuit provided in the embodiment of the present application Figure 5 ;

[0042] Figure 8 Circuit of the voltage absorption circuit provided in the embodiment of the present application Figure 6 ;

[0043] Fig. 9 Circuit of the voltage absorption circuit provided in the embodiment of the present application Figure 7 ;

[0044] Fig.10 Circuit of the voltage absorption circuit provided in the embodiment of the present application Figure 8 ;

[0045] Fig.11 Circuit of the voltage absorption circuit provided in the embodiment of the present application Figure 9 .

[0046] Explanation of reference numerals: 10: photovoltaic power generation system; 11: photovoltaic module; 12: load; 20: inverter; 21: first bridge arm; 22: second bridge arm; 23: third bridge arm; 24: voltage absorption circuit; 241: first sub-circuit; 242: second sub-circuit; 243: third sub-circuit; 244: fourth sub-circuit; 25: filter circuit; 31: first switch tube; 32: second switch tube; 33: third switch tube; 34: fourth switch tube; 35: fifth switch tube : off tube; 36: the sixth switch tube; 41: the first node; 42: the second node; 51: the first diode; 52: the second diode; 53: the third diode; 54: the fourth diode; 55: the fifth diode; 56: the sixth diode; 71: the first resistor; 72: the second resistor; 73: the third resistor; 74: the fourth resistor; 75: the fifth resistor; 76: the sixth resistor; 77: the seventh resistor; 78: the eighth resistor; 81: the inverter inductor; 82: the inverter capacitor. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0049] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to changes in the orientation of the components placed in the drawings.

[0050] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0051] Please refer to Figure 1The photovoltaic power generation system 10 generally includes an inverter 20, which can convert direct current into alternating current. The inverter 20 can be connected to the photovoltaic module 11 to receive direct current from the photovoltaic module 11, and the inverter 20 can also be connected to the load 12 to transmit the converted alternating current to the load 12 to supply power to the load 12.

[0052] Please refer to Figure 2 The inverter 20 includes a Highly Efficient and Reliable Inverter Concept (HERIC) inverter circuit, the HERIC inverter circuit includes a first bridge arm 21, a second bridge arm 22 and a third bridge arm 23, the first bridge arm 21 is connected between the positive DC bus (BUS+) and the negative DC bus (BUS-), the first bridge arm 21 includes a first switch tube 31 and a second switch tube 32 connected in series, the second bridge arm 22 is connected between the positive DC bus (BUS+) and the negative DC bus (BUS-), and the second bridge arm 22 includes a third switch tube 33 and a fourth switch tube 34 connected in series.

[0053] The third bridge arm 23 is connected between a first node 41 and a second node 42. The first node 41 is a connection point between the first switch tube 31 and the second switch tube 32. The second node 42 is a connection point between the third switch tube 33 and the fourth switch tube 34. The third bridge arm 23 includes a fifth switch tube 35 and a sixth switch tube 36 connected in series.

[0054] The embodiments of the present application do not limit the switch tube. For example, the switch tube can be a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as MOSFET), and can also be an insulated-gate bipolar transistor (Insulated-Gate Bipolar Transistor, referred to as IGBT).

[0055] The fifth switch tube 35 and the sixth switch tube 36 in the HERIC inverter circuit are in an alternate conduction state during operation, and both the fifth switch tube 35 and the sixth switch tube 36 are switched on and off at high speed. Since the HERIC inverter circuit is arranged on a circuit board, the wire will generate parasitic inductance. During the high-speed switching process, the current changes rapidly, which will generate a large overvoltage at both ends of the fifth switch tube 35 and the sixth switch tube 36. If the generated overvoltage is not absorbed, the overvoltage will directly act on the fifth switch tube 35 and the sixth switch tube 36, causing damage to the fifth switch tube 35 and the sixth switch tube 36, thereby affecting the normal operation of the fifth switch tube 35 and the sixth switch tube 36.

[0056] Therefore, a voltage absorption circuit 24 is usually required to be provided in the inverter 20 to absorb the overvoltage on the fifth switch tube 35 or the sixth switch tube 36 .

[0057] Continue to refer to Figure 2 In the related art, the voltage absorption circuit 24 is connected in parallel with the fifth switch tube 35 and the sixth switch tube 36, and the voltage absorption circuit 24 includes a resistor and a capacitor, which are connected in series. The capacitor can absorb the electric energy on the fifth switch tube 35 and the sixth switch tube 36, and release the absorbed electric energy to the resistor, which is consumed by the resistor. However, since the voltage at both ends of the fifth switch tube 35 and the sixth switch tube 36 changes rapidly during the opening process of the first bridge arm 21 and the second bridge arm 22, the capacitor will generate an instantaneous current, which will increase the current on the third bridge arm 23, thereby increasing the opening current of the HERIC inverter circuit, resulting in an increase in the opening loss of the HERIC inverter circuit.

[0058] Please refer to Figure 3 The inverter 20 provided in the embodiment of the present application includes a voltage absorption circuit 24, which is connected to the input end of the fifth switch tube 35 and the input end of the sixth switch tube 36, and is used to be connected to the positive DC bus (BUS+) and the negative DC bus (BUS-); the voltage absorption circuit 24 is used to absorb the electric energy of the input end of the fifth switch tube 35 or the input end of the sixth switch tube 36 during the process of opening the first bridge arm 21 or the second bridge arm 22, and release the absorbed electric energy to the negative DC bus (BUS-).

[0059] The voltage absorption circuit 24 provided in the embodiment of the present application is connected to the positive DC bus (BUS+) and the negative DC bus (BUS-), and the operating voltage of the voltage absorption circuit 24 can be limited to the bus voltage. When the voltage on the third bridge arm 23 is less than the bus voltage, the voltage absorption circuit 24 does not work, and does not affect the turn-on current of the first bridge arm 21 and the second bridge arm 22; when the voltage on the third bridge arm 23 is greater than the bus voltage, the voltage absorption circuit 24 works, and can absorb the electric energy exceeding the bus voltage (i.e., the overvoltage part) and release it to the bus.

[0060] Compared with the related art, the voltage absorption circuit 24 provided in the embodiment of the present application can reduce the turn-on current on the first bridge arm 21 and the second bridge arm 22, thereby reducing the turn-on loss. At the same time, in the embodiment of the present application, the electric energy of the overvoltage part is released back to the bus, which can avoid energy loss and improve energy utilization.

[0061] In the above embodiment, the voltage absorption circuit 24 includes a first subcircuit 241 and a second subcircuit 242. The first subcircuit 241 is connected to the input end of the fifth switch tube 35 and is used to connect to the positive DC bus (BUS+) and the negative DC bus (BUS-); the first subcircuit 241 is used to absorb the electric energy at the input end of the fifth switch tube 35 and release the absorbed electric energy to the negative DC bus (BUS-).

[0062] The second sub-circuit 242 is connected to the input end of the sixth switch tube 36 and is used to connect to the positive DC bus (BUS+) and the negative DC bus (BUS-); the second sub-circuit 242 is used to absorb the electric energy at the input end of the sixth switch tube 36 and release the absorbed electric energy to the negative DC bus (BUS-).

[0063] It can be understood that the first sub-circuit 241 is used to connect to the positive DC bus (BUS+) and the negative DC bus (BUS-), and the operating voltage of the first sub-circuit 241 can be limited to the bus voltage. The second sub-circuit 242 is used to connect to the positive DC bus (BUS+) and the negative DC bus (BUS-), and the operating voltage of the second sub-circuit 242 can be limited to the bus voltage.

[0064] When the first switch tube 31 and the fourth switch tube 34 are turned on, the fifth switch tube 35 works. The first sub-circuit 241 is connected to the input end of the fifth switch tube 35. When the voltage at the input end of the fifth switch tube 35 is greater than the bus voltage, there is an overvoltage on the fifth switch tube 35. At this time, the first sub-circuit 241 is turned on, and the first sub-circuit 241 absorbs the electric energy of the overvoltage part and releases it back to the bus.

[0065] When the second switch tube 32 and the third switch tube 33 are turned on, the sixth switch tube 36 works. The second sub-circuit 242 is connected to the input end of the sixth switch tube 36. When the voltage at the input end of the sixth switch tube 36 is greater than the bus voltage, there is an overvoltage on the sixth switch tube 36. At this time, the second sub-circuit 242 is turned on, and the second sub-circuit 242 absorbs the electrical energy of the overvoltage part and releases it back to the bus.

[0066] The first subcircuit 241 is connected to the input end of the fifth switch tube 35. The first subcircuit 241 can absorb the overvoltage on the fifth switch tube 35 and release it back to the busbar to avoid damage to the fifth switch tube 35 and ensure the normal operation of the fifth switch tube 35. The second subcircuit 242 is connected to the input end of the sixth switch tube 36. The second subcircuit 242 can absorb the overvoltage on the sixth switch tube 36 and release it back to the busbar to avoid damage to the sixth switch tube 36 and ensure the normal operation of the sixth switch tube 36.

[0067] Continue to refer to Figure 3In the above embodiment, the input end of the fifth switch tube 35 is connected to the first node 41, the input end of the sixth switch tube 36 is connected to the second node 42, and the output end of the fifth switch tube 35 is connected to the output end of the sixth switch tube 36.

[0068] That is, when the first switch tube 31 and the fourth switch tube 34 are turned on, the fifth switch tube 35 is in operation. When the second switch tube 32 and the third switch tube 33 are turned on, the sixth switch tube 36 is in operation.

[0069] The first subcircuit 241 includes a first diode 51 and a first capacitor 61, wherein an anode of the first diode 51 is connected to the input end of the fifth switch tube 35, a cathode of the first diode 51 is connected to a first end of the first capacitor 61, the first end of the first capacitor 61 is also connected to a positive DC bus (BUS+), and a second end of the first capacitor 61 is connected to a negative DC bus (BUS-);

[0070] Both ends of the first capacitor 61 are connected to the positive and negative DC bus (BUS-), so that the voltage across the first capacitor 61 is clamped to the bus voltage. When there is no overvoltage on the fifth switch tube 35, the voltage value at the input end of the fifth switch tube 35 is equal to the bus voltage, and the anode side voltage and the cathode side voltage of the first diode 51 are equal. At this time, the first diode 51 is not turned on, and the HERIC inverter circuit works normally.

[0071] When there is an overvoltage on the fifth switch tube 35, the voltage value at the input end of the fifth switch tube 35 is greater than the bus voltage, and the anode side voltage of the first diode 51 is greater than the cathode side voltage. At this time, the first diode 51 is turned on, and the electric energy of the overvoltage portion flows into the first capacitor 61 through the first diode 51 and is absorbed by the first capacitor 61. Both ends of the first capacitor 61 are also connected to the positive and negative DC bus (BUS-), so that the electric energy absorbed by the first capacitor 61 can be released to the bus, so that the electric energy of the overvoltage portion can be recovered.

[0072] The second sub-circuit 242 includes a second diode 52 and a second capacitor 62, the anode of the second diode 52 is connected to the input end of the sixth switch tube 36, the cathode of the second diode 52 is connected to the first end of the second capacitor 62, the first end of the second capacitor 62 is also connected to the positive DC bus (BUS+), and the second end of the second capacitor 62 is connected to the negative DC bus (BUS-).

[0073] It can be understood that the two ends of the second capacitor 62 are connected to the positive and negative DC bus (BUS-), so that the voltage across the second capacitor 62 is clamped to the bus voltage. When there is no overvoltage on the sixth switch tube 36, the voltage value at the input end of the sixth switch tube 36 is equal to the bus voltage, and the anode side voltage and the cathode side voltage of the second diode 52 are equal. At this time, the second diode 52 is not turned on, and the HERIC inverter circuit works normally.

[0074] When there is an overvoltage on the sixth switch tube 36, the voltage value at the input end of the sixth switch tube 36 is greater than the bus voltage, and the anode side voltage of the second diode 52 is greater than the cathode side voltage. At this time, the second diode 52 is turned on, and the electric energy of the overvoltage portion flows into the second capacitor 62 through the second diode 52 and is absorbed by the second capacitor 62. Both ends of the second capacitor 62 are also connected to the positive and negative DC bus (BUS-), so that the electric energy absorbed by the second capacitor 62 can be released to the bus, so that the electric energy of the overvoltage portion can be recovered.

[0075] The first diode 51 can ensure that when there is an overvoltage on the fifth switch tube 35, the first capacitor 61 absorbs the overvoltage on the fifth switch tube 35. The second diode 52 can ensure that when there is an overvoltage on the sixth switch tube 36, the second capacitor 62 absorbs the overvoltage on the sixth switch tube 36, thereby reducing the voltage stress at both ends of the fifth switch tube 35 and the sixth switch tube 36, and ensuring the normal operation of the third bridge arm 23.

[0076] In addition, the first capacitor 61 and the second capacitor 62 can release the electrical energy of the overvoltage portion to the bus, so that the electrical energy of the overvoltage portion is recovered, thereby reducing the energy loss of the inverter 20 .

[0077] Please refer to Figure 4 In the above embodiment, the voltage absorption circuit 24 also includes a third diode 53, the anode of the third diode 53 is connected to the second end of the first capacitor 61 and the second end of the second capacitor 62, and the cathode of the third diode 53 is connected to the output end of the fifth switch tube 35 and the output end of the sixth switch tube 36.

[0078] It is understandable that the second end of the first capacitor 61 is connected to the negative DC bus (BUS-). Since the fourth switch tube 34 is connected to the negative DC bus (BUS-) in the HERIC inverter circuit, when the first capacitor 61 is connected to the negative DC bus (BUS-) on the circuit board, it is necessary to bypass the HERIC inverter circuit routing, that is, the wire connecting the first capacitor 61 to the negative DC bus (BUS-) is longer, and the parasitic inductance generated by the wire becomes larger, thereby affecting the effect of the voltage absorption circuit 24.

[0079] The second end of the first capacitor 61 is connected to the output end of the fifth switch tube 35 through the third diode 53, which can ensure that the first capacitor 61 is directly connected in parallel to the two ends of the fifth switch tube 35, shortening the absorption loop, so that the first capacitor 61 absorbs the overvoltage at the two ends of the fifth switch tube 35, and ensures the effect of the voltage absorption circuit 24.

[0080] At the same time, since the voltage value of the output end of the fifth switch tube 35 is not equal to the voltage value of the negative DC bus (BUS-), the output end of the fifth switch tube 35 cannot be directly connected to the second end of the first capacitor 61 (i.e., the negative DC bus (BUS-)). The anode of the third diode 53 is connected to the second end of the first capacitor 61 (i.e., the negative DC bus (BUS-)), and the cathode of the third diode 53 is connected to the input end of the fifth switch tube 35, which can avoid the output end of the fifth switch tube 35 from being connected to the negative DC bus (BUS-), avoid the wire short circuit between the two, and ensure the normal operation of the voltage absorption circuit 24.

[0081] Similarly, the third diode 53 can also ensure that the second capacitor 62 is directly connected in parallel to the two ends of the sixth switch tube 36, shortening the absorption loop, so that the second capacitor 62 absorbs the overvoltage at the two ends of the sixth switch tube 36, ensuring the effect of the voltage absorption circuit 24. At the same time, the third diode 53 can also prevent the output end of the sixth switch tube 36 from being connected to the negative DC bus (BUS-), avoiding a short circuit between the wires therebetween, and ensuring the normal operation of the voltage absorption circuit 24.

[0082] Please refer to Figure 5 In the above embodiment, the voltage absorption circuit 24 also includes a first resistor 71, one end of the first resistor 71 is connected to the second end of the first capacitor 61 and the second end of the second capacitor 62, and the other end of the first resistor 71 is connected to the negative DC bus (BUS-).

[0083] Since the voltage absorption circuit 24 includes the first diode 51 and the second diode 52 , when the first diode 51 and the second diode 52 are turned on, the current increases sharply, and the first diode 51 and the second diode 52 are easily broken down by the excessive current and voltage.

[0084] The first resistor 71 is disposed at the cathode side of the first diode 51 and the second diode 52 to prevent the first diode 51 and the second diode 52 from being broken down by excessive current and voltage when they are turned on, thereby preventing the first diode 51 and the second diode 52 from being damaged.

[0085] Please refer to Figure 6 In some embodiments, the voltage absorption circuit 24 further includes a first resistor 71 and a second resistor 72, wherein the first resistor 71 is connected between the second end of the first capacitor 61 and the negative DC bus (BUS-), and the second resistor 72 is connected between the second end of the second capacitor 62 and the negative DC bus (BUS-).

[0086] Since the second end of the first capacitor 61 and the second end of the second capacitor 62 are both connected to the negative DC bus (BUS-), the first capacitor 61 and the second capacitor 62 can be connected to the same wiring, and then connected to the negative DC bus (BUS-) (as in the above embodiment). The first capacitor 61 and the second capacitor 62 can also be connected to the negative DC bus (BUS-) respectively. At this time, the first sub-circuit 241 includes a first diode 51, a first capacitor 61 and a first resistor 71, and the second sub-circuit 242 includes a second diode 52, a second capacitor 62 and a second resistor 72.

[0087] The first resistor 71 is located at the cathode side of the first diode 51, and can limit the current passing through the first diode 51 to ensure the normal use of the first diode 51. The second resistor 72 is located at the cathode side of the second diode 52, and can limit the current passing through the second diode 52 to ensure the normal use of the second diode 52.

[0088] In addition, the first resistor 71 is arranged between the first capacitor 61 and the negative DC bus (BUS-), which can limit the charging current and discharging current of the first capacitor 61 to prevent the first capacitor 61 from overheating and burning. The first resistor 71 is also arranged between the second capacitor 62 and the negative DC bus (BUS-), which can limit the charging current and discharging current of the second capacitor 62 to prevent the second capacitor 62 from overheating and burning.

[0089] Please refer to Figure 7 In some embodiments, the voltage absorption circuit 24 further includes a third resistor 73 and a fourth resistor 74, the third resistor 73 is connected between the first end of the first capacitor 61 and the positive DC bus (BUS+), and the fourth resistor 74 is connected between the first end of the second capacitor 62 and the positive DC bus (BUS+).

[0090] The third resistor 73 and the fourth resistor 74 are also located on the voltage absorption circuit 24, and the third resistor 73 is located on the cathode side of the first diode 51, and the fourth resistor 74 is located on the cathode side of the second diode 52. The third resistor 73 has the same function as the first resistor 71, which can prevent the first diode 51 from being broken down by excessive current and voltage when it is turned on, thereby ensuring the normal use of the first diode 51. The fourth resistor 74 has the same function as the second resistor 72, which can prevent the second diode 52 from being broken down by excessive current and voltage when it is turned on, thereby ensuring the normal use of the second diode 52.

[0091] In some embodiments, the voltage absorption circuit 24 includes a first resistor 71 , a third resistor 73 , and a fourth resistor 74 .

[0092] The first resistor 71 and the third resistor 73 can protect the first diode 51 to prevent the first diode 51 from being broken down. The first resistor 71 and the fourth resistor 74 can protect the second diode 52 to prevent the second diode 52 from being broken down.

[0093] In some embodiments, the voltage absorption circuit 24 includes a first resistor 71 , a second resistor 72 , a third resistor 73 , and a fourth resistor 74 .

[0094] The first resistor 71 and the third resistor 73 can protect the first diode 51 from being broken down. The second resistor 72 and the fourth resistor 74 can protect the second diode 52 from being broken down.

[0095] Please refer to Figure 8 In some embodiments, the voltage absorption circuit 24 includes a third sub-circuit 243 and a fourth sub-circuit 244, the input end of the fifth switch tube 35 is connected to the input end of the sixth switch tube 36, the output end of the fifth switch tube 35 is connected to the first node 41, and the output end of the sixth switch tube 36 is connected to the second node 42;

[0096] The third sub-circuit 243 includes a fourth diode 54 and a third capacitor 63, wherein the anode of the fourth diode 54 is connected to the input end of the fifth switch tube 35, the cathode of the fourth diode 54 is connected to the first end of the third capacitor 63, the first end of the third capacitor 63 is also connected to the positive DC bus (BUS+), and the second end of the third capacitor 63 is connected to the negative DC bus (BUS-);

[0097] The fourth subcircuit 244 includes a fourth diode 54 and a fourth capacitor 64, the anode of the fourth diode 54 is connected to the input end of the sixth switch tube 36, the cathode of the fourth switch tube 34 is connected to the first end of the fourth capacitor 64, the first end of the fourth capacitor 64 is also connected to the positive DC bus (BUS+), and the second end of the fourth capacitor 64 is connected to the negative DC bus (BUS-).

[0098] It can be understood that the input end of the fifth switch tube 35 is connected to the input end of the sixth switch tube 36, the output end of the fifth switch tube 35 is connected to the first node 41, and the output end of the sixth switch tube 36 is connected to the second node 42. When the first switch tube 31 and the fourth switch tube 34 are turned on, the sixth switch tube 36 works. When the second switch tube 32 and the third switch tube 33 are turned on, the fifth switch tube 35 works.

[0099] When the first switch tube 31 and the fourth switch tube 34 are turned on, since the two ends of the fourth capacitor 64 are respectively connected to the positive DC bus (BUS+) and the negative DC bus (BUS-), the voltage of the fourth capacitor 64 is clamped to the bus voltage. The anode of the fourth diode 54 is connected to the input end of the sixth switch tube 36, and the cathode of the fourth diode 54 is connected to the first end of the fourth capacitor 64. That is, when the anode side voltage of the fourth diode 54 is greater than the bus voltage, that is, when there is an overvoltage on the sixth switch tube 36, the fourth diode 54 is turned on, and the second sub-circuit 242 works at this time. When the fourth diode 54 is turned on, the electric energy of the overvoltage part is absorbed by the fourth capacitor 64 and released back to the bus.

[0100] When the second switch tube 32 and the third switch tube 33 are turned on, since the two ends of the third capacitor 63 are respectively connected to the positive DC bus (BUS+) and the negative DC bus (BUS-), the voltage of the third capacitor 63 is clamped to the bus voltage. The anode of the fourth diode 54 is connected to the input end of the fifth switch tube 35, and the cathode of the fourth diode 54 is connected to the first end of the third capacitor 63. That is, when the anode side voltage of the fourth diode 54 is greater than the bus voltage, that is, when there is an overvoltage on the fifth switch tube 35, the fourth diode 54 is turned on, and at this time, the first sub-circuit 241 works. When the fourth diode 54 is turned on, the electrical energy of the overvoltage part is absorbed by the third capacitor 63 and released back to the bus.

[0101] The fourth diode 54 can ensure that when there is an overvoltage on the fifth switch tube 35, the third capacitor 63 absorbs the overvoltage on the fifth switch tube 35. The fourth diode 54 can also ensure that when there is an overvoltage on the sixth switch tube 36, the fourth capacitor 64 absorbs the overvoltage on the sixth switch tube 36. The third capacitor 63 and the fourth capacitor 64 can release the electric energy of the overvoltage part to the bus, so that the electric energy of the overvoltage part is recovered, thereby reducing the energy loss of the inverter 20.

[0102] Please refer to Fig. 9 In the above embodiment, the voltage absorption circuit 24 also includes a fifth diode 55 and a sixth diode 56, the anode of the fifth diode 55 is connected to the second end of the third capacitor 63, and the cathode of the fifth diode 55 is connected to the first node 41; the anode of the sixth diode 56 is connected to the second end of the fourth capacitor 64, and the cathode of the sixth diode 56 is connected to the second node 42.

[0103] It is understandable that, on the circuit board, when the third capacitor 63 is connected to the negative DC bus (BUS-), it is necessary to bypass the HERIC inverter circuit routing, that is, the wire connecting the third capacitor 63 to the negative DC bus (BUS-) is longer, and the parasitic inductance generated by the wire becomes larger, thereby affecting the effect of the voltage absorption circuit 24. The fifth diode 55 can ensure that the third capacitor 63 is directly connected in parallel to the two ends of the fifth switch tube 35, absorb the overvoltage at the two ends of the fifth switch tube 35, and ensure the effect of the voltage absorption circuit 24.

[0104] In addition, since the voltage value of the output end of the fifth switch tube 35 is not equal to the voltage value of the negative DC bus (BUS-), the output end of the fifth switch tube 35 cannot be directly connected to the second end of the first capacitor 61 (i.e., the negative DC bus (BUS-)). The anode of the fifth diode 55 is connected to the second end of the third capacitor 63 (i.e., the negative DC bus (BUS-)), and the cathode of the fifth diode 55 is connected to the input end of the fifth switch tube 35, which can avoid the output end of the fifth switch tube 35 from being connected to the negative DC bus (BUS-), avoid the wire short circuit between the two, and ensure the normal operation of the voltage absorption circuit 24.

[0105] Similarly, the sixth diode 56 can ensure that the fourth capacitor 64 is directly connected in parallel to both ends of the sixth switch tube 36, absorb the overvoltage at both ends of the sixth switch tube 36, and ensure the effect of the voltage absorption circuit 24. The sixth diode 56 can also prevent the output end of the sixth switch tube 36 from being connected to the negative DC bus (BUS-), avoid a short circuit between the wires therebetween, and ensure the normal operation of the voltage absorption circuit 24.

[0106] Continue to refer to Fig. 9 In the above embodiment, the voltage absorption circuit 24 also includes a fifth resistor 75 and a sixth resistor 76, the fifth resistor 75 is connected between the second end of the third capacitor 63 and the negative DC bus (BUS-), and the sixth resistor 76 is connected between the second end of the fourth capacitor 64 and the negative DC bus (BUS-).

[0107] The fifth resistor 75 and the sixth switch tube 36 are located on the cathode side of the fourth switch tube 34 , which can limit the current passing through the fourth switch tube 34 , prevent the fourth switch tube 34 from being broken down by excessive current and voltage when it is turned on, and ensure the normal use of the fourth switch tube 34 .

[0108] Please refer to Fig.10 In some embodiments, the voltage absorption circuit 24 further includes a seventh resistor 77, one end of the seventh resistor 77 is connected to the first end of the third capacitor 63 and the first end of the fourth capacitor 64, and the other end of the seventh resistor 77 is connected to the positive DC bus (BUS+).

[0109] Similar to the fifth resistor 75 , the seventh resistor 77 is also located on the cathode side of the fourth switch tube 34 , which can limit the current passing through the fourth switch tube 34 , prevent the fourth switch tube 34 from being broken down by excessive current and voltage when turned on, and ensure the normal use of the fourth switch tube 34 .

[0110] Please refer to Fig.11 In some embodiments, the voltage absorption circuit 24 also includes a seventh resistor 77 and an eighth resistor 78, the seventh resistor 77 is connected between the first end of the third capacitor 63 and the positive DC bus (BUS+), and the eighth resistor 78 is connected between the first end of the fourth capacitor 64 and the positive DC bus (BUS+).

[0111] The seventh resistor 77 and the eighth resistor 78 are located on the cathode side of the fourth switch tube 34 , which can limit the current passing through the fourth switch tube 34 , prevent the fourth switch tube 34 from being broken down by excessive current and voltage when it is turned on, and ensure the normal use of the fourth switch tube 34 .

[0112] In some embodiments, the voltage absorption circuit 24 includes a fifth resistor 75, a sixth resistor 76, and a seventh resistor 77. The fifth resistor 75, the sixth resistor 76, and the seventh resistor 77 can protect the fourth switch tube 34 and prevent the fourth switch tube 34 from being broken down.

[0113] In some embodiments, the voltage absorption circuit 24 includes a fifth resistor 75, a sixth resistor 76, a seventh resistor 77 and an eighth resistor 78. The fifth resistor 75, the sixth resistor 76, the seventh resistor 77 and the eighth resistor 78 can protect the fourth switch tube 34 from being broken down.

[0114] In the above embodiment, the inverter 20 further includes a filter circuit 25 . The filter circuit 25 includes an inverter inductor 81 and an inverter capacitor 82 connected in series. The filter circuit 25 is connected between the first node 41 and the second node 42 .

[0115] It is understandable that when the HERIC inverter circuit is working, the switch tube is constantly turned on and off, which is easy to generate high-frequency noise. The inverter inductor 81 and the inverter capacitor 82 can form an LC filter circuit 25 to reduce the noise of the output voltage of the HERIC inverter circuit and improve the output quality.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An inverter, characterized in that: include: A first bridge arm is used to connect between a positive DC bus and a negative DC bus, and the first bridge arm includes a first switch tube and a second switch tube connected in series; A second bridge arm, used to be connected between the positive DC bus and the negative DC bus, the second bridge arm comprising a third switch tube and a fourth switch tube connected in series; A third bridge arm is connected between a first node and a second node, wherein the first node is a connection point between the first switch tube and the second switch tube, and the second node is a connection point between the third switch tube and the fourth switch tube; the third bridge arm includes a fifth switch tube and a sixth switch tube connected in series; A voltage absorption circuit is connected to the input end of the fifth switch tube and the input end of the sixth switch tube, and is used to be connected to the positive DC bus and the negative DC bus; the voltage absorption circuit is used to absorb the electric energy of the input end of the fifth switch tube or the input end of the sixth switch tube during the process of opening the first bridge arm or the second bridge arm, and release the absorbed electric energy to the negative DC bus.

2. The inverter according to claim 1, characterized in that: The voltage absorption circuit includes a first subcircuit and a second subcircuit; The input end of the fifth switch tube is connected to the first node, the input end of the sixth switch tube is connected to the second node, and the output end of the fifth switch tube is connected to the output end of the sixth switch tube; The first subcircuit includes a first diode and a first capacitor, wherein an anode of the first diode is connected to the input end of the fifth switch tube, a cathode of the first diode is connected to a first end of the first capacitor, the first end of the first capacitor is also connected to the positive DC bus, and a second end of the first capacitor is connected to the negative DC bus; The second sub-circuit includes a second diode and a second capacitor, the anode of the second diode is connected to the input end of the sixth switch tube, the cathode of the second diode is connected to the first end of the second capacitor, the first end of the second capacitor is also connected to the positive DC bus, and the second end of the second capacitor is connected to the negative DC bus.

3. The inverter according to claim 2, characterized in that: The voltage absorption circuit also includes a third diode; An anode of the third diode is connected to the second end of the first capacitor and the second end of the second capacitor, and a cathode of the third diode is connected to the output end of the fifth switch tube and the output end of the sixth switch tube.

4. The inverter according to claim 2 or 3, characterized in that: The voltage absorption circuit also includes a first resistor; One end of the first resistor is connected to the second end of the first capacitor and the second end of the second capacitor, and the other end of the first resistor is connected to the negative DC bus.

5. The inverter according to claim 2 or 3, characterized in that: The voltage absorption circuit also includes a first resistor and a second resistor; The first resistor is connected between the second end of the first capacitor and the negative DC bus, and the second resistor is connected between the second end of the second capacitor and the negative DC bus.

6. The inverter according to any one of claims 2 to 5, characterized in that: The voltage absorption circuit also includes a third resistor and a fourth resistor; The third resistor is connected between the first end of the first capacitor and the positive DC bus, and the fourth resistor is connected between the first end of the second capacitor and the positive DC bus.

7. The inverter according to claim 1, characterized in that: The voltage absorption circuit includes a third subcircuit and a fourth subcircuit; The input end of the fifth switch tube is connected to the input end of the sixth switch tube, the output end of the fifth switch tube is connected to the first node, and the output end of the sixth switch tube is connected to the second node; The third subcircuit includes a fourth diode and a third capacitor, wherein an anode of the fourth diode is connected to the input end of the fifth switch, a cathode of the fourth diode is connected to a first end of the third capacitor, the first end of the third capacitor is also connected to the positive DC bus, and a second end of the third capacitor is connected to the negative DC bus; The fourth subcircuit includes the fourth diode and the fourth capacitor, the anode of the fourth diode is connected to the input end of the sixth switch tube, the cathode of the fourth switch tube is connected to the first end of the fourth capacitor, the first end of the fourth capacitor is also connected to the positive DC bus, and the second end of the fourth capacitor is connected to the negative DC bus.

8. The inverter according to claim 7, characterized in that: The voltage absorption circuit also includes a fifth diode and a sixth diode; An anode of the fifth diode is connected to the second end of the third capacitor, and a cathode of the fifth diode is connected to the first node; An anode of the sixth diode is connected to the second end of the fourth capacitor, and a cathode of the sixth diode is connected to the second node.

9. The inverter according to claim 7 or 8, characterized in that: The voltage absorption circuit also includes a fifth resistor and a sixth resistor; The fifth resistor is connected between the second end of the third capacitor and the negative DC bus, and the sixth resistor is connected between the second end of the fourth capacitor and the negative DC bus.

10. The inverter according to any one of claims 7 to 9, characterized in that: The voltage absorption circuit also includes a seventh resistor; One end of the seventh resistor is connected to the first end of the third capacitor and the first end of the fourth capacitor, and the other end of the seventh resistor is connected to the positive DC bus.

11. The inverter according to any one of claims 7 to 9, characterized in that: The voltage absorption circuit also includes a seventh resistor and an eighth resistor; The seventh resistor is connected between the first end of the third capacitor and the positive DC bus, and the eighth resistor is connected between the first end of the fourth capacitor and the positive DC bus.

12. The inverter according to any one of claims 1 to 11, characterized in that: The inverter further includes a filter circuit, which includes an inverter inductor and an inverter capacitor connected in series, and is connected between the first node and the second node.

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