Calibration circuit and calibration method for offset voltage of differential amplifier

Abstract

The invention relates to the technical field of integrated circuits and provides a calibration circuit and a calibration method for offset voltage of a differential amplifier. The calibration circuit comprises a common-gate first field-effect transistor pair, a second field-effect transistor pair and a third field-effect transistor pair, the current source pairs are respectively connected with the respective load poles of the first field-effect transistor pairs, and superposition results between the current output by the respective load poles of the first field-effect transistor pairs and the current output by the respective load poles of the second field-effect transistor pairs forming the differential amplifier are respectively controlled by the current source pairs; at least one of the current source pairs can be adjusted to enable the calibration circuit to calibrate the output differential voltage signal based on the input differential voltage signal of the differential amplifier. In this way, offset voltage is offset, a high-precision offset voltage calibration function is provided, uniform calibration is achieved, and the requirements for high bandwidth and high speed are met.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a calibration circuit and a calibration method for an offset voltage of a differential amplifier. Background Art

[0002] The principle of the differential amplifier is to amplify the differential signal of the input port to the output port. Affected by factors such as differences in transistor characteristics, an offset voltage may exist at the output port, which is further amplified in the subsequent circuit, resulting in a higher degree of offset deterioration, which is not conducive to the stability of the overall circuit. In the prior art, there are two ways to eliminate the offset voltage. One way is to change the overall characteristics of the entire branch by adjusting the number of transistors connected in parallel to the input stage, but the adjustment accuracy is affected by the number of transistors, so the adjustment accuracy is unevenly distributed, which is not conducive to improving the simulation accuracy and simplifying the complexity of chip design. Another way is to generate a correction voltage with the same magnitude and opposite polarity as the offset voltage through an additional circuit, and directly apply the correction voltage to the output port to eliminate the influence of the offset voltage. The difference in transistor characteristics of the differential pair of the differential amplifier is a factor that may cause the offset voltage to be generated, and the differential pair of the additional circuit used to generate the correction voltage may also have differences in transistor characteristics, which affects the elimination effect of the correction voltage on the offset voltage, and it may not be possible to completely eliminate the offset voltage, thereby causing the offset deterioration in the subsequent circuit.

[0003] To this end, the present application provides a calibration circuit and a calibration method for the offset voltage of a differential amplifier, which are used to address the technical difficulties in the prior art. Summary of the invention

[0004] In a first aspect, the present application provides a calibration circuit for the offset voltage of a differential amplifier. The calibration circuit comprises: a first field effect transistor pair with a common gate, wherein the bias electrodes of the first field effect transistor pair are used as output differential voltage signals; a current source pair, wherein the current source pair is respectively connected to the load electrodes of the first field effect transistor pair, and the superposition result between the current output by the load electrodes of the first field effect transistor pair and the current output by the load electrodes of the second field effect transistor pair used to constitute the differential amplifier is respectively controlled by the current source pair, and at least one current source in the current source pair can be adjusted so that the calibration circuit can calibrate the output differential voltage signal based on the input differential voltage signal of the differential amplifier.

[0005] Through the first aspect of the present application, the offset voltage is offset by utilizing the current regulation mechanism and the input-output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, providing a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, achieving uniform calibration, and being conducive to meeting high-bandwidth and high-speed requirements.

[0006] In a possible implementation of the first aspect of the present application, when the second field effect transistor pair of the differential amplifier outputs an offset voltage, the calibration circuit calibrates the output differential voltage signal by adjusting at least one current source in the current source pair to offset the offset voltage.

[0007] In a possible implementation manner of the first aspect of the present application, when the input differential voltage signal of the differential amplifier is zero, the calibration circuit is used to make the output differential voltage signal zero.

[0008] In a possible implementation manner of the first aspect of the present application, the current source pair includes a fixed current source and an adjustable current source.

[0009] In a possible implementation manner of the first aspect of the present application, the current source pair includes two adjustable current sources.

[0010] In a possible implementation manner of the first aspect of the present application, the two adjustable current sources included in the current source pair each have the same current regulation accuracy.

[0011] In a possible implementation manner of the first aspect of the present application, the first field effect transistor pair and the two adjustable current sources included in the current source pair together form a current mirror with equal proportions and equal calibration steps.

[0012] In a possible implementation of the first aspect of the present application, when the transistor characteristics of the first field effect transistor pair are inconsistent, or when the transistor characteristics of the second field effect transistor pair are inconsistent, the calibration circuit calibrates the output differential voltage signal by adjusting at least one current source in the current source pair to offset the difference in transistor characteristics.

[0013] In a possible implementation of the first aspect of the present application, when the input common-mode voltage of the input differential voltage signal of the differential amplifier is a low voltage, the first field-effect transistor pair is an N-type metal oxide semiconductor, and the second field-effect transistor pair is a P-type metal oxide semiconductor, and, when the input common-mode voltage of the input differential voltage signal of the differential amplifier is a high voltage, the first field-effect transistor pair is a P-type metal oxide semiconductor, and the second field-effect transistor pair is an N-type metal oxide semiconductor.

[0014] In a possible implementation of the first aspect of the present application, the transistor type of the first field effect transistor pair is different from the transistor type of the second field effect transistor pair, and the first field effect transistor pair and the second field effect transistor pair together constitute an input and output common mode design.

[0015] In a second aspect, the present application provides a method for calibrating the offset voltage of a differential amplifier. The calibration method includes: providing a first field effect transistor pair with a common gate, wherein the bias pole of each of the first field effect transistor pair is used as an output differential voltage signal; providing a current source pair, wherein the current source pair is respectively connected to the load poles of each of the first field effect transistor pair, and the superposition result between the current output by the load poles of each of the first field effect transistor pair and the current output by the load poles of each of the second field effect transistor pair used to constitute the differential amplifier is respectively controlled by the current source pair, and at least one current source in the current source pair can be adjusted so that the output differential voltage signal can be calibrated based on the input differential voltage signal of the differential amplifier.

[0016] Through the second aspect of the present application, the offset voltage is offset by utilizing the current regulation mechanism and the input-output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, thereby providing a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, achieving uniform calibration, and being conducive to meeting high-bandwidth and high-speed requirements.

[0017] In a possible implementation of the second aspect of the present application, the calibration method further includes: when the second field effect transistor pair of the differential amplifier outputs an offset voltage, calibrating the output differential voltage signal by adjusting at least one current source in the current source pair to offset the offset voltage.

[0018] In a possible implementation manner of the second aspect of the present application, the current source pair includes a fixed current source and an adjustable current source.

[0019] In a possible implementation of the second aspect of the present application, the current source pair includes two adjustable current sources, each of which has the same current regulation accuracy, and the first field effect transistor pair and the two adjustable current sources together constitute a current mirror with equal proportions and equal calibration steps.

[0020] In a possible implementation of the second aspect of the present application, the transistor type of the first field effect transistor pair is different from the transistor type of the second field effect transistor pair, and the first field effect transistor pair and the second field effect transistor pair together constitute an input and output common mode design. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of a calibration module for a differential amplifier circuit provided in an embodiment of the present application; Figure 2 A schematic diagram of a calibration circuit for an offset voltage of a differential amplifier provided in an embodiment of the present application; Figure 3 A schematic flow chart of a method for calibrating an offset voltage of a differential amplifier provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0024] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0025] Figure 1 A schematic diagram of a calibration module for a differential amplifier circuit provided in an embodiment of the present application. Figure 1 As shown, the differential amplifier circuit 101 receives an input differential voltage signal 110 , and the differential amplifier circuit 101 is calibrated by a calibration module 103 to provide an output differential voltage signal 120 to a subsequent circuit. Figure 1The calibration module 103 shown is used to calibrate the differential amplifier circuit 101 for the offset voltage, so as to offset the influence of the offset voltage on the output differential voltage signal 120. Here, the differential amplifier circuit 101 is used to amplify the differential signal at the input end, that is, the input differential voltage signal 110, to the output port, that is, to provide the output differential voltage signal 120 to the subsequent circuit. When the differential amplifier circuit 101 is in normal operation, when the input differential voltage signal 110 is zero, that is, the voltages of the two input ends of the differential amplifier circuit 101 are the same, then, according to the design purpose of the differential amplifier circuit 101, the output differential voltage signal 120 should also be zero. The input differential voltage signal 110 being zero does not mean that the voltages of the two input ends must be zero, but only means that the difference between the two is zero, that is, the differential mode part of the voltage signal of the two input ends is zero, but the common mode part of the voltage signal of the two input ends may not be zero. Therefore, when the common mode part of the voltage signal at the two input ends is not zero and the differential mode part is zero, if there is inconsistency in transistor characteristics between the paired field effect transistors used for signal amplification inside the differential amplifier circuit 101, the output differential voltage signal 120 may be non-zero. Here, the inconsistency of transistor characteristics or the difference in transistor characteristics may be caused by various possible factors such as differences in process manufacturing conditions, differences in doping concentrations in transistors, device aging, device damage, etc. Therefore, when the differential amplifier circuit 101 has an offset voltage, this may cause the output differential voltage signal 120 to be non-zero when the input differential voltage signal 110 is zero. At this time, it is necessary to calibrate through the calibration module 103 to offset the influence of the offset voltage and avoid further amplification in the subsequent circuit to cause a higher degree of offset deterioration.

[0026] See also Figure 1The main reason why the differential amplifier circuit 101 generates an offset voltage is the inconsistency between the transistor characteristics of the field effect transistors of the two branches constituting the differential amplifier circuit 101, which leads to the fact that when the input differential voltage signal 110 is zero, the output differential voltage signal 120 is not zero. If the transistors of one branch are fixed, and a certain number of transistors that can be connected in parallel are provided on the other branch, by adjusting the number of transistors that are finally connected in parallel to the other branch, the overall characteristics of the transistors on the other branch are equivalently adjusted, and the number of transistors that make the output differential voltage signal 120 zero can be found. However, the overall adjustment accuracy of this calibration scheme for adjusting the number of transistors connected to the branch is determined by the minimum number of input transistors that can be selected in parallel, such as a minimum of 1, 2, 4 or 8 transistors connected in parallel, so there are multiple gears from small to large. A small gear provides a larger overall adjustment accuracy, and a large gear provides a smaller overall adjustment accuracy. Moreover, the adjustment accuracy is determined by the number of transistors on the branches with a fixed number. For example, if it is fixed at 10 and at least 1 is connected in parallel each time, then the adjustment accuracy is one-tenth, or if it is fixed at 18 and at least 1 is connected in parallel each time, then the adjustment accuracy is one-eighteenth. Therefore, directly changing the calibration method of the number of transistors connected to the input stage inside the differential amplifier circuit 101 will result in an uneven distribution of the adjustment accuracy, which is not conducive to improving the simulation accuracy and simplifying the complexity of chip design. In addition, in application fields such as high-speed digital communications and high-speed interfaces, the differential amplifier circuit 101 is used for amplifying high-speed differential signals. Therefore, connecting an adjustable number of transistors to the input stage will introduce poles and parasitic effects, thereby reducing the overall bandwidth. In order to compensate for the reduced bandwidth, a larger operating current needs to be provided, which in turn increases power consumption. Therefore, Figure 1 The calibration module 103 for the differential amplifier circuit 101 shown does not adopt the method of deploying an adjustable number of transistors on the branches of the differential amplifier circuit 101, which avoids parasitic effects and increased power consumption and is also conducive to meeting high bandwidth and high speed requirements.

[0027] Continue reading Figure 1, the main reason why the differential amplifier circuit 101 generates an offset voltage is the difference between the paired field effect transistors on the input stage of the differential amplifier circuit 101, that is, the difference between the transistor characteristics of the differential pair used for signal amplification inside the differential amplifier circuit 101, such as the inconsistency of transistor parameters. Therefore, the offset voltage is reflected on the output port of the differential amplifier circuit 101. If a correction voltage equal to the offset voltage but opposite in polarity is applied to the output port of the differential amplifier circuit 101, the effect of the offset voltage can be offset, but an additional circuit is required to generate the correction voltage. In addition, because the offset voltage is generated by the differential pair inside the differential amplifier circuit 101, this means that the additional circuit needs to generate the corresponding correction voltage in real time according to the real-time value of the offset voltage through an additional differential pair. However, the differential pair of the additional circuit itself may also have inconsistencies in transistor characteristics such as transistor parameters, which affects the effect of the correction voltage on eliminating the offset voltage, and it may not be possible to completely eliminate the offset voltage, which in turn leads to the deterioration of the offset in the subsequent circuit. For this reason, Figure 1 The calibration module 103 for the differential amplifier circuit 101 shown does not use an additional circuit and an additional differential pair inside it to generate a correction voltage equal to the offset voltage but with an opposite polarity, thus avoiding the introduction of additional parasitic resistors and capacitors and also avoiding the introduction of additional differential pairs. It provides a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, realizes uniform calibration, and is conducive to meeting high-bandwidth and high-speed requirements. This is described in detail below.

[0028] Figure 2 A schematic diagram of a calibration circuit for an offset voltage of a differential amplifier provided in an embodiment of the present application. Figure 2 As shown, the calibration circuit 210 includes: a first common-gate field effect transistor pair (field effect transistor M4 and field effect transistor M5), wherein the bias electrodes of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) are respectively used as output differential voltage signals (output signal A220 and output signal B222); a current source pair (current source I1 and current source I2). The current source pair (current source I1 and current source I2) are respectively connected to the load electrodes of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5). Figure 22 shows an example in which the current source I1 is connected to the load electrode of the field effect transistor M4 in the first field effect transistor pair (field effect transistor M4 and field effect transistor M5). The current source I2 is connected to the load electrode of the field effect transistor M5 in the first field effect transistor pair (field effect transistor M4 and field effect transistor M5). The superposition result between the current output from the load electrode of each of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) and the current output from the load electrode of each of the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) used to form the differential amplifier 212 is respectively controlled by the current source pair (current source I1 and current source I2). Figure 2 , it is exemplarily shown that the superposition result between the current outputted from the load electrode of the field effect transistor M4 in the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) and the current outputted from the load electrode of the field effect transistor M1 in the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) of the differential amplifier 212 is controlled by the current source I1 in the current source pair (current source I1 and current source I2). The superposition result between the current outputted from the load electrode of the field effect transistor M5 in the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) and the current outputted from the load electrode of the field effect transistor M2 in the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) of the differential amplifier 212 is controlled by the current source I2 in the current source pair (current source I1 and current source I2). At least one current source in the current source pair (current source I1 and current source I2) can be adjusted so that the calibration circuit 210 can calibrate the output differential voltage signal (output signal A220 and output signal B222) based on the input differential voltage signal (input signal A230 and input signal B232) of the differential amplifier 212. In this way, the calibration circuit 210 provides a current regulation mechanism. Figure 2 It is also exemplarily shown that the differential amplifier 212 and the calibration circuit 210 are both operated by the power supply voltage 201. The field effect transistor M3 also has a bias resistor R1 and a bias resistor R2 for providing necessary bias conditions to cooperate with the operation of the differential amplifier 212 and the calibration circuit 210.

[0029] See also Figure 2 The differential amplifier 212 includes a pair of field effect transistors for signal amplification. Therefore, the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) included in the differential amplifier 212 is a differential pair. Figure 1 The differential amplifier circuit 101 shown, Figure 2If there is inconsistency in transistor characteristics, such as inconsistency in transistor parameters, between the paired field effect transistors M1 and M2 for signal amplification inside the differential amplifier 212, an offset voltage may be generated. That is, when an offset voltage exists in the differential amplifier 212, even if the input differential voltage signal (input signal A230 and input signal B232) of the differential amplifier 212 is zero, that is, the voltage of the input signal A230 is equal to the voltage of the input signal B232, at this time, the differential mode component in the output of the differential amplifier 212 is not zero, which may cause the output differential voltage signal (output signal A220 and output signal B222) to be non-zero, that is, the voltage of the output signal A220 is not equal to the voltage of the output signal B222. To this end, by introducing a calibration circuit 210, including a current source pair (current source I1 and current source I2) and a first common-gate field effect transistor pair (field effect transistor M4 and field effect transistor M5) included in the calibration circuit 210, a control mechanism based on the input differential voltage signal (input signal A230 and input signal B232) of the differential amplifier 212 is implemented on the basis of the current regulation mechanism, and then the influence of the offset voltage is offset by calibrating the output differential voltage signal (output signal A220 and output signal B222). Specifically, if the offset voltage is generated due to the inconsistency of the transistor characteristics of the field effect transistor M1 and the field effect transistor M2, that is, the voltage on the load electrode of the field effect transistor M1 is not equal to the voltage on the load electrode of the field effect transistor M2, then in order to avoid the situation that the voltage of the output signal A220 is not equal to the voltage of the output signal B222, at least one current source in the current source pair (current source I1 and current source I2) can be adjusted, and the current size of the current source I1 can be changed, or the current size of the current source I2 can be changed, or the current size of the current source I1 and the current size of the current source I2 can be changed at the same time; in this way, the above-mentioned current adjustment mechanism can be used, for example, the superposition result between the current output of the load electrode of the field effect transistor M5 and the current output of the load electrode of the field effect transistor M2 is controlled by the current source I2, which ensures that the voltage of the output signal A220 is equal to the voltage of the output signal B222, thereby offsetting the influence of the offset voltage.

[0030] See also Figure 2, the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) included in the calibration circuit 210 is a common gate, so the field effect transistor M4 and the field effect transistor M5 do not constitute a differential pair. The field effect transistor M4 and the field effect transistor M5 are used to construct the current regulation mechanism of the calibration circuit 210 to reduce the difference. Therefore, the calibration circuit 210 is based on the current regulation mechanism to control the differential mode component in the output of the differential amplifier 212, that is, to control the voltage at the output end of the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) included in the differential amplifier 212. Here, the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) is a common gate, so the control voltage of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) is not required, and the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) is not a differential pair. By using at least one of the current sources in the current source pair (current source I1 and current source I2) to be adjustable, a fixed-ratio current mirror design, such as a proportional current mirror design, can be implemented, so that the difference between the output signal A220 and the output signal B222 can be fed back to the control of the current source, thereby offsetting the influence of the offset voltage. In this way, compared with the calibration method of directly changing the number of transistors connected to the input stage inside the differential amplifier circuit 101, Figure 2 The calibration circuit 210 for the offset voltage of the differential amplifier 212 shown saves the trouble of adjusting the number of transistors connected in parallel, thus avoiding parasitic effects and increased power consumption. In addition, by replicating the same current mirror mode, that is, the current mirror mode of equal proportion, the current adjustment accuracy can be consistent, that is, the current source I1 and the current source I2 have the same current design accuracy, which reduces the difficulty of chip design and simulation verification. In addition, for the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) introduced by the calibration circuit 210 itself, because the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) is not a differential pair, even if the transistor characteristics of the field effect transistor M4 and the field effect transistor M5 are different, this difference will not affect the offset effect of the offset voltage. Using the above-mentioned current regulation mechanism, it can still be ensured that the voltage of the output signal A220 is equal to the voltage of the output signal B222. In other words, the current regulation mechanism of the calibration circuit 210 is utilized to compensate for the influence of the transistor difference of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) of the calibration circuit 210 itself by controlling the magnitude of the current. In other words, the influence of the transistor difference of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) is taken into consideration when providing the adjustment range of the offset voltage, thereby ensuring that the offset voltage is completely eliminated, providing a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, and realizing uniform calibration, which is conducive to meeting high-bandwidth and high-speed requirements.

[0031] See also Figure 2The type of the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) is different from the type of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5). This design is to achieve input and output common mode design, so as to realize the above-mentioned current regulation mechanism, so that the superposition result between the current output by the load electrode of each of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) and the current output by the load electrode of each of the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) is respectively controlled by the current source pair (current source I1 and current source I2). Figure 2 It is exemplarily shown that the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) is a P-type metal oxide semiconductor (Positive Channel-Metal-Oxide-Semiconductor, PMOS), and the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) is an N-type metal oxide semiconductor (Negative Channel-Metal-Oxide-Semiconductor, NMOS). The gates of field effect transistors M1 and M2, that is, the control electrodes, are respectively connected to input signals A230 and B232. The sources of field effect transistors M1 and M2, that is, the bias electrodes, use a common source, and the common source node is determined by the power supply voltage 201 and field effect transistor M3 ( Figure 2 The field effect transistor M3 is exemplarily shown as a PMOS transistor. The drains of the field effect transistor M1 and the field effect transistor M2, that is, the load electrodes, respectively output currents to the calibration circuit 210 .

[0032] Continue reading Figure 2, the gates of the field effect transistors M4 and M5 are respectively connected to a common gate. The source electrodes, i.e., the load electrodes, of the field effect transistors M4 and M5 are respectively connected to the current source I1 and the current source I2. Moreover, after the current outputted by the drain electrodes, i.e., the load electrodes, of the field effect transistors M1 and M2 are superimposed with the current outputted by the source electrodes, i.e., the load electrodes, of the field effect transistors M4 and M5, they are respectively controlled by the current source I1 and the current source I2. The drain electrodes, i.e., the bias electrodes, of the field effect transistors M4 and M5 are respectively used as the output signals A220 and B222. In this way, by using at least one controllable current source of the current source I1 and the current source I2, and the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) with a common gate, the input and output common mode design is realized. By adjusting the magnitude of the current, it can be ensured that when the input differential voltage signal (input signal A230 and input signal B232) is zero, the output differential voltage signal (output signal A220 and output signal B222) is also zero, that is, the calibration circuit 210 can calibrate the output differential voltage signal (output signal A220 and output signal B222) based on the input differential voltage signal (input signal A230 and input signal B232) of the differential amplifier 212. It should be understood that the type of the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) and the type of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) are determined by the level of the input common mode voltage, as long as the input and output common mode design can be realized. Figure 2 The types of field effect transistors shown are only exemplary.

[0033] In conclusion, Figure 2 The offset voltage calibration circuit 210 shown for the differential amplifier 212 utilizes a current regulation mechanism and an input-output common mode design to achieve offset voltage cancellation. Furthermore, by adopting a proportional current mirror mode, the same calibration step can be provided with the same current regulation accuracy. A high-precision offset voltage calibration function is provided without affecting the bandwidth of the main circuit, thereby achieving uniform calibration and meeting high-bandwidth and high-speed requirements.

[0034] See also Figure 1 and Figure 2 In a possible implementation, when the second field effect transistor pair of the differential amplifier outputs an offset voltage, the calibration circuit adjusts at least one current source in the current source pair to calibrate the output differential voltage signal so as to offset the offset voltage. In this way, the offset voltage is offset by using the current regulation mechanism and the input and output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, providing a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, achieving uniform calibration, and being conducive to meeting high-bandwidth and high-speed requirements.

[0035] In a possible implementation, when the input differential voltage signal of the differential amplifier is zero, the calibration circuit is used to make the output differential voltage signal zero. In this way, the offset voltage is offset by using the current regulation mechanism and the input and output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, and a high-precision offset voltage calibration function is provided without affecting the bandwidth of the main circuit, achieving uniform calibration, which is conducive to meeting high-bandwidth and high-speed requirements.

[0036] In a possible implementation, the current source pair includes a fixed current source and an adjustable current source. In this way, the offset voltage is offset by using the current regulation mechanism and the input-output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, and a high-precision offset voltage calibration function is provided without affecting the bandwidth of the main circuit, achieving uniform calibration, which is conducive to meeting high-bandwidth and high-speed requirements.

[0037] In one possible implementation, the current source pair includes two adjustable current sources. In this way, the offset voltage is offset by using the current regulation mechanism and the input-output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, and a high-precision offset voltage calibration function is provided without affecting the bandwidth of the main circuit, achieving uniform calibration, which is conducive to meeting high-bandwidth and high-speed requirements. In addition, the adjustment range of the offset voltage is expanded by two adjustable current sources, and a completely symmetrical field effect transistor can be provided in the circuit design and layout design, which further helps to offset the influence of the offset voltage.

[0038] In some embodiments, the two adjustable current sources included in the current source pair each have the same current regulation accuracy. In this way, the offset voltage is offset by using the current regulation mechanism and the input and output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, and a high-precision offset voltage calibration function is provided without affecting the bandwidth of the main circuit, achieving uniform calibration, which is conducive to meeting high-bandwidth and high-speed requirements.

[0039] In some embodiments, the first field effect transistor pair and the two adjustable current sources included in the current source pair together form a current mirror with equal proportion and equal calibration step. In this way, the offset voltage is offset by using the current regulation mechanism and the input and output common mode design, and by adopting the equal proportion current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, and a high-precision offset voltage calibration function is provided without affecting the bandwidth of the main circuit, achieving uniform calibration, which is conducive to meeting high bandwidth and high speed requirements.

[0040] In a possible implementation, when the transistor characteristics of the first field effect transistor pair are inconsistent, or when the transistor characteristics of the second field effect transistor pair are inconsistent, the calibration circuit adjusts at least one current source in the current source pair to calibrate the output differential voltage signal to offset the difference in transistor characteristics. In this way, the offset voltage is offset by using the current regulation mechanism and the input and output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, providing a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, achieving uniform calibration, and helping to meet high bandwidth and high speed requirements.

[0041] In one possible implementation, when the input common-mode voltage of the input differential voltage signal of the differential amplifier is low voltage, the first field effect transistor pair is an N-type metal oxide semiconductor, and the second field effect transistor pair is a P-type metal oxide semiconductor, and when the input common-mode voltage of the input differential voltage signal of the differential amplifier is high voltage, the first field effect transistor pair is a P-type metal oxide semiconductor, and the second field effect transistor pair is an N-type metal oxide semiconductor. The type of the second field effect transistor pair (field effect transistor M1 and field effect transistor M2) and the type of the first field effect transistor pair (field effect transistor M4 and field effect transistor M5) are determined by the level of the input common-mode voltage, as long as the input and output common-mode design can be achieved. In this way, the level of the input common-mode voltage can be flexibly adapted to better adapt to the application scenario requirements.

[0042] In a possible implementation, the transistor type of the first field effect transistor pair is different from the transistor type of the second field effect transistor pair, and the first field effect transistor pair and the second field effect transistor pair together constitute an input and output common mode design. In this way, the offset voltage is offset by using the current regulation mechanism and the input and output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, providing a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, achieving uniform calibration, and being conducive to meeting high-bandwidth and high-speed requirements.

[0043] Figure 3A flow chart of a method for calibrating the offset voltage of a differential amplifier provided in an embodiment of the present application. Figure 3 As shown, the calibration method includes the following steps.

[0044] Step S301: providing a first field effect transistor pair with a common gate, wherein the bias electrodes of the first field effect transistor pair are used as output differential voltage signals.

[0045] Step S303: Provide a current source pair, wherein the current source pair is respectively connected to the respective load electrodes of the first field effect transistor pair, and the superposition result between the current output by the respective load electrodes of the first field effect transistor pair and the current output by the respective load electrodes of the second field effect transistor pair used to constitute the differential amplifier is respectively controlled by the current source pair, and at least one current source in the current source pair can be adjusted so that the output differential voltage signal can be calibrated based on the input differential voltage signal of the differential amplifier.

[0046] Figure 3 The offset voltage calibration method for a differential amplifier shown utilizes a current regulation mechanism and an input-output common mode design to achieve offset voltage cancellation. Furthermore, by adopting a proportional current mirror mode, the same calibration step can be provided with the same current regulation accuracy. This provides a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, thereby achieving uniform calibration and meeting high-bandwidth and high-speed requirements.

[0047] See also Figure 3 In a possible implementation, the calibration method further includes: when the second field effect transistor pair of the differential amplifier outputs an offset voltage, the output differential voltage signal is calibrated by adjusting at least one current source in the current source pair to offset the offset voltage. In this way, the offset voltage is offset by using the current regulation mechanism and the input and output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, providing a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, achieving uniform calibration, and being conducive to meeting high bandwidth and high speed requirements.

[0048] In a possible implementation, the current source pair includes a fixed current source and an adjustable current source. In this way, the offset voltage is offset by using the current regulation mechanism and the input-output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, and a high-precision offset voltage calibration function is provided without affecting the bandwidth of the main circuit, achieving uniform calibration, which is conducive to meeting high-bandwidth and high-speed requirements.

[0049] In a possible implementation, the current source pair includes two adjustable current sources, each of which has the same current regulation accuracy, and the first field effect transistor pair and the two adjustable current sources together form a current mirror with equal proportion and equal calibration step. In this way, the offset voltage is offset by using the current regulation mechanism and the input and output common mode design, and by adopting the equal proportion current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, and a high-precision offset voltage calibration function is provided without affecting the bandwidth of the main circuit, achieving uniform calibration, which is conducive to meeting high bandwidth and high speed requirements.

[0050] In a possible implementation, the transistor type of the first field effect transistor pair is different from the transistor type of the second field effect transistor pair, and the first field effect transistor pair and the second field effect transistor pair together constitute an input and output common mode design. In this way, the offset voltage is offset by using the current regulation mechanism and the input and output common mode design, and by adopting the proportional current mirror mode, the same calibration step can be provided according to the same current regulation accuracy, providing a high-precision offset voltage calibration function without affecting the bandwidth of the main circuit, achieving uniform calibration, and being conducive to meeting high-bandwidth and high-speed requirements.

[0051] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0052] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0053] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0054] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0055] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A calibration circuit for an offset voltage of a differential amplifier, characterized in that: The calibration circuit comprises: A first field effect transistor pair with a common gate, wherein the bias electrodes of the first field effect transistor pair are respectively used as output differential voltage signals; A current source pair, wherein the current source pair is respectively connected to the respective load electrodes of the first field effect transistor pair, the superposition result between the current output by the respective load electrodes of the first field effect transistor pair and the current output by the respective load electrodes of the second field effect transistor pair used to constitute a differential amplifier is respectively controlled by the current source pair, and at least one current source in the current source pair can be adjusted so that the calibration circuit can calibrate the output differential voltage signal based on the input differential voltage signal of the differential amplifier.

2. The calibration circuit according to claim 1, characterized in that: When the second field effect transistor pair of the differential amplifier outputs an offset voltage, the calibration circuit calibrates the output differential voltage signal by adjusting at least one current source in the current source pair so as to cancel the offset voltage.

3. The calibration circuit according to claim 1, characterized in that: When the input differential voltage signal of the differential amplifier is zero, the calibration circuit is used to make the output differential voltage signal zero.

4. The calibration circuit according to claim 1, characterized in that: The current source pair includes a fixed current source and an adjustable current source.

5. The calibration circuit according to claim 1, characterized in that: The current source pair includes two adjustable current sources.

6. The calibration circuit according to claim 5, characterized in that: The two adjustable current sources included in the current source pair each have the same current regulation accuracy.

7. The calibration circuit according to claim 5, characterized in that: The first field effect transistor pair and the two adjustable current sources included in the current source pair together form a current mirror with equal proportions and equal calibration steps.

8. The calibration circuit according to claim 1, characterized in that: When the transistor characteristics of the first field effect transistor pair are inconsistent, or when the transistor characteristics of the second field effect transistor pair are inconsistent, the calibration circuit calibrates the output differential voltage signal by adjusting at least one current source in the current source pair to offset the difference in transistor characteristics.

9. The calibration circuit according to claim 1, characterized in that: When the input common-mode voltage of the input differential voltage signal of the differential amplifier is a low voltage, the first field-effect transistor pair is an N-type metal oxide semiconductor and the second field-effect transistor pair is a P-type metal oxide semiconductor, and, when the input common-mode voltage of the input differential voltage signal of the differential amplifier is a high voltage, the first field-effect transistor pair is a P-type metal oxide semiconductor and the second field-effect transistor pair is an N-type metal oxide semiconductor.

10. The calibration circuit according to claim 1, characterized in that: The transistor type of the first field effect transistor pair is different from the transistor type of the second field effect transistor pair, and the first field effect transistor pair and the second field effect transistor pair together form an input and output common mode design.

11. A method for calibrating an offset voltage of a differential amplifier, characterized in that: The calibration method comprises: Providing a first field effect transistor pair with a common gate, wherein the bias electrodes of the first field effect transistor pair are respectively used as output differential voltage signals; A current source pair is provided, wherein the current source pair is respectively connected to the respective load electrodes of the first field effect transistor pair, and the superposition result between the current output by the respective load electrodes of the first field effect transistor pair and the current output by the respective load electrodes of the second field effect transistor pair used to constitute a differential amplifier is respectively controlled by the current source pair, and at least one current source in the current source pair can be adjusted so that the output differential voltage signal can be calibrated based on the input differential voltage signal of the differential amplifier.

12. The calibration method according to claim 11, characterized in that: The calibration method further comprises: When the second field effect transistor pair of the differential amplifier outputs an offset voltage, the output differential voltage signal is calibrated by adjusting at least one current source in the current source pair to cancel the offset voltage.

13. The calibration method according to claim 11, characterized in that: The current source pair includes a fixed current source and an adjustable current source.

14. The calibration method according to claim 11, characterized in that: The current source pair includes two adjustable current sources, each of which has the same current regulation accuracy, and the first field effect transistor pair and the two adjustable current sources together form a current mirror with equal proportions and equal calibration steps.

15. The calibration method according to claim 11, characterized in that: The transistor type of the first field effect transistor pair is different from the transistor type of the second field effect transistor pair, and the first field effect transistor pair and the second field effect transistor pair together form an input and output common mode design.

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