LINK-JOINT asymmetric large delay matching unit based on Schmitt trigger

Abstract

The invention relates to a LINK-JOINT asymmetric large delay matching unit based on a Schmitt trigger and application of the LINK-JOINT asymmetric large delay matching unit. The large delay matching unit comprises an input stage circuit used for realizing inversion and preliminary transmission of signals; an intermediate stage circuit for amplifying the signal and introducing a delay; the inverted proportional tube circuit is used for further increasing the delay time of the signal and realizing voltage following and amplification; the output stage circuit is used for outputting the processed signal; the auxiliary circuit provides a feedback mechanism, the input stage circuit, the intermediate stage circuit, the inverted proportional tube circuit and the output stage circuit are respectively provided with a pair of complementary PMOS (P-channel Metal Oxide Semiconductor) tubes and NMOS (N-channel Metal Oxide Semiconductor) tubes, the auxiliary circuit is provided with two NMOS tubes of which the sources are connected to the same line, an input signal I is connected with the input stage circuit, and an output signal O is connected with the output stage circuit. The large delay matching unit can be applied to an asynchronous self-clock control system of a Bluetooth chip, and the large delay matching unit can be used between nodes of a data path in a delay matching circuit module.

Description

Technical Field

[0001] The invention relates to the technical field of digital circuit design, and in particular to a LINK-JOINT asymmetric large delay matching unit based on a Schmitt trigger. Background Art

[0002] Asynchronous circuits are a type of sequential circuit that does not require synchronous clock signal control. Asynchronous self-clocked circuits are a type of asynchronous circuit. This type of circuit module can generate local clock signals to drive data paths as needed, including self-clocked state machines and asynchronous self-clocked handshake circuits.

[0003] The LINK-JOINT asynchronous self-clocking circuit is a self-clocking asynchronous circuit structure. It integrates different self-clocking asynchronous controllers into the LINK and JOINT handshake circuits, and realizes complex self-clocking control path design through their connection. The design and test process of the LINK-JOINT circuit is highly consistent with the existing synchronous circuit design process, and has good compatibility and testability with the synchronous system.

[0004] In the LINK-JOINT handshake circuit, the JOINT unit is used to perform asymmetric delay matching on the controlled computing unit, so that the asymmetric delay of each match on the control path needs to be greater than the maximum delay of the computing unit in the corresponding data path. At the same time, the cooperation of the asymmetric delay unit and the JOINT circuit produces a low-pass filtering effect on the input handshake signal, eliminating the impact of input glitches in the control path on the control path.

[0005] Delay cells are standard cells that are often used to introduce delays in signal paths in VLSI digital circuit design. They have functions such as adjusting clock distribution, timing synchronization, and signal alignment. At present, there are three main design structures for delay cells: buffer-based delay cells, RC oscillator-based delay cells, and LC circuit-based delay cells. Buffer-based delay cells are the most commonly used delay cells in VLSI design, and their circuit structure consists of multi-stage connected inverters. Although this type of cell has a small area and a simple structure, its delay time is short and its driving capability is poor. The RC oscillator-based delay cell can achieve a larger delay time, but the circuit structure is complex, the dynamic power consumption is high, and the area is large, so it is not suitable for low-power asynchronous circuit design. The LC circuit-based delay cell cannot be used in VLSI standard cell design because it requires the use of inductors.

[0006] CN219875530U discloses an asymmetric delay control circuit, an asynchronous circuit and an asynchronous motor control device, which relate to the technical field of electronic circuits. The control circuit comprises: an input circuit, an output circuit and a common delay module, wherein the common delay module is respectively connected to the input circuit and the output circuit, and the common delay module is used to delay the transmission of the electrical signal of the input circuit to the output circuit; a rising delay module, wherein the rising delay module is respectively connected to the input circuit and the common delay module, and the rising delay module is used to delay the transmission of the rising edge electrical signal input by the input circuit to the common delay module, and the common delay module delays the transmission of the rising edge electrical signal to the output circuit.

[0007] The prior art has the following technical problems:

[0008] (1) Limited delay time: Traditional buffer-based delay cells are difficult to achieve a large delay time under limited area and timing constraints. This is because the delay time of buffer-based delay cells is short, and increasing the delay time will significantly increase the circuit area and complexity.

[0009] (2) Self-oscillation problem: The LINK-JOINT circuit design based on registers and using narrow pulses as trigger signals and local clock outputs has the risk of self-oscillation. Specifically, if the pulse width of the fill and drain signals distributed by the JOINT unit to the previous and next LINK units is greater than the delay width of the rising edge of the narrow pulse trigger, the control signal will cause self-oscillation between the previous and next LINK units, affecting the stability of the system.

[0010] (3) Difficulty in adjusting the delay time: Traditional delay units need to increase the delay time by adding cascade inverters. This method not only increases the complexity and area of ​​the circuit, but also limits the flexibility of adjusting the delay time. Every time the delay time needs to be changed, the topology of the circuit layout needs to be redesigned and modified.

[0011] (4) High power consumption and wiring complexity: The existing LINK-JOINT handshake circuit requires a large number of cascaded buffer-based delay units, which leads to a significant increase in dynamic power consumption, which accounts for about 50% to 90% of the total power consumption. In addition, a large number of cascaded delay units will also increase static power consumption and wiring complexity, affecting the performance and reliability of the overall circuit.

[0012] In addition, on the one hand, there are differences in understanding among those skilled in the art; on the other hand, the applicant studied a large number of documents and patents when making the present invention, but due to space limitations, not all details and contents are listed in detail. However, this does not mean that the present invention does not have the characteristics of these prior arts. On the contrary, the present invention already has all the characteristics of the prior art, and the applicant reserves the right to add relevant prior art to the background technology. Summary of the invention

[0013] In view of the deficiencies of the prior art, the present invention provides a LINK-JOINT asymmetric large delay matching unit based on a Schmitt trigger to solve at least part of the above-mentioned technical problems.

[0014] The present invention discloses a LINK-JOINT asymmetric large delay matching unit based on a Schmitt trigger, which includes: an input stage circuit for realizing signal inversion and preliminary transmission; an intermediate stage circuit for amplifying the signal and introducing delay; an inverted proportional tube circuit for further increasing the delay time of the signal to realize voltage following and amplification; an output stage circuit for outputting the processed signal; and an auxiliary circuit for providing a feedback mechanism. The input stage circuit, the intermediate stage circuit, the inverted proportional tube circuit and the output stage circuit respectively have a pair of complementary PMOS tubes and NMOS tubes, and the auxiliary circuit has two NMOS tubes whose source electrodes are connected to the same line, wherein the input signal I is connected to the input stage circuit, and the output signal O is connected to the output stage circuit.

[0015] According to a preferred embodiment, the input stage circuit includes a complementary PMOS tube mp1 and an NMOS tube mn1, wherein the source of the PMOS tube mp1 is connected to the power supply VCC, the drain is connected to the line n1, and the gate is connected to the input signal I; the source of the NMOS tube mn1 is connected to the ground GND, the drain is connected to the line n1, and the gate is connected to the input signal I.

[0016] According to a preferred embodiment, the intermediate stage circuit includes a complementary PMOS tube mp2 and an NMOS tube mn2, wherein the source of the PMOS tube mp2 is connected to the power supply VCC, the drain is connected to the line n2, and the gate is connected to the line n1; the source of the NMOS tube mn2 is connected to the ground GND, the drain is connected to the line n2, and the gate is connected to the line n1.

[0017] According to a preferred embodiment, the inverted ratio transistor circuit includes a complementary PMOS transistor mp3 and an NMOS transistor mn3, wherein the source of the PMOS transistor mp3 is connected to the power supply VCC, the drain is connected to the line n3, and the gate is connected to the line n2; the source of the NMOS transistor mn3 is connected to the ground GND, the drain is connected to the line n4, and the gate is connected to the line n2.

[0018] According to a preferred embodiment, the output stage circuit includes a complementary PMOS tube mp4 and an NMOS tube mn4, wherein the source of the PMOS tube mp4 is connected to the power supply VCC, the drain is connected to the output signal O, and the gate is connected to the line n3; the source of the NMOS tube mn4 is connected to the ground GND, the drain is connected to the output signal O, and the gate is connected to the line n3.

[0019] According to a preferred embodiment, the auxiliary circuit includes an NMOS tube mn6 ​​and an NMOS tube mn7, wherein the source of the NMOS tube mn6 ​​is connected to the line n4, the drain is connected to the line n3, and the gate is connected to the line n2; the source of the NMOS tube mn7 is connected to the line n4, the drain is connected to the power supply VCC, and the gate is connected to the line n3.

[0020] According to a preferred embodiment, when the level of the input signal I increases, the large delay matching unit performs a rising edge charging trigger process, which includes:

[0021] The PMOS tube mp1 is turned off, and the NMOS tube mn1 is turned on and pulls down the line n1;

[0022] The NMOS tube mn2 is turned off, the PMOS tube mp2 is turned on and charges the gate capacitances of the PMOS tube mp3, the NMOS tube mn6 ​​and the NMOS tube mn3 connected to the line n2;

[0023] As the voltage of line n2 rises, the PMOS tube mp3 changes from on to off, the voltage of line n3 decreases, and at the same time, the NMOS tube mn3 changes from off to on;

[0024] As the voltage on line n2 rises to the Schmitt rising edge trigger voltage V TLH , the voltage of line n3 drops to less than the threshold voltage of NMOS tube mn7, NMOS tube mn7 changes from on to off, the voltage of line n4 is pulled down to a low level by NMOS tube mn3, and NMOS tube mn6 ​​enters the saturation region to further pull down the voltage of line n3;

[0025] The NMOS tube mn4 is turned off, and the PMOS tube mp4 is turned on and pulls up the output signal O.

[0026] According to a preferred embodiment, when the level of the input signal I decreases, the large delay matching unit performs a falling edge discharge triggering process, which includes:

[0027] NMOS tube mn1 is turned off, PMOS tube mp1 is turned on and pulls up line n1;

[0028] The PMOS tube mp2 is turned off, and the NMOS tube mn2 is turned on to discharge the gate capacitances of the PMOS tube mp3, the NMOS tube mn6, and the NMOS tube mn3 connected to the line n2;

[0029] As the voltage of line n2 drops to less than the power supply VCC minus the threshold voltage of PMOS tube mp3, PMOS tube mp3 is turned on and pulls up line n3, PMOS tube mp4 is turned off, NMOS tube mn4 is turned on and pulls down the output signal O, NMOS tube mn7 changes from being turned off to being turned on and pulls up line n4, so that NMOS tube mn6 ​​is turned off and NMOS tube mn3 is turned on;

[0030] When the line n2 finishes discharging, the NMOS tube mn3 changes from on to off.

[0031] According to a preferred embodiment, the process of the large delay matching unit matching the corresponding data path in the LINK-JOINT handshake circuit includes:

[0032] In the initial state, set the LINK1 unit to an empty state and the LINK3 unit to an empty state;

[0033] When a narrow pulse triggers Fill 1, register r1 updates the output data and changes the LINK1 unit from the empty state to the full state, and the Full state 1 is pulled high and passed as input to the corresponding asymmetric large delay matching unit;

[0034] The corresponding asymmetric large delay matching unit only delays the rising edge to ensure that when the full state signal is transmitted to the combinational logic CL in the JOINT unit, the input data of register r3 is stable, and the state switching of LINK3 unit and LINK1 unit is controlled through the JOINT unit;

[0035] After the empty state 3 signal changes, the JOINT unit controls the filling and emptying signals of the previous and next stage LINK units and latches the output data of register r2. At the same time, the falling edge of the full state 1 directly acts on the combinational logic CL in the JOINT unit.

[0036] The present invention also discloses an application of the aforementioned large delay matching unit in an asynchronous self-clock control system of a Bluetooth chip. The large delay matching unit can be used between various nodes of a data path in a delay matching circuit module to match the delays of different data paths and ensure that the signal arrives at the target register or storage unit synchronously during the transmission process.

[0037] In order to prevent the self-oscillation of the front and rear stage LINK units, the present invention only uses the rising trigger network part of the Schmitt trigger to achieve the delay of the rising edge. In this way, it can be ensured that the pulse width of the filling and emptying signals distributed by the JOINT unit to the front and rear stage LINK units is smaller than the delay width of the narrow pulse trigger to the rising edge. This effectively prevents the control signal from generating self-oscillation between the front and rear stage LINK units, ensures the stable operation of the system, and avoids timing violations.

[0038] The present invention has the characteristics of strong multiplexing and easy adjustment of delay time. By fine-tuning the channel length of the inverted proportional tube, the delay time can be increased without adding cascade inverters and changing the topological structure of the circuit layout. This provides great convenience for the design and implementation of asynchronous self-clock control systems, and can more flexibly adapt to the delay matching requirements of different asynchronous self-clock schemes based on the four-way handshake protocol.

[0039] The introduction of the Schmitt trigger structure can significantly reduce the dynamic power consumption of the delay unit. Compared with a large number of cascaded buffer-based delay units, the area of ​​the large delay matching unit of the present invention is significantly reduced, thereby reducing static power consumption and wiring complexity. In the asynchronous self-clock control system of the chip, this not only means lower energy consumption and higher efficiency, but also helps to extend the service life of the equipment and reduce maintenance frequency and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a circuit diagram of a large delay matching unit provided by the present invention;

[0041] Figure 2 It is a schematic diagram of the large delay matching unit provided by the present invention matching the corresponding data path in the LINK-JOINT handshake circuit; DETAILED DESCRIPTION

[0042] The following is a detailed description with reference to the accompanying drawings.

[0043] In the present invention, "asymmetric" means that only one input level change from a low level to a high level or from a high level to a low level is delayed, and there is no delay for the opposite level change.

[0044] In the present invention, "large delay" refers to a delay of hundreds of nanoseconds.

[0045] Example 1

[0046] The present invention discloses a LINK-JOINT asymmetric large delay matching unit based on a Schmitt trigger, which comprises: an input stage circuit, which is used to realize the inversion and preliminary transmission of a signal and has a noise suppression function; an intermediate stage circuit, which is used to amplify the signal and introduce a delay to ensure the stability and reliability of the signal; an inverted proportional tube circuit, which is used to further increase the delay time of the signal and realize voltage following and amplification; an output stage circuit, which outputs the processed signal and has a strong driving ability; and an auxiliary circuit, which provides a feedback mechanism and enhances the stability and anti-noise ability of the signal.

[0047] A Schmitt trigger is a circuit that converts an input analog signal into a digital signal and has hysteresis, and its output voltage has different switching thresholds for the rising and falling edges of the input signal. This hysteresis can be used to improve the noise immunity and signal integrity of digital circuits.

[0048] Preferably, the input stage circuit may include a complementary PMOS transistor and an NMOS transistor, which are a PMOS transistor mp1 and an NMOS transistor mn1, respectively. Figure 1 As shown, the source of the PMOS tube mp1 is connected to the power supply VCC, the drain is connected to the line n1, and the gate is connected to the input signal I; the source of the NMOS tube mn1 is connected to the ground GND, the drain is connected to the line n1, and the gate is connected to the input signal I. When the input signal I is at a low level, the PMOS tube mp1 is turned on, the NMOS tube mn1 is turned off, and the line n1 is pulled up to a high level. When the input signal I is at a high level, the PMOS tube mp1 is turned off, the NMOS tube mn1 is turned on, and the line n1 is pulled down to a low level. Further, the main function of the input stage circuit is to control the potential of the line n1 according to the state of the input signal I. By using complementary PMOS tubes and NMOS tubes, the input stage circuit can effectively suppress the noise in the input signal and ensure the stability and reliability of the signal.

[0049] "Complementary PMOS and NMOS" is one of the basic building blocks in CMOS (complementary metal oxide semiconductor) technology. In CMOS technology, the circuit is composed of complementary PMOS (P-type metal oxide semiconductor) and NMOS (N-type metal oxide semiconductor) transistors. These two types of transistors have different conductive characteristics: PMOS tubes are usually turned on when a low voltage is applied to the gate, suitable for pulling the output close to the power supply voltage (logical high level), usually with a high on-resistance, so the speed is relatively slow, but the power consumption is low when pulling the output level; NMOS tubes are usually turned on when a high voltage is applied to the gate (that is, allowing current to flow from the drain to the source), suitable for pulling the output down to close to 0 volts (logical low level), with a lower on-resistance, so it provides faster speed when driving. In CMOS circuits, PMOS tubes and NMOS tubes are used in a complementary combination. When the circuit switches state, one is turned on and the other is cut off. The main advantages of this configuration include: low static power consumption: in steady state (i.e. when the circuit output is unchanged), one transistor is always in the off state, so the current is almost zero; high noise margin: due to the complementary use of two types of transistors, CMOS circuits have a higher tolerance to noise; high speed and density: CMOS technology allows the creation of faster and smaller integrated circuits. Preferably, in the present invention, the transistor may especially refer to a MOSFET (metal oxide field effect transistor).

[0050] The source is the port through which current enters the transistor, where in NMOS transistors, the source is usually connected to a lower potential (such as ground); while in PMOS transistors, the source is usually connected to a higher potential (such as power supply). The drain is the port through which current leaves the transistor, where in NMOS transistors, the drain is usually connected to a higher potential; while in PMOS transistors, the drain is usually connected to a lower potential. The gate (also called "gate") controls the conduction and cutoff of the transistor. By applying an electric field to the gate, the formation of a conductive channel in the semiconductor material can be regulated. The voltage between the gate and the source determines the switching state of the transistor. For NMOS transistors, when the gate voltage is higher than the source voltage, the transistor is turned on; and for PMOS transistors, when the gate voltage is lower than the source voltage, the transistor is turned on.

[0051] The power supply VCC provides the required electrical energy for the circuit. It is the starting point for the flow of current and powers the active and passive components in the circuit. In CMOS circuits, the power supply VCC is usually connected to the source of the PMOS tube, so that the PMOS tube can pull a certain line to the power supply VCC voltage by turning on. The ground GND is the end point of the current flow. The current flows out of the power supply, passes through the circuit and finally returns to the ground, which is usually regarded as 0 potential. In NMOS tubes, the ground GND is usually connected to the source of the NMOS tube, so that when the transistor is turned on, a certain line can be pulled down to a voltage close to the ground GND.

[0052] Preferably, the intermediate stage circuit may include a complementary PMOS transistor and an NMOS transistor, which are a PMOS transistor mp2 and an NMOS transistor mn2, respectively, wherein Figure 1As shown, the source of the PMOS tube mp2 is connected to the power supply VCC, the drain is connected to the line n2, and the gate is connected to the line n1; the source of the NMOS tube mn2 is connected to the ground GND, the drain is connected to the line n2, and the gate is connected to the line n1. The intermediate circuit amplifies the potential change of the line n1 through the complementary operation of the PMOS tube mp2 and the NMOS tube mn2, and generates a certain delay. When the line n1 is at a low level, the PMOS tube mp2 is turned on, the NMOS tube mn2 is turned off, and the line n2 is pulled up to a high level. When the line n1 is at a high level, the PMOS tube mp2 is turned off, the NMOS tube mn2 is turned on, and the line n2 is pulled down to a low level. Furthermore, due to the gate capacitance effect of the PMOS tube mp2 and the NMOS tube mn2, the voltage change of the line n2 will have a time constant, thereby introducing a delay, which helps to achieve the desired delay effect. The gate capacitance effect refers to the parasitic capacitance formed between the gate and the source and drain of the transistor. The presence of this capacitance affects the switching speed and signal transmission characteristics of the MOSFET, thus playing an important role in the switching process of the transistor, especially in signal transmission and delay. One of the design goals of the intermediate stage circuit is to introduce delays to achieve specific signal processing effects. The gate capacitance effect naturally provides this delay without additional circuit complexity. By selecting the appropriate transistor size and gate capacitance value, the delay time can be precisely controlled to meet the design requirements. The gate capacitance effect helps to smooth the rising and falling edges of the signal, reduce signal spikes and glitches, and improve signal integrity, which is very important for applications that require high stability and reliability.

[0053] Preferably, the inverse ratio transistor circuit may include a complementary PMOS transistor and an NMOS transistor, which are a PMOS transistor mp3 and an NMOS transistor mn3, respectively, wherein Figure 1As shown, the source of the PMOS tube mp3 is connected to the power supply VCC, the drain is connected to the line n3, and the gate is connected to the line n2; the source of the NMOS tube mn3 is connected to the ground GND, the drain is connected to the line n4, and the gate is connected to the line n2. The inverted proportional transistor is a special type of transistor, which is characterized by a channel length (L) greater than the channel width (W), so that the transistor has unique advantages in delay circuits and voltage followers. Due to the long channel length, the threshold voltage (Vth) of the inverted proportional transistor is usually higher. The threshold voltage is the minimum gate voltage required for the transistor to start conducting. A higher threshold voltage means that the transistor will not turn on easily at a lower gate voltage, which helps to improve the stability and noise resistance of the circuit. The transconductance of the inverted proportional transistor is usually lower, because the longer channel length reduces the mobility of the charge carriers. The lower transconductance means that the transistor has a smaller gain, but it also reduces signal distortion and improves linearity. Increasing the channel length of the inverted proportional tube while keeping the channel width unchanged can increase the gate capacitance area, thereby increasing the gate capacitance Cgs and increasing the charging time of the input signal to achieve the purpose of accurately adjusting the delay time of the delay unit by configuring the channel length. The threshold voltage modulation (DIBL effect) is weak in the inverted proportional tube, which helps to improve the stability and reliability of the MOSFET, wherein the DIBL effect refers to the phenomenon that the threshold voltage decreases when the source-drain voltage of the MOSFET increases. The inverted proportional tube circuit further increases the delay time of the signal through the complementary operation of the PMOS tube mp3 and the NMOS tube mn3. When the line n2 is at a high level, the PMOS tube mp3 is turned off, the NMOS tube mn3 is turned on, and the line n3 is pulled down to a low level. When the line n2 is at a low level, the PMOS tube mp3 is turned on, the NMOS tube mn3 is turned off, and the line n3 is pulled up to a high level. Furthermore, the combination of the PMOS tube mp3 and the NMOS tube mn3 can achieve voltage following and amplification, ensuring that the signal maintains sufficient strength and stability during the transmission process.

[0054] Preferably, the output stage circuit may include a complementary PMOS transistor and an NMOS transistor, which are a PMOS transistor mp4 and an NMOS transistor mn4, respectively. Figure 1As shown, the source of the PMOS tube mp4 is connected to the power supply VCC, the drain is connected to the output signal O, and the gate is connected to the line n3; the source of the NMOS tube mn4 is connected to the ground GND, the drain is connected to the output signal O, and the gate is connected to the line n3. The output stage circuit is responsible for outputting the signal processed by the previous stages. When the line n3 is at a low level, the PMOS tube mp4 is turned on, the NMOS tube mn4 is turned off, and the output signal O is pulled up to a high level; when the line n3 is at a high level, the PMOS tube mp4 is turned off, the NMOS tube mn4 is turned on, and the output signal O is pulled down to a low level. Furthermore, the PMOS tube mp4 and the NMOS tube mn4 usually select larger transistors to provide stronger driving capabilities to ensure that the output signal can drive subsequent loads.

[0055] Preferably, the auxiliary circuit may include an NMOS transistor mn6 and an NMOS transistor mn7, wherein Figure 1 As shown, the source of the NMOS tube mn6 ​​is connected to the line n4, the drain is connected to the line n3, and the gate is connected to the line n2; the source of the NMOS tube mn7 is connected to the line n4, the drain is connected to the power supply VCC, and the gate is connected to the line n3.

[0056] Preferably, when the input signal I changes from a low level to a high level, the large delay matching unit performs a rising edge charging trigger process, and the specific steps are as follows:

[0057] When the input signal I becomes high level, the PMOS tube mp1 is turned off, the NMOS tube mn1 is turned on and pulls down the line n1;

[0058] When line n1 changes to a low level, NMOS tube mn2 is turned off, PMOS tube mp2 is turned on and charges the gate capacitances of PMOS tube mp3, NMOS tube mn6 ​​and NMOS tube mn3 connected to line n2;

[0059] As the voltage of line n2 rises, the PMOS tube mp3 changes from on to off, the voltage of line n3 decreases, and at the same time, the NMOS tube mn3 changes from off to on;

[0060] As the voltage on line n2 rises to the Schmitt rising edge trigger voltage V TLH That is, when the voltage of line n3 drops to less than the threshold voltage of NMOS tube mn7, NMOS tube mn7 changes from on to off, the voltage of line n4 is pulled down to a low level by NMOS tube mn3, and NMOS tube mn6 ​​enters the saturation region to further pull down the voltage of line n3;

[0061] When the line n3 is at a low level, the NMOS tube mn4 is turned off, the PMOS tube mp4 is turned on and pulls up the output signal O to a high level.

[0062] Preferably, the Schmidt rising edge trigger voltage V TLHAlso called the positive threshold voltage, it defines the voltage threshold at which the flip-flop switches state when the input voltage rises from a low level to a high level. Specifically: When the input voltage exceeds V TLH When the input voltage drops from high to low, the output voltage of the Schmitt trigger switches from high to low. This characteristic of the Schmitt trigger helps filter out noise and ensure the stability and reliability of the input signal.

[0063] Preferably, when the input signal I changes from a high level to a low level, the large delay matching unit performs a falling edge discharge triggering process, and the specific steps are as follows:

[0064] When I becomes low level, NMOS tube mn1 is turned off, PMOS tube mp1 is turned on and pulls up line n1;

[0065] When line n1 changes to a high level, PMOS tube mp2 is turned off, NMOS tube mn2 is turned on and discharges the gate capacitances of PMOS tube mp3, NMOS tube mn6 ​​and NMOS tube mn3 connected to line n2;

[0066] As the voltage of line n2 drops to a value less than the power supply VCC minus the threshold voltage of the PMOS tube mp3, the PMOS tube mp3 is turned on and pulls up the line n3. Since the voltage of line n3 is greater than the threshold voltage of the NMOS tube mn4, the PMOS tube mp4 is turned off, and the NMOS tube mn4 is turned on and pulls down the output signal O. At this time, the discharge process of line n2 has not yet ended. At the same time, since the voltage of line n3 is greater than the threshold voltage of the NMOS tube mn7, the NMOS tube mn7 changes from being turned off to being turned on and pulls the line n4 to a high level, so that the NMOS tube mn6 ​​is turned off and the NMOS tube mn3 is turned on.

[0067] When the line n2 finishes discharging, the NMOS tube mn3 changes from on to off.

[0068] Preferably, Tran (Transient Analysis) refers to transient analysis, which is a circuit simulation technology used to simulate the dynamic behavior of a circuit in the time domain. Through transient analysis, the response of the circuit under a specific input signal can be observed, such as the rise time, fall time, and steady state of the signal. Parameter scanning refers to a series of values ​​of a certain parameter in the circuit (such as resistance value, capacitance value, voltage, etc.) during the simulation process to observe the impact of the parameter change on the circuit performance. This helps to optimize the circuit design and ensure that the circuit can work properly under different parameter values. In integrated circuit design, layout design refers to the process of converting circuit design into physical layout. Layout design needs to consider wiring, device placement, power supply and ground layout, etc. to ensure the feasibility and performance of the circuit in physical implementation. Further, it can be determined through Tran parameter scanning simulation that the large delay matching unit of the present invention can achieve delay matching from 1us to 100ns, and can realize standard unit characterization. Standard cell characterization is an important step in integrated circuit design. It refers to obtaining the electrical characteristic data of standard cells under different working conditions through simulation and testing, and recording them for use in subsequent design and verification processes. Among them, standard cells are predefined logical function modules commonly used in integrated circuit design.

[0069] Preferably, the large delay matching unit can be used in a LINK-JOINT handshake circuit to match a corresponding data path, wherein the LINK-JOINT handshake circuit may include a plurality of LINK units and a JOINT unit. Preferably, the fill (input) of each LINK unit may be connected to a corresponding register. Preferably, a corresponding large delay matching unit may be provided between the full state (output) of some LINK units and the JOINT unit. For example, Figure 2 As shown, the LINK-JOINT handshake circuit may include three LINK units, namely, LINK1 unit, LINK2 unit and LINK3 unit, wherein fill 1, fill 2 and fill 3 of LINK1 unit, LINK2 unit and LINK3 unit are respectively connected with respective corresponding registers, namely, register r1, register r2 and register r3; respective large delay matching units, namely, ADLY1 and ADLY2, may be respectively arranged between full state 1 and full state 2 of LINK1 unit and LINK2 unit and JOINT unit. Further, there is a data path Arc1 between register r1 and register r3, and there is a data path Arc2 between register r2 and register r3, wherein ADLY1 and ADLY2 may be matched with respective corresponding data paths, namely, ADLY1 may be matched with data path Arc1, and ADLY2 may be matched with data path Arc2.

[0070] Preferably, taking the above LINK-JOINT handshake circuit as an example, the process of the large delay matching unit of the present invention matching the corresponding data path in the LINK-JOINT handshake circuit may include:

[0071] S1. Assume that the LINK1 unit is in the empty state in the initial state. At this time, the signal empty state 1 is high level and the full state 1 is low level. The LINK3 unit is in the empty state. At this time, the empty state 3 is high level and the full state 3 is low level. The combinational logic CL in the JOINT unit is OR. At this time, all filling and emptying signals are low level.

[0072] S2. When a narrow pulse is input to the control input fill 1, register r1 is opened and the output data is updated, the data path combinational logic CL starts to calculate, and the LINK1 unit changes from an empty state to a full state. At this time, the empty state 1 becomes a low level while the full state 1 becomes a high level and is passed as input to the asymmetric large delay matching unit ADLY1.

[0073] S3. Since the delay time of ADLY1 to the rising edge is greater than the maximum delay time of the corresponding data path Arc1 from register r1 to r3, when the high level of full state 1 is transmitted to the combinational logic CL of JOINT through ADLY1, the input data of register r3 has been stable. After the OR calculation of the combinational logic CL in the JOINT unit and the output F is pulled high, since the empty state 3 is also high at this time, the AND gate in the JOINT generates a high level output and is transmitted in two ways to the fill 3 of the LINK3 unit and the empty input of the LINK1 unit and the LINK2 unit. Register r2 is opened and the output is updated. The LINK3 unit becomes full state, and the empty state 3 becomes low level and the full state 3 becomes high level at the same time; the LINK1 unit becomes empty state, and the empty state 1 becomes high level and the full state 1 becomes low level at the same time.

[0074] S4. Since the empty state 3 becomes low level, the AND gate fill 3 in the JOINT unit becomes low level and pulls down the fill and empty signals of the previous and next stage LINK units, and latches the output data of r2. At the same time, since the asymmetric large delay unit ADLY1 has no delay effect on the falling edge, the full state 1 falling edge also directly acts on the combinational logic CL in the JOINT unit.

[0075] Preferably, the combinatorial logic CL of the data path does not need to ensure that the output generates glitches, and its function is to use the data outputs of registers r1 and r2 as inputs for calculation, and pass the calculation results to the data output of register r3. The combinatorial logic CL in the JOINT unit belongs to the self-clock control path, and it is necessary to ensure that the output does not generate glitches. The combinatorial logic CL of the JOINT unit in the self-clock control path of the LINK-JOINT corresponds to the combinatorial logic CL in the data path in terms of function.

[0076] Example 2

[0077] This embodiment is a further improvement on Embodiment 1, and the repeated contents will not be repeated here.

[0078] In the design of low-power asynchronous self-clock control system of Bluetooth chip, the delay matching of asynchronous control path may face a series of defects. The existing delay matching unit mainly has problems such as large area, poor driving capability, excessive dynamic power consumption and static power consumption, and difficulty in integration. Especially in the absence of Schmitt trigger, the asymmetric large delay matching technology for LINK-JOINT asynchronous self-clock control path faces more challenges. In order to ensure that the data path matched by the control path meets the timing constraints, the delay matching inside the JOINT unit needs to cover the maximum transmission delay of its corresponding combinational logic through cascaded buffer delay units. In addition, it is necessary to add gate circuits to realize the asymmetric delay of the four-way handshake protocol of LINK-JOINT. However, this method will take up too much area in chip layout design, increase the static power consumption of the chip, and its delay effect is affected by layout and wiring, which cannot be accurately controlled, and also increases the failure rate of the chip. In addition, due to the problems of large dynamic power consumption and inability to integrate, RC delay unit and LC delay unit are not suitable for delay matching of LINK-JOINT asynchronous self-clock control path.

[0079] In order to overcome these problems, the LINK-JOINT asymmetric large delay matching unit based on Schmitt trigger of the present invention can be integrated into the key circuit part of the (low power) asynchronous self-clock control system of the Bluetooth chip. In other words, the present invention also discloses an application of the LINK-JOINT asymmetric large delay matching unit based on Schmitt trigger in the (low power) asynchronous self-clock control system of the Bluetooth chip, and a (low power) asynchronous self-clock control system of the Bluetooth chip. This not only effectively solves the area and power consumption problems of the delay matching unit in the existing Bluetooth chip, but also improves the accuracy and reliability of delay matching.

[0080] Preferably, the large delay matching unit of the present invention can be used in a delay matching circuit module, especially between various nodes of the data path of the module, and its main purpose is to match the delays of different data paths to ensure that the signal reaches the target register or storage unit synchronously during the transmission process. The large delay matching unit of the present invention makes the data reach a stable state on the data path by accurately delaying the rising edge signal in the delay matching circuit module, thereby avoiding data errors caused by timing mismatch.

[0081] By inserting a link-joint asymmetric large delay matching unit based on Schmitt trigger in these key circuit parts, the performance of the entire asynchronous self-clock control system can be significantly improved.

[0082] The large delay matching unit of the present invention involves delay matching of four asynchronous handshake input signals in the asynchronous self-clock control system of the Bluetooth chip to ensure the normal operation of the asynchronous self-clock control path.

[0083] It should be noted that the above-mentioned specific embodiments are exemplary, and those skilled in the art can come up with various solutions inspired by the disclosure of the present invention, and these solutions also belong to the disclosure scope of the present invention and fall within the protection scope of the present invention. Those skilled in the art should understand that the present invention specification and its drawings are illustrative and do not constitute a limitation of the claims. The scope of protection of the present invention is defined by the claims and their equivalents. The present invention specification contains multiple inventive concepts, such as "preferably" or "according to a preferred embodiment", which means that the corresponding paragraph discloses an independent concept, and the applicant reserves the right to file a divisional application based on each inventive concept. Throughout the text, the features guided by "preferably" are only an optional method and should not be understood as a must-have setting. Therefore, the applicant reserves the right to abandon or delete the relevant preferred features at any time.

Claims

1. A LINK-JOINT asymmetric large delay matching unit based on a Schmitt trigger, characterized in that: It includes: Input stage circuit, used to realize signal inversion and preliminary transmission; Intermediate stage circuits to amplify the signal and introduce delay; The inverted proportional tube circuit is used to further increase the delay time of the signal and realize voltage following and amplification; The output stage circuit outputs the processed signal; Auxiliary circuit, providing feedback mechanism, The input stage circuit, the intermediate stage circuit, the inverse proportional tube circuit and the output stage circuit respectively have a pair of complementary PMOS tubes and NMOS tubes, and the auxiliary circuit has two NMOS tubes whose sources are connected to the same line, wherein the input signal I is connected to the input stage circuit, and the output signal O is connected to the output stage circuit.

2. The large delay matching unit according to claim 1, characterized in that: The input stage circuit includes a complementary PMOS tube mp1 and an NMOS tube mn1, wherein the source of the PMOS tube mp1 is connected to the power supply VCC, the drain is connected to the line n1, and the gate is connected to the input signal I; the source of the NMOS tube mn1 is connected to the ground GND, the drain is connected to the line n1, and the gate is connected to the input signal I.

3. The large delay matching unit according to claim 1 or 2, characterized in that: The intermediate stage circuit includes a complementary PMOS tube mp2 and an NMOS tube mn2, wherein the source of the PMOS tube mp2 is connected to the power supply VCC, the drain is connected to the line n2, and the gate is connected to the line n1; the source of the NMOS tube mn2 is connected to the ground GND, the drain is connected to the line n2, and the gate is connected to the line n1.

4. The large delay matching unit according to any one of claims 1 to 3, characterized in that: The inverted ratio transistor circuit includes a complementary PMOS transistor mp3 and an NMOS transistor mn3, wherein the source of the PMOS transistor mp3 is connected to the power supply VCC, the drain is connected to the line n3, and the gate is connected to the line n2; the source of the NMOS transistor mn3 is connected to the ground GND, the drain is connected to the line n4, and the gate is connected to the line n2.

5. The large delay matching unit according to any one of claims 1 to 4, characterized in that: The output stage circuit includes a complementary PMOS tube mp4 and an NMOS tube mn4, wherein the source of the PMOS tube mp4 is connected to the power supply VCC, the drain is connected to the output signal O, and the gate is connected to the line n3; the source of the NMOS tube mn4 is connected to the ground GND, the drain is connected to the output signal O, and the gate is connected to the line n3.

6. The large delay matching unit according to any one of claims 1 to 5, characterized in that: The auxiliary circuit includes NMOS tube mn6 ​​and NMOS tube mn7, wherein the source of NMOS tube mn6 ​​is connected to line n4, the drain is connected to line n3, and the gate is connected to line n2; the source of NMOS tube mn7 is connected to line n4, the drain is connected to power supply VCC, and the gate is connected to line n3.

7. The large delay matching unit according to any one of claims 1 to 6, characterized in that: When the level of the input signal I increases, the large delay matching unit performs a rising edge charging trigger process, which includes: The PMOS tube mp1 is turned off, and the NMOS tube mn1 is turned on and pulls down the line n1; The NMOS tube mn2 is turned off, the PMOS tube mp2 is turned on and charges the gate capacitances of the PMOS tube mp3, the NMOS tube mn6 ​​and the NMOS tube mn3 connected to the line n2; As the voltage of line n2 rises, the PMOS tube mp3 changes from on to off, the voltage of line n3 decreases, and at the same time, the NMOS tube mn3 changes from off to on; As the voltage on line n2 rises to the Schmitt rising edge trigger voltage V TLH , the voltage of line n3 drops to less than the threshold voltage of NMOS tube mn7, NMOS tube mn7 changes from on to off, the voltage of line n4 is pulled down to a low level by NMOS tube mn3, and NMOS tube mn6 ​​enters the saturation region to further pull down the voltage of line n3; The NMOS tube mn4 is turned off, and the PMOS tube mp4 is turned on and pulls up the output signal O.

8. The large delay matching unit according to any one of claims 1 to 7, characterized in that: When the level of the input signal I decreases, the large delay matching unit performs a falling edge discharge triggering process, which includes: NMOS tube mn1 is turned off, PMOS tube mp1 is turned on and pulls up line n1; The PMOS tube mp2 is turned off, and the NMOS tube mn2 is turned on to discharge the gate capacitances of the PMOS tube mp3, the NMOS tube mn6, and the NMOS tube mn3 connected to the line n2; As the voltage of line n2 drops to less than the power supply VCC minus the threshold voltage of PMOS tube mp3, PMOS tube mp3 is turned on and pulls up line n3, PMOS tube mp4 is turned off, NMOS tube mn4 is turned on and pulls down the output signal O, NMOS tube mn7 changes from being turned off to being turned on and pulls up line n4, so that NMOS tube mn6 ​​is turned off and NMOS tube mn3 is turned on; When the line n2 finishes discharging, the NMOS tube mn3 changes from on to off.

9. The large delay matching unit according to any one of claims 1 to 8, characterized in that: The process of the large delay matching unit matching the corresponding data path in the LINK-JOINT handshake circuit includes: In the initial state, set the LINK1 unit to an empty state and the LINK3 unit to an empty state; When a narrow pulse triggers Fill 1, register r1 updates the output data and changes the LINK1 unit from the empty state to the full state, and the Full state 1 is pulled high and passed as input to the corresponding asymmetric large delay matching unit; The corresponding asymmetric large delay matching unit only delays the rising edge to ensure that when the full state signal is transmitted to the combinational logic CL in the JOINT unit, the input data of register r3 is stable, and the state switching of LINK3 unit and LINK1 unit is controlled through the JOINT unit; After the empty state 3 signal changes, the JOINT unit controls the filling and emptying signals of the previous and next stage LINK units and latches the output data of register r2. At the same time, the falling edge of the full state 1 directly acts on the combinational logic CL in the JOINT unit.

10. An application of the large delay matching unit according to any one of claims 1 to 9 in an asynchronous self-clock control system of a Bluetooth chip, characterized in that: The large delay matching unit can be used between various nodes of the data path in the delay matching circuit module to match the delays of different data paths and ensure that the signal reaches the target register or storage unit synchronously during the transmission process.

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