Direction automatic identification circuit applied to signal chain circuit

Abstract

The invention relates to an automatic direction identification circuit applied to a signal chain circuit, and belongs to the technical field of electronics. The direction automatic identification circuit applied to the signal chain circuit comprises an acceleration pull-up I / O module, a rising edge detection module, a single trigger pulse module and a falling edge detection and direction control module. The falling edge detection and direction control module detects the acceleration pull-up I / O module through the rising edge detection module to judge a signal at one end of the I / O port A and the I / O port B to serve as a driving circuit, and controls the other end of the I / O port A and the I / O port B to give a corresponding output signal through the single trigger pulse module and the falling edge detection and direction control module; the acceleration drive output end is pulled up; when the falling edge is detected, the control right is given to the signal on the other side; when no signal is input to the two ends, the levels on the two sides need to be pulled up so as to prevent misjudgment of a post-stage circuit. The circuit is simple in structure, low in cost and wide in application range.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, in particular to the field of integrated circuit technology, and specifically refers to an automatic direction recognition circuit applied to a signal chain circuit. Background Art

[0002] With the development of radio technology, various signal chain products are becoming more and more common. When these signal chain products are facing bidirectional transmission, if there is no fast direction recognition control unit, the input and output I / O ports will inevitably compete with each other. Therefore, we need to quickly identify the direction of the I / O ports on both sides to confirm the driving port and the driven port. Therefore, it is necessary to study a circuit solution for automatic direction recognition suitable for signal chain circuits. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide an automatic direction recognition circuit for use in a signal chain circuit, which can quickly identify the direction of a driving port and a driven port.

[0004] In order to achieve the above-mentioned purpose, the automatic direction identification circuit applied to the signal chain circuit of the present invention has the following structure:

[0005] It includes: an accelerated pull-up I / O module, a rising edge detection module, a one-shot pulse (ONESHOT pulse) module, and a falling edge detection and direction control module;

[0006] The accelerated pull-up I / O module includes an I / O port A and an I / O port B connected to two ends of the signal chain circuit.

[0007] The I / O port A is connected to the I / O port B via the A-end rising edge detection module and the one-shot pulse module, and the I / O port B is connected to the I / O port A via the B-end rising edge detection module and the one-shot pulse module;

[0008] The output ends of the A-end rising edge detection module and the B-end rising edge detection module are both connected to the falling edge detection and direction control module, and the output ends of the falling edge detection and direction control module are respectively connected to the I / O port A and the I / O port B;

[0009] The falling edge detection and direction control module detects the accelerated pull-up I / O module through the rising edge detection module to determine the signal at one end of the I / O port A and the I / O port B as a driving circuit, and uses the single-trigger pulse module and the falling edge detection and direction control module to control the other end to give a corresponding output signal.

[0010] This is applied to the automatic direction identification circuit of the signal chain circuit.

[0011] The I / O port A is simultaneously connected to the lower end of the resistor R2, the drain end of the NMOS tube N2, the drain end of the PMOS tube P2 and the input end of the A-end rising edge detection module M2;

[0012] The output end of the A-end rising edge detection module M2 is connected to the input end of the single-trigger pulse module M3 and the a1 input end of the falling edge detection and direction control module M1;

[0013] The gate terminal of the NMOS tube N2 is connected to the b2 output terminal of the falling edge detection and direction control module M1; the source terminal of the NMOS tube N2 is grounded;

[0014] The upper end of the resistor R2 is connected to the power supply VDD1 and the source end of the PMOS tube P2;

[0015] The gate terminal of the PMOS tube P2 is connected to the output terminal of the single-trigger pulse module M5;

[0016] The I / O port B is simultaneously connected to the lower end of the resistor R1, the drain end of the NMOS tube N1, the drain end of the PMOS tube P1 and the input end of the B-end rising edge detection module M4;

[0017] The output end of the B-end rising edge detection module M4 is connected to the input end of the single-trigger pulse module M5 and the b1 input end of the falling edge detection and direction control module M1;

[0018] The gate terminal of the NMOS tube N1 is connected to the a2 output terminal of the falling edge detection and direction control module M1; the source terminal of the NMOS tube N2 is grounded;

[0019] The upper end of the resistor R1 is connected to the power supply VDD2 and the source end of the PMOS tube P1;

[0020] The gate end of the PMOS tube P1 is connected to the output end of the single-trigger pulse module M3.

[0021] This is applied to the automatic direction identification circuit of the signal chain circuit.

[0022] The single-shot pulse module includes an inverter (INV) M6, a resistor R4, a buffer M7 and a NAND gate M8 connected in sequence. The output end of the rising edge detection module is respectively connected to the input end of the inverter M6 and one input end of the NAND gate M8, the output end of the buffer M7 is connected to the other input end of the NAND gate M8, and the output end of the NAND gate M8 is connected to the accelerated pull-up I / O module.

[0023] This is applied to the automatic direction identification circuit of the signal chain circuit.

[0024] The falling edge detection and direction control module M1 includes a selection circuit (SEL) M10 and a selection circuit (SEL) M15;

[0025] The a1 input terminal of the falling edge detection and direction control module M1 is connected to the input terminal of the OR gate M16 and the input terminal of the NOR gate M18;

[0026] The output end of the OR gate M16 is connected to the input end of the NAND gate M17 and the C input end of the selection circuit M15; the other input end of the OR gate M16 is connected to the Z output end of the selection circuit M15;

[0027] The other input end of the NAND gate M17 is connected to the output end of the inverter M14; the output end of the NAND gate M17 is connected to the other input end of the NOR gate M18;

[0028] The D input terminal of the selection circuit M15 is connected to GND; the SEL selection terminal of the selection circuit M15 is connected to the output terminal of the NOR gate M13 and the input terminal of the inverter M14;

[0029] The output end of the NOR gate M18 is the a2 output end of the falling edge detection and direction control module M1;

[0030] The output end of the NOR gate M13 is the b2 output end of the falling edge detection and direction control module M1;

[0031] The b1 input terminal of the falling edge detection and direction control module M1 is connected to the input terminal of the OR gate M11 and the input terminal of the NOR gate M13;

[0032] The output end of the OR gate M11 is connected to the input end of the NAND gate M12 and the C input end of the selection circuit M10; the other input end of the OR gate M11 is connected to the Z output end of the selection circuit M10;

[0033] The other input end of the NAND gate M12 is connected to the output end of the inverter M9; the output end of the NAND gate M12 is connected to the other input end of the NOR gate M13;

[0034] The D input terminal of the selection circuit M10 is connected to GND; the SEL selection terminal of the selection circuit M10 is connected to the output terminal of the NOR gate M18 and the input terminal of the inverter M9.

[0035] The invention is used in the automatic direction identification circuit applied to the signal chain circuit, which includes an accelerated pull-up I / O module, a rising edge detection module, a single-trigger pulse module and a falling edge detection and direction control module; the falling edge detection and direction control module detects the accelerated pull-up I / O module through the rising edge detection module to determine the signal at one end of the I / O port A and the I / O port B as the driving circuit, and uses the single-trigger pulse module and the falling edge detection and direction control module to control the other end to give a corresponding output signal. Since the driving direction needs to be determined only when both sides are at a high level, when the rising edge is detected, the accelerated driving output end is pulled high; when the falling edge is detected, the control right of the signal on the other side is given; when there is no input signal at both ends, the levels on both sides need to be pulled high to prevent misjudgment of the subsequent circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic block diagram of the structure of a direction automatic identification circuit applied to a signal chain circuit of the present invention;

[0037] Figure 2 A specific circuit diagram of a direction automatic identification circuit applied to a signal chain circuit of the present invention;

[0038] Figure 3 It is a structural diagram of a single-trigger pulse module;

[0039] Figure 4 It is a structural diagram of the falling edge detection and direction control module;

[0040] Figure 5 A specific circuit diagram of an embodiment of a direction automatic identification circuit applied to a signal chain circuit of the present invention;

[0041] Figure 6 This is a schematic diagram of the I / O port without driver simulation;

[0042] Figure 7 This is a simulation diagram of the I / O port transmission direction from A to B;

[0043] Figure 8 This is a simulation diagram of the I / O port transmission direction being B to A. DETAILED DESCRIPTION

[0044] In order to more clearly understand the technical content of the present invention, the following embodiments are given in detail.

[0045] See also Figure 1 FIG. 1 is a schematic block diagram of the structure of an automatic direction identification circuit applied to a signal chain circuit of the present invention.

[0046] In one embodiment, the automatic direction identification circuit applied to the signal chain circuit is as follows: Figure 1 and Figure 2 As shown, it includes: an accelerated pull-up I / O module, a rising edge detection module, a single-trigger pulse module, and a falling edge detection and direction control module;

[0047] The accelerated pull-up I / O module includes an I / O port A and an I / O port B connected to two ends of the signal chain circuit.

[0048] The I / O port A is connected to the I / O port B via the A-end rising edge detection module and the one-shot pulse module, and the I / O port B is connected to the I / O port A via the B-end rising edge detection module and the one-shot pulse module;

[0049] The output ends of the A-end rising edge detection module and the B-end rising edge detection module are both connected to the falling edge detection and direction control module, and the output ends of the falling edge detection and direction control module are respectively connected to the I / O port A and the I / O port B;

[0050] The falling edge detection and direction control module detects the accelerated pull-up I / O module through the rising edge detection module to determine the signal at one end of the I / O port A and the I / O port B as a driving circuit, and uses the single-trigger pulse module and the falling edge detection and direction control module to control the other end to give a corresponding output signal.

[0051] Among them, Figure 2 As shown, the I / O port A is simultaneously connected to the lower end of the resistor R2, the drain end of the NMOS tube N2, the drain end of the PMOS tube P2 and the input end of the A-end rising edge detection module M2;

[0052] The output end of the A-end rising edge detection module M2 is connected to the input end of the single-trigger pulse module M3 and the a1 input end of the falling edge detection and direction control module M1;

[0053] The gate terminal of the NMOS tube N2 is connected to the b2 output terminal of the falling edge detection and direction control module M1; the source terminal of the NMOS tube N2 is grounded;

[0054] The upper end of the resistor R2 is connected to the power supply VDD1 and the source end of the PMOS tube P2;

[0055] The gate terminal of the PMOS tube P2 is connected to the output terminal of the single-trigger pulse module M5;

[0056] The I / O port B is simultaneously connected to the lower end of the resistor R1, the drain end of the NMOS tube N1, the drain end of the PMOS tube P1 and the input end of the B-end rising edge detection module M4;

[0057] The output end of the B-end rising edge detection module M4 is connected to the input end of the single-trigger pulse module M5 and the b1 input end of the falling edge detection and direction control module M1;

[0058] The gate terminal of the NMOS tube N1 is connected to the a2 output terminal of the falling edge detection and direction control module M1; the source terminal of the NMOS tube N2 is grounded;

[0059] The upper end of the resistor R1 is connected to the power supply VDD2 and the source end of the PMOS tube P1;

[0060] The gate end of the PMOS tube P1 is connected to the output end of the single-trigger pulse module M3.

[0061] The single trigger pulse module is as follows Figure 3 As shown, it includes an inverter M6, a resistor R4, a buffer M7 and a NAND gate M8 connected in sequence, the output end of the rising edge detection module is respectively connected to the input end of the inverter M6 and one input end of the NAND gate M8, the output end of the buffer M7 is connected to the other input end of the NAND gate M8, and the output end of the NAND gate M8 is connected to the gate end of the PMOS tube P1 in the accelerated pull-up I / O module. One end of the resistor R4 connected to the buffer M7 is also connected to the upper end of the capacitor C2, and the lower end of the capacitor C2 is connected to GND.

[0062] like Figure 5 As shown, the one-shot pulse module on the other side includes an inverter M25, a resistor R3, a buffer M23 and a NAND gate M21 connected in sequence, and also includes a capacitor C1. The circuit structure of the one-shot pulse module is the same as the above-mentioned one-shot pulse module.

[0063] In a preferred embodiment, Figure 4 and Figure 5 As shown, the falling edge detection and direction control module M1 includes a selection circuit M10 and a selection circuit M15;

[0064] The a1 input terminal of the falling edge detection and direction control module M1 is connected to the input terminal of the OR gate M16 and the input terminal of the NOR gate M18;

[0065] The output end of the OR gate M16 is connected to the input end of the NAND gate M17 and the C input end of the selection circuit M15; the other input end of the OR gate M16 is connected to the Z output end of the selection circuit M15;

[0066] The other input end of the NAND gate M17 is connected to the output end of the inverter M14; the output end of the NAND gate M17 is connected to the other input end of the NOR gate M18;

[0067] The D input terminal of the selection circuit M15 is connected to GND; the SEL selection terminal of the selection circuit M15 is connected to the output terminal of the NOR gate M13 and the input terminal of the inverter M14;

[0068] The output end of the NOR gate M18 is the a2 output end of the falling edge detection and direction control module M1;

[0069] The output end of the NOR gate M13 is the b2 output end of the falling edge detection and direction control module M1;

[0070] The b1 input terminal of the falling edge detection and direction control module M1 is connected to the input terminal of the OR gate M11 and the input terminal of the NOR gate M13;

[0071] The output end of the OR gate M11 is connected to the input end of the NAND gate M12 and the C input end of the selection circuit M10; the other input end of the OR gate M11 is connected to the Z output end of the selection circuit M10;

[0072] The other input end of the NAND gate M12 is connected to the output end of the inverter M9; the output end of the NAND gate M12 is connected to the other input end of the NOR gate M13;

[0073] The D input terminal of the selection circuit M10 is connected to GND; the SEL selection terminal of the selection circuit M10 is connected to the output terminal of the NOR gate M18 and the input terminal of the inverter M9.

[0074] Figure 5 The OR gate, NAND gate, NOR gate and selection circuit described in the invention may adopt other logic gates realizing similar logic functions.

[0075] In the application of the present invention, Figure 5 As shown, the rising edge detection module and the falling edge detection and direction control module detect the accelerated pull-up I / O module, determine that one side of the signal is used as the driving circuit, and at the same time drive the accelerated pull-up I / O module on the other side to make a corresponding signal output through the single-shot pulse module and the falling edge detection and direction control module; because only when both sides are at a high level does it need to determine the driving direction. Therefore, when the rising edge is detected, the accelerated drive output end is pulled high. When the falling edge is detected, the control right of the signal on the other side is granted. When there is no input signal at both ends, the levels on both sides need to be pulled high to prevent misjudgment of the subsequent circuit.

[0076] like Figure 6 As shown in the simulation results, when there is no input signal at both ends of the I / O, the levels on both sides need to be pulled high to prevent misjudgment by the subsequent circuit.

[0077] like Figure 7As shown in the simulation results, when the signal is transmitted from I / O port A to I / O port B, the falling edge detection and direction control module receives signals from the a1 input terminal and the b1 input terminal respectively, and detects that when a falling edge signal appears at port A, it pulls the a2 output terminal signal high and controls I / O port B to pull low, that is, the b1 input terminal is passively pulled low, and the b2 output terminal signal has no response;

[0078] like Figure 8 As shown in the simulation results, when the signal is transmitted from I / O port B to I / O port A, the falling edge detection and direction control module receives signals from the a1 input terminal and the b1 input terminal respectively, and detects that when a falling edge signal appears on port B, the b2 output terminal signal is pulled high and the I / O port A is controlled to be pulled low, that is, the a1 input terminal is passively pulled low, and the a2 output terminal signal has no response.

[0079] The invention is used in the automatic direction identification circuit applied to the signal chain circuit, which includes an accelerated pull-up I / O module, a rising edge detection module, a single-trigger pulse module and a falling edge detection and direction control module; the falling edge detection and direction control module detects the accelerated pull-up I / O module through the rising edge detection module to determine the signal at one end of the I / O port A and the I / O port B as the driving circuit, and uses the single-trigger pulse module and the falling edge detection and direction control module to control the other end to give a corresponding output signal. Since the driving direction needs to be determined only when both sides are at a high level, when the rising edge is detected, the accelerated driving output end is pulled high; when the falling edge is detected, the control right of the signal on the other side is given; when there is no input signal at both ends, the levels on both sides need to be pulled high to prevent misjudgment of the subsequent circuit.

[0080] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A direction automatic identification circuit applied to a signal chain circuit, characterized in that: include: Accelerated pull-up I / O module, rising edge detection module, one-shot pulse module, and falling edge detection and direction control module; The accelerated pull-up I / O module includes an I / O port A and an I / O port B connected to two ends of the signal chain circuit. The I / O port A is connected to the I / O port B via the A-end rising edge detection module and the one-shot pulse module, and the I / O port B is connected to the I / O port A via the B-end rising edge detection module and the one-shot pulse module; The output ends of the A-end rising edge detection module and the B-end rising edge detection module are both connected to the falling edge detection and direction control module, and the output ends of the falling edge detection and direction control module are respectively connected to the I / O port A and the I / O port B; The falling edge detection and direction control module detects the accelerated pull-up I / O module through the rising edge detection module to determine the signal at one end of the I / O port A and the I / O port B as a driving circuit, and uses the single-trigger pulse module and the falling edge detection and direction control module to control the other end to give a corresponding output signal.

2. The automatic direction identification circuit applied to a signal chain circuit according to claim 1, characterized in that: The I / O port A is simultaneously connected to the lower end of the resistor R2, the drain end of the NMOS tube N2, the drain end of the PMOS tube P2 and the input end of the A-end rising edge detection module M2; The output end of the A-end rising edge detection module M2 is connected to the input end of the single-trigger pulse module M3 and the a1 input end of the falling edge detection and direction control module M1; The gate terminal of the NMOS tube N2 is connected to the b2 output terminal of the falling edge detection and direction control module M1; the source terminal of the NMOS tube N2 is grounded; The upper end of the resistor R2 is connected to the power supply VDD1 and the source end of the PMOS tube P2; The gate terminal of the PMOS tube P2 is connected to the output terminal of the single-trigger pulse module M5; The I / O port B is simultaneously connected to the lower end of the resistor R1, the drain end of the NMOS tube N1, the drain end of the PMOS tube P1 and the input end of the B-end rising edge detection module M4; The output end of the B-end rising edge detection module M4 is connected to the input end of the single-trigger pulse module M5 and the b1 input end of the falling edge detection and direction control module M1; The gate terminal of the NMOS tube N1 is connected to the a2 output terminal of the falling edge detection and direction control module M1; the source terminal of the NMOS tube N2 is grounded; The upper end of the resistor R1 is connected to the power supply VDD2 and the source end of the PMOS tube P1; The gate end of the PMOS tube P1 is connected to the output end of the single-trigger pulse module M3.

3. The automatic direction identification circuit applied to a signal chain circuit according to claim 2, characterized in that: The single-shot pulse module includes an inverter M6, a resistor R4, a buffer M7 and a NAND gate M8 connected in sequence. The output end of the rising edge detection module is respectively connected to the input end of the inverter M6 and one input end of the NAND gate M8, the output end of the buffer M7 is connected to the other input end of the NAND gate M8, and the output end of the NAND gate M8 is connected to the accelerated pull-up I / O module.

4. The automatic direction identification circuit applied to a signal chain circuit according to claim 3, characterized in that: The falling edge detection and direction control module M1 includes a selection circuit M10 and a selection circuit M15; The a1 input terminal of the falling edge detection and direction control module M1 is connected to the input terminal of the OR gate M16 and the input terminal of the NOR gate M18; The output end of the OR gate M16 is connected to the input end of the NAND gate M17 and the C input end of the selection circuit M15; the other input end of the OR gate M16 is connected to the Z output end of the selection circuit M15; The other input end of the NAND gate M17 is connected to the output end of the inverter M14; the output end of the NAND gate M17 is connected to the other input end of the NOR gate M18; The D input terminal of the selection circuit M15 is connected to GND; the SEL selection terminal of the selection circuit M15 is connected to the output terminal of the NOR gate M13 and the input terminal of the inverter M14; The output end of the NOR gate M18 is the a2 output end of the falling edge detection and direction control module M1; The output end of the NOR gate M13 is the b2 output end of the falling edge detection and direction control module M1; The b1 input terminal of the falling edge detection and direction control module M1 is connected to the input terminal of the OR gate M11 and the input terminal of the NOR gate M13; The output end of the OR gate M11 is connected to the input end of the NAND gate M12 and the C input end of the selection circuit M10; the other input end of the OR gate M11 is connected to the Z output end of the selection circuit M10; The other input end of the NAND gate M12 is connected to the output end of the inverter M9; the output end of the NAND gate M12 is connected to the other input end of the NOR gate M13; The D input terminal of the selection circuit M10 is connected to GND; the SEL selection terminal of the selection circuit M10 is connected to the output terminal of the NOR gate M18 and the input terminal of the inverter M9.

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