A low-power integrator for continuous-time ΔΣ analog-to-digital converters

Abstract

This disclosure relates to a low-power integrator for a continuous-time ΔΣ analog-to-digital converter (ADC). The integrator includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, an operational transconductance amplifier, a first capacitor, a second capacitor, and a third capacitor. In this embodiment, the integrator controls the opening and closing of the first to eighth switches to alternately utilize either the first or second capacitor. The integrated charge accumulated by the input current over a certain time period is directly "poured" onto the third capacitor of the integrator. Integration is achieved through charge sharing between the first or second capacitor and the third capacitor. This eliminates the need for the operational transconductance amplifier to provide a large current to charge the integrating capacitor, reducing the requirement for high-performance active devices and lowering the integrator's power consumption, thereby contributing to a reduction in the power consumption of the continuous-time ΔΣ ADC.

Description

Technical Field

[0001] This disclosure relates to the field of electronic technology, and more particularly to a low-power integrator for a continuous-time ΔΣ analog-to-digital converter. Background Technology

[0002] Continuous-Time Delta-Sigma Analog-to-Digital Converters (CTΔΣADCs) are easy to drive, consume less power than Discrete-Time Delta-Sigma Analog-to-Digital Converters (DTΔΣADCs), and have built-in anti-aliasing capabilities. Therefore, wideband continuous-time ΔΣ ADCs are widely used in communication systems. Figure 1 The following are circuit diagrams of two commonly used integrators for continuous-time ΔΣ analog-to-digital converters in related technologies: Figure 1 As shown, the left side is an active RC integrator, and the right side is a G... m -C integrator, where V IN V represents the input voltage of the integrator. OUT R represents the input voltage of the integrator. INT Indicates the input resistance, C INT OTA represents the integrating capacitor, and OTA represents the active device of the integrator, the operational transconductance amplifier (OTA). m This refers to the transconductance of the operational transconductance amplifier OTA. Integrators in related technologies rely on an active device, the operational transconductance amplifier OTA, to perform integration, with the OTA providing current to the integrating capacitor C. INT Charging and integration of the operational transconductance amplifier OTA requires high power consumption, especially when the input of the operational transconductance amplifier OTA is a wideband signal. Summary of the Invention

[0003] In view of this, this disclosure proposes a low-power integrator for a continuous-time ΔΣ analog-to-digital converter.

[0004] According to one aspect of this disclosure, an integrator is provided, the integrator comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, an operational transconductance amplifier, a first capacitor, a second capacitor, and a third capacitor, wherein a first terminal of the first switch is connected to a first terminal of the seventh switch as an input terminal of the integrator for receiving input current; a second terminal of the first switch and a first terminal of the fifth switch are connected to a first terminal of the first capacitor; a second terminal of the first capacitor and a first terminal of the sixth switch are connected to a first terminal of the second switch; the second terminal of the second switch is used to receive a first voltage; and the sixth switch... The second terminal of the switch, the first terminal of the third capacitor, and the first terminal of the fourth switch are connected to the inverting input terminal of the operational transconductance amplifier. The non-inverting input terminal of the operational transconductance amplifier is connected to the input common-mode voltage. The second terminal of the third capacitor, the second terminal of the fifth switch, and the first terminal of the third switch are connected to the non-inverting output terminal of the operational transconductance amplifier as the output terminal of the integrator to provide the output voltage. The second terminal of the third switch and the second terminal of the seventh switch are connected to the first terminal of the second capacitor. The second terminal of the second capacitor and the second terminal of the fourth switch are connected to the first terminal of the eighth switch. The second terminal of the eighth switch is used to receive the second voltage.

[0005] In one possible implementation, the first switch, the second switch, the third switch, and the fourth switch receive a first switch control signal. In response to the first switch control signal being at a first level, the first switch, the second switch, the third switch, and the fourth switch are closed; in response to the first switch control signal being at a second level, the first switch, the second switch, the third switch, and the fourth switch are open. The fifth switch, the sixth switch, the seventh switch, and the eighth switch receive a second switch control signal. In response to the second switch control signal being at a first level, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are closed; in response to the second switch control signal being at a second level, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are open; wherein the first switch control signal and the second switch control signal are non-overlapping signals.

[0006] In one possible implementation, in response to the first switch control signal changing from a first level to a second level and the second switch control signal changing from a second level to a first level, the first capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value. The charge accumulated in the first capacitor and the charge on the third capacitor together constitute the charge of the integrating capacitor (that is, the charge accumulated in the first capacitor and the existing charge on the third capacitor together constitute the charge that the integrating capacitor should have when the second switch control signal changes from a second level to a first level). The charge carried by the input current of the integrator begins to accumulate on the second capacitor. In response to the first switch control signal changing from a second level to a first level and the second switch control signal changing from a first level to a second level, the second capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value. The charge accumulated in the second capacitor and the charge on the third capacitor together constitute the charge of the integrating capacitor (that is, the charge accumulated in the second capacitor and the existing charge on the third capacitor together constitute the charge that the integrating capacitor should have when the first switch control signal changes from a second level to a first level). The charge carried by the input current of the integrator begins to accumulate on the first capacitor.

[0007] In one possible implementation, the integrator further includes a compensation circuit for compensating for a portion of the integrated charge carried away when the parallel connection between the first capacitor or the second capacitor and the third capacitor is broken. The compensation circuit includes a first sample-and-hold circuit, a second sample-and-hold circuit, and the operational transconductance amplifier. The inverting output of the operational transconductance amplifier is connected to the input of the first sample-and-hold circuit and the input of the second sample-and-hold circuit. The output of the first sample-and-hold circuit is connected to the second terminal of the second switch to provide the first voltage, and the output of the second sample-and-hold circuit is connected to the second terminal of the eighth switch to provide the second voltage.

[0008] In one possible implementation, each sample-and-hold circuit includes a sampling switch, a sample-and-hold capacitor, and a voltage buffer. The first terminal of the sampling switch serves as the input terminal of the sample-and-hold circuit. The second terminal of the sampling switch and the first terminal of the sample-and-hold capacitor are connected to the input terminal of the voltage buffer. The second terminal of the sample-and-hold capacitor is connected to the output common-mode voltage of the operational transconductance amplifier. The output terminal of the voltage buffer serves as the output terminal of the sample-and-hold circuit.

[0009] In one possible implementation, in response to the first switch control signal changing from a first level to a second level and the second switch control signal changing from a second level to a first level, the first capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value. The charge accumulated in the first capacitor and the charge on the third capacitor together constitute the charge of the integrating capacitor (that is, the charge that the integrating capacitor should have when the second switch control signal changes from a second level to a first level). The parallel connection between the second capacitor and the third capacitor is disconnected, carrying away a portion of the integrated charge. The charge carried by the input current of the integrator and the charge loss compensated by the second voltage output by the second sample-and-hold circuit begin to accumulate in the integrated capacitor. The second capacitor is connected in parallel with the third capacitor to form an integrating capacitor with a total capacitance value of a preset value. The charge accumulated in the second capacitor and the charge on the third capacitor together constitute the charge of the integrating capacitor (that is, the amount of charge that the integrating capacitor should have when the first switch control signal changes from the second level to the first level). The first capacitor and the third capacitor are disconnected from each other and take away part of the integrated charge. The charge carried by the input current of the integrator and the loss charge compensated by the first voltage output by the first sample-and-hold circuit begin to accumulate in the first capacitor.

[0010] In one possible implementation, the charge accumulated in the first capacitor includes the charge accumulated from the input current and the partial integrated charge carried away by the second capacitor when the second switch control signal changes from the first level to the second level half a sampling clock cycle ago; the charge accumulated in the second capacitor includes the charge accumulated from the input current and the partial integrated charge carried away by the first capacitor when the first switch control signal changes from the first level to the second level half a sampling clock cycle ago.

[0011] In one possible implementation, the first voltage and the second voltage are the input common-mode voltage (signal ground) of the operational transconductance amplifier.

[0012] According to one aspect of this disclosure, an analog-to-digital converter (ADC) is provided, comprising a first resistor, a first current buffer, a second current buffer, a digital-to-analog converter (DAC), a quantizer, and an integrator as described above. A first terminal of the first resistor is used to receive an analog voltage. A second terminal of the first resistor is connected to the input terminal of the first current buffer. The output terminal of the first current buffer is connected to the input terminal of the integrator and the output terminal of the second current buffer. The output terminal of the integrator is connected to the input terminal of the quantizer. The quantizer outputs the digital output of the ADC. Simultaneously, the output terminal of the quantizer is connected to the control terminal of the DAC, and the output terminal of the DAC is connected to the input terminal of the second current buffer.

[0013] According to one aspect of this disclosure, an electronic device is provided that includes an integrator as described above.

[0014] The integrator of this embodiment can achieve the following: by controlling the opening and closing of the first to eighth switches, the integrated charge accumulated by the input current over a certain period of time can be directly "poured" onto the third capacitor of the integrator using either the first or second capacitor in turn. Integration is achieved through the charge sharing between the first or second capacitor and the third capacitor. This eliminates the need for a large current from the operational transconductance amplifier to charge the integrating capacitor, reducing the demand for high-performance (i.e., high-speed, high-gain) active devices and lowering the power consumption of the integrator. This, in turn, helps to reduce the power consumption of the continuous-time ΔΣ analog-to-digital converter.

[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0017] Figure 1 A circuit diagram of an integrator for a continuous-time ΔΣ analog-to-digital converter is shown in the related art.

[0018] Figure 2 A circuit diagram of an integrator according to an embodiment of the present disclosure is shown.

[0019] Figure 3 A circuit diagram of an integrator with a compensation circuit according to an embodiment of the present disclosure is shown.

[0020] Figure 4A schematic diagram of a sample-and-hold circuit for compensation according to an embodiment of the present disclosure is shown.

[0021] Figure 5 A circuit diagram of an integrator without compensation circuitry according to an embodiment of the present disclosure is shown.

[0022] Figure 6 A circuit diagram is shown for a continuous-time ΔΣ analog-to-digital converter using an integrator proposed in this disclosure, according to an embodiment of the present disclosure.

[0023] Figure 7 A schematic diagram of a timing generation circuit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0024] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0025] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0026] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0028] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0029] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0030] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0031] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0032] Figure 2 A circuit diagram of an integrator according to an embodiment of the present disclosure is shown, as follows: Figure 2 As shown, the integrator includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, an operational transconductance amplifier OTA, and a first capacitor C. ACC,A Second capacitor C ACC,B Third capacitor C FIX Wherein, the first terminal of the first switch S1 is connected to the first terminal of the seventh switch S7 as the input terminal of the integrator for receiving the input current I.IN The second terminal of the first switch S1, the first terminal of the fifth switch S5, and the first capacitor C ACC,A The first terminal is connected, and the first capacitor C ACC,A The second terminal of the sixth switch S6 is connected to the first terminal of the second switch S2, and the second terminal of the second switch S2 is used to receive the first voltage V. S,A The second terminal of the sixth switch S6 and the third capacitor C FIX The first terminal of the fourth switch S4 is connected to the inverting input terminal of the operational transconductance amplifier OTA, and the non-inverting input terminal of the operational transconductance amplifier OTA is connected to the input common-mode voltage (also known as signal ground). The third capacitor C FIX The second terminal of the fifth switch S5, the second terminal of the third switch S3, and the first terminal of the third switch S3 are connected to the non-inverting output terminal of the operational transconductance amplifier OTA as the output terminal of the integrator to provide the output voltage V. OUT The second terminal of the third switch S3, the second terminal of the seventh switch S7, and the second capacitor C ACC,B The first terminal is connected, and the second capacitor C ACC,B The second terminal of the fourth switch S4 is connected to the first terminal of the eighth switch S8, and the second terminal of the eighth switch S8 is used to receive the second voltage V. S,B .

[0033] The integrator of this embodiment can achieve the following: by controlling the opening and closing of the first to eighth switches, the integrated charge accumulated by the input current over a certain period of time can be directly "poured" onto the third capacitor of the integrator using either the first or second capacitor in turn. Integration is achieved through the charge sharing between the first or second capacitor and the third capacitor. This eliminates the need for a large current from the operational transconductance amplifier to charge the integrating capacitor, reducing the demand for high-performance (i.e., high-speed, high-gain) active devices and lowering the power consumption of the integrator. This, in turn, helps to reduce the power consumption of the continuous-time ΔΣ analog-to-digital converter.

[0034] In one possible implementation, the integrator can be at least one of a transistor-level integrated circuit and a printed circuit board. This disclosure does not limit the implementation of the integrator.

[0035] In one possible implementation, the integrator can be applied to a continuous-time delta-Sigma analog-to-digital converter (CTΔΣADC) to integrate an unknown analog signal so that it can be converted into a digitally represented signal with low quantization noise in conjunction with a quantizer and a feedback digital-to-analog converter.

[0036] In one possible implementation, the operational transconductance amplifier OTA of the integrator is a fully differential operational transconductance amplifier.

[0037] In one possible implementation, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 can be either N-channel metal-oxide-semiconductor (MOSFETs) or P-channel MOSFETs. Since the switching speed of N-channel MOSFETs is higher than that of P-channel MOSFETs, N-channel MOSFETs are preferred. The control terminal of these switching transistors is the gate; the first terminal can be the source, and the second terminal can be the drain; alternatively, the first terminal can be the drain, and the second terminal can be the source, without specific distinction here. Furthermore, in a specific implementation, the N-channel switch is turned on under a high-level signal and turned off under a low-level signal. The P-channel switch is turned off under a high-level signal and turned on under a low-level signal. It should be understood that high-level signals and low-level signals are logic levels, which are only used to better explain the specific working process of the embodiments of this disclosure. This disclosure does not limit the voltage applied to the gate of each transistor during specific implementation.

[0038] In one possible implementation, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 receive a first switch control signal Φ1. In response to the first switch control signal Φ1 being at a first level (e.g., a high level), the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are closed. In response to the first switch control signal Φ1 being at a second level (e.g., a low level), the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are open.

[0039] The fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 receive the second switch control signal Φ2. In response to the second switch control signal Φ2 being at a first level (e.g., a high level), the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 close. In response to the second switch control signal Φ2 being at a second level (e.g., a low level), the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 open.

[0040] The first switch control signal Φ1 and the second switch control signal Φ2 are non-overlapping signals. The first switch control signal Φ1 and the second switch control signal Φ2 will not be at the same first level (e.g., high level) at the same time, thereby avoiding potential conflicts or short circuits between the switches and improving the stability and safety of the integrator circuit.

[0041] By setting non-overlapping first switch control signal Φ1 and second switch control signal Φ2, this disclosure sets the switching operation to a "ping-pong" working mode, that is, two-way time interleaving, thereby reducing aliasing caused by switching operations in the early stage of the loop filter. Thus, without affecting the anti-aliasing function of the continuous-time ΔΣ analog-to-digital converter, the power consumption of the integrator in the continuous-time ΔΣ analog-to-digital converter is reduced by using the technology proposed in this disclosure.

[0042] In one possible implementation, in response to the first switch control signal Φ1 changing from a first level to a second level and the second switch control signal Φ2 changing from a second level to a first level, the first capacitor C... ACC,A With the third capacitor C FIX The total capacitance formed by parallel connection is a preset value C. INT The integrating capacitor, the first capacitor C ACC,A The accumulated charge and the third capacitor C FIX The existing charge on the capacitor constitutes the charge that should exist on the equivalent integral capacitor when the second switch control signal Φ2 changes from the second level to the first level. Here, the capacitance value of the equivalent integral capacitor is C. INT The input current I of the integrator IN The charge begins to accumulate in the second capacitor C. ACC,B superior;

[0043] In response to the first switch control signal Φ1 changing from the second level to the first level and the second switch control signal Φ2 changing from the first level to the second level, the second capacitor C ACC,B With the third capacitor C FIX The total capacitance formed by parallel connection is a preset value C. INT The integrating capacitor, the second capacitor C ACC,B The accumulated charge and the third capacitor C FIX The existing charge on the capacitor constitutes the charge that should exist on the equivalent integral capacitor when the first switch control signal Φ1 changes from the second level to the first level. Here, the capacitance value of the equivalent integral capacitor is C. INT The input current I of the integrator IN The charge begins to accumulate in the first capacitor C ACC,A .

[0044] In this way, the input current I from the integrator can be... IN The accumulated integrated charge is directly "dumped" into the third capacitor C of the integrator. FIX Above, through the first capacitor C ACC,A Or the second capacitor C ACC,B The integration of the input signal is achieved by sharing the charge with the third capacitor, a process that does not require the participation of an active device, the operational transconductance amplifier (OTA). To avoid aliasing caused by switching operations during this process, the "charge dumping" operation is performed in a "ping-pong" manner. Therefore, this integrator reduces the power consumption of the integrator in a continuous-time ΔΣ analog-to-digital converter (RTD) while maintaining the anti-aliasing function of the RTD.

[0045] like Figure 2 As shown, I IN The input current of the integrator is represented by OTA, which represents the fully differential operational transconductance amplifier. Gm is the transconductance of the operational transconductance amplifier OTA, and the first capacitor C is... ACC,A Second capacitor C ACC,B Used to accommodate input current I IN The charge accumulated within 0.5 sampling clock cycles has the same capacitance value, i.e.: C ACC,A =C ACC,B C INT V represents the value of the integrating capacitor in the integrator. OUT The output voltage of the integrator is represented by the first switch control signal Φ1 and the second switch control signal Φ2, which are non-overlapping clocks with a period equal to the continuous time ΔΣ, which is the sampling clock period T of the analog-to-digital converter. S C ACC,A / B Indicates the first capacitor C ACC,A Second capacitor C ACC,B The capacitance value, V S,A Represents the first voltage, V S,B This indicates the second voltage.

[0046] Optionally, the specific operation process of this integrator is as follows:

[0047] When the first switch control signal Φ1 is at the first level (e.g., high level) and the second switch control signal Φ2 is at the second level (e.g., low level), the input current I... IN Accumulated in the first capacitor C ACC,A Above, at the same time, the second capacitor C ACC,B With the third capacitor C FIX Connected in parallel, the total capacitance is the preset value C. INT Integrating capacitor;

[0048] When the first switch control signal Φ1 changes from a first level (e.g., high level) to a second level (e.g., low level) and the second switch control signal Φ2 changes from a second level (e.g., low level) to a first level (e.g., high level), the first capacitor C... ACC,A With the third capacitor C FIX The capacitor formed by the parallel connection of the products has a preset value C. INT The integrating capacitor, this parallel operation makes the input current I IN In the 0.5 clock cycles prior to the current moment, the accumulated capacitance C ACC,A The charge on the capacitor is "poured" into the third capacitor C. FIX Above, the integrator completed the input current I... IN The integration over 0.5 clock cycles, simultaneously, the second capacitor C ACC,B Repeat the first capacitor C ACC,A The operation during the period when the first switch control signal Φ1 is at the first level (e.g., high level), that is: the operation of the input current I IN Second capacitor C ACC,B Accumulate on top.

[0049] When the first switch control signal Φ1 changes from a second level (e.g., low level) to a first level (e.g., high level) and the second switch control signal Φ2 changes from a first level (e.g., high level) to a second level (e.g., low level), the input current I... IN The result obtained by integration over 0.5 clock cycles is deposited into the second capacitor C. ACC,B The charge on the capacitor is poured into the third capacitor C. FIX Above, the integrator completes the input current I... IN The integration over the second 0.5 clock cycles completes, at this point, the input current I... IN The integration is completed within one sampling clock cycle. Afterward, the above steps are repeated sequentially.

[0050] In this way, the first capacitor C ACC,A Second capacitor C ACC,B It participates in two operations in a "ping-pong" manner, namely: for the input current I IN The accumulation of, and the impact on the input current I within 0.5 clock cycles. IN The accumulated charge is poured into the third capacitor C. FIX This ensures that the switching operations in this integrator do not introduce aliasing, which helps to preserve the anti-aliasing advantages of continuous-time ΔΣ analog-to-digital converters.

[0051] In the integrator disclosed herein, the operational transconductance amplifier OTA does not participate in the input current I. IN In the integrating capacitor (e.g., by the first capacitor C) ACC,A With the third capacitor C FIXAn integrating capacitor connected in parallel, or a second capacitor C ACC,B With the third capacitor C FIX The integral over the parallel-connected integrating capacitors (i.e., the operational transconductance amplifier OTA does not need to be integrated as in...) Figure 1 The integrating capacitor C is used in traditional integrators. INT Instead of providing current to aid its integration, it does so through the first capacitor C. ACC,A (or the second capacitor C) ACC,B ) and the third capacitor C FIX This is achieved through passive charge sharing between them. The operational transconductance amplifier OTA only participates in compensating the first capacitor C. ACC,A (or the second capacitor C) ACC,B ) and the third capacitor C FIX The integrated charge carried away when the parallel connection is disconnected; since high precision is not required for compensation, the operational transconductance amplifier OTA in this integrator has low power consumption. Therefore, the integrator of this embodiment effectively reduces the power consumption of active devices in the active integrator of a continuous-time ΔΣ analog-to-digital converter.

[0052] like Figure 2 As shown, when the first capacitor C ACC,A (or the second capacitor C) ACC,B ) and the third capacitor C FIX When the parallel connection is broken, the first capacitor C ACC,A (or the second capacitor C) ACC,B This will take away the third capacitor C. FIX The partial integration charge on the integrator causes integration loss. To compensate for this integration loss, a compensation circuit can be set in the integrator.

[0053] Figure 3 A circuit diagram of an integrator with compensation circuitry according to an embodiment of the present disclosure is shown. Figure 3 As shown, the integrator further includes a compensation circuit, which is used to compensate for the first capacitor C. ACC,A Or the second capacitor C ACC,B With the third capacitor C FIX The partial integrated charge carried away when the parallel connection is broken.

[0054] like Figure 3 As shown, the integrator includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, an operational transconductance amplifier OTA, and a first capacitor C. ACC,A Second capacitor C ACC,B Third capacitor C FIXThe integrator further includes a compensation circuit, which includes a first sample-and-hold circuit A, a second sample-and-hold circuit B, and the operational transconductance amplifier OTA.

[0055] Wherein, the first terminal of the first switch S1 is connected to the first terminal of the seventh switch S7 as the input terminal of the integrator for receiving the input current I. IN The second terminal of the first switch S1, the first terminal of the fifth switch S5, and the first capacitor C ACC,A The first terminal is connected, and the first capacitor C ACC,A The second end of the sixth switch S6 and the first end of the second switch S2 are connected, and the second end of the sixth switch S6 and the third capacitor C are connected. FIX The first terminal of the fourth switch S4 is connected to the inverting input terminal of the operational transconductance amplifier OTA, and the non-inverting input terminal of the operational transconductance amplifier OTA is connected to the input common-mode voltage (also known as signal ground) of the operational transconductance amplifier OTA. The third capacitor C FIX The second terminal, the second terminal of the fifth switch S5, and the first terminal of the third switch S3 are connected to the non-inverting output terminal of the operational transconductance amplifier OTA as the output terminal of the integrator to provide the output voltage V. OUT The inverting output of the operational transconductance amplifier OTA is connected to the input of the first sample-and-hold circuit A and the input of the second sample-and-hold circuit B. The output of the first sample-and-hold circuit A is connected to the second terminal of the second switch S2 to provide the first voltage V. S,A The output terminal of the second sample-and-hold circuit B is connected to the second terminal of the eighth switch S8 to provide the second voltage V. S,B The second terminal of the third switch S3, the second terminal of the seventh switch S7, and the second capacitor C ACC,B The first terminal is connected, and the second capacitor C ACC,B The second end of the fourth switch S4 is connected to the first end of the eighth switch S8.

[0056] In one possible implementation, in response to the first switch control signal Φ1 changing from a first level (e.g., high level) to a second level (e.g., low level) and the second switch control signal Φ2 changing from a second level (e.g., low level) to a first level (e.g., high level), the first capacitor C ACC,A With the third capacitor C FIX The total capacitance formed by parallel connection is a preset value C. INT The integrating capacitor, the first capacitor C ACC,A The accumulated charge and the third capacitor C FIXThe existing charge on the capacitor constitutes the charge that should exist on the equivalent integral capacitor when the second switch control signal Φ2 changes from the second level to the first level. Here, the capacitance value of the equivalent integral capacitor is C. INT The second capacitor C ACC,B With the third capacitor C FIX The parallel connection being disconnected carries away some of the integrated charge, and the input current I of the integrator... IN The charge carried and the second voltage V output by the second sample-and-hold circuit B S,B The replenished lost charge begins to accumulate in the second capacitor C. ACC,B Above; wherein, the first capacitor C ACC,A The accumulated charge includes the charge on the input current I IN The accumulated charge and the second switch control signal Φ2 changing from the first level to the second level half a sampling clock cycle before the second capacitor C ACC,B The portion of the integrated charge that was carried away;

[0057] In response to the first switch control signal Φ1 changing from a second level (e.g., low level) to a first level (e.g., high level) and the second switch control signal Φ2 changing from a first level (e.g., high level) to a second level (e.g., low level), the second capacitor C ACC,B With the third capacitor C FIX The total capacitance formed by parallel connection is a preset value C. INT The integrating capacitor, the second capacitor C ACC,B The accumulated charge and the third capacitor C FIX The existing charge on the capacitor constitutes the charge that should exist on the equivalent integral capacitor when the first switch control signal Φ1 changes from the second level to the first level. Here, the capacitance value of the equivalent integral capacitor is C. INT The first capacitor C ACC,A With the third capacitor C FIX The parallel connection being disconnected carries away some of the integrated charge, and the input current I of the integrator... IN The charge carried and the first voltage V output by the first sample-and-hold circuit A S,A The compensated loss charge begins to accumulate in the first capacitor C. ACC,A ; wherein, the second capacitor C ACC,B The accumulated charge includes the charge on the input current I IN The accumulated charge and the change in the first switch control signal Φ1 from the first level to the second level half a sampling clock cycle before the first capacitor C ACC,A The portion of integrated charge that was taken away.

[0058] The following is based on Figure 3 Taking an example, the compensation technique of this disclosure embodiment will be described. Figure 3The circuits within the upper and lower red boxes together constitute the integrating circuit of this embodiment, and the two operate in a "ping-pong" manner.

[0059] like Figure 3 Taking the circuit within the red box in the upper half as an example, the moment when the second switch control signal Φ2 changes from the first level (e.g., high level) to the second level (e.g., low level) is denoted as t. sw At this time, the output voltage of the integrator is V. OUT (t sw Therefore, the first capacitor C ACC,A The portion of the integrated charge removed from the integrating capacitor is C. ACC,A *V OUT (t sw In order to address the issue of the first capacitor C... ACC,A The portion of the integrated charge carried away is compensated at the falling edge of the second switch control signal Φ2, i.e., at time t. sw The sampling and holding circuit A samples the operational transconductance amplifier OTA at its inverting differential output, i.e.: V OUT,N The voltage obtained by sampling is denoted as V. OUT,N (t sw ), and in the next 0.5 clock cycles, that is: from time t sw Start, until time t sw +0.5T S (Note: T) S (for clock cycles), that is Figure 3 In the timing diagram on the left, during the period when the first switch control signal Φ1 is at the first level (e.g., high level), the... Figure 3 The first capacitor C ACC,A The right electrode is connected to the voltage V OUT,N (t sw Therefore, at time t sw +0.5T S ,Right now: Figure 3 In the timing diagram, when the first switch control signal Φ1 changes from a first level (e.g., high level) to a second level (e.g., low level), and the second switch control signal Φ2 changes from a second level (e.g., low level) to a first level (e.g., high level), the signal accumulates in the first capacitor C. ACC,A The charge on it is: Q ACC =C ACC,A *(V AVE -V OUT,N (t SW )),in, In this calculation formula, the numerator is the value from time t. SW At time t SW +0.5T sThe amount of charge generated by integrating the input current during this period; that is, the amount of charge generated by integrating the input current I during this 0.5 clock cycle. IN The accumulated deposits should be deposited on the integrating capacitor C. INT The charge on it is Q ACC,0 =C ACC,A *V AVE , and in t sw First capacitor C at time ACC,A The portion of the integrated charge carried away from the integrating capacitor is: Q LOSS =C ACC,A *V OUT (t sw ), due to V OUT and V OUT,N For the two differential outputs of the fully differential operational transconductance amplifier OTA, therefore, in terms of the signal, V OUT =-V OUT，N Therefore, Q LOSS =C ACC,A *(-V OUT，N (t sw In order to compensate for t sw First capacitor C at time ACC,A The portion of the integrated charge carried away from the integrating capacitor at time t sw +0.5T S At any given time, the total amount deposited in the integrating capacitor C should be [amount missing]. INT The charge on it is Q TOT =Q ACC,0 +Q LOSS =C ACC,A *V AVE +C ACC,A *(-V OUT，N (t sw ))=C ACC,A *(V AVE -V OUT，N (t sw This charge is also the amount of charge in the first capacitor C. ACC,A The right electrode plate is connected to V OUT，N (t sw Voltage value, over time period [t] sw ,t sw +0.5T S [Inner first capacitor C] ACC,A The total amount of charge accumulated.

[0060] Therefore, using the above compensation method, the first capacitor C ACC,A (or the second capacitor C) ACC,B The input current I can be used to determine the input current I. IN The accumulated charge, and their interaction with the third capacitor C FIXWhen the parallel connection is broken, a portion of the integrated charge carried away is deposited on the integrating capacitor, preventing the first capacitor C from being affected. ACC,A (or the second capacitor C) ACC,B ) and the third capacitor C FIX The integral loss is caused by the removal of some integral charge when the parallel connection ends. Figure 3 The circuit within the red box in the lower half also uses the aforementioned charge compensation method, which will not be elaborated upon here. Among these, due to... Figure 3 The circuit in the upper half of the red box and the circuit in the lower half of the red box use a "ping-pong" operation. The clock control signal of the lower half of the circuit has a 180-degree phase difference with the clock control signal of the upper half of the circuit.

[0061] In one possible implementation, each sample-and-hold circuit includes a sampling switch, a sample-and-hold capacitor, and a voltage buffer. The first terminal of the sampling switch serves as the input terminal of the sample-and-hold circuit. The second terminal of the sampling switch and the first terminal of the sample-and-hold capacitor are connected to the input terminal of the voltage buffer. The second terminal of the sample-and-hold capacitor is connected to the output common-mode voltage (e.g., signal ground) of the operational transconductance amplifier. The output terminal of the voltage buffer serves as the output terminal of the sample-and-hold circuit.

[0062] Figure 4 The diagram shows a sample-and-hold circuit for compensation according to an embodiment of the present disclosure, as shown below. Figure 4 As shown, the first sample-and-hold circuit A includes a sampling switch SW. C,A Sample and hold capacitor C H,A Voltage buffer B A The sampling switch SW C,A The first terminal serves as the input terminal of the first sample-and-hold circuit A, and the sampling switch SW C,A The second terminal, the sample-and-hold capacitor C H,A The first terminal is connected to the voltage buffer B A The input terminal is connected, and the sample-and-hold capacitor C H,A The second terminal is connected to the output common-mode voltage of the operational transconductance amplifier, and the voltage buffer B A The output terminal is used as the output terminal of the first sample-and-hold circuit A.

[0063] The second sample-and-hold circuit B includes a sampling switch SW. C,B Sample and hold capacitor C H,B Voltage buffer B B The sampling switch SW C,B The first terminal serves as the input terminal of the second sample-and-hold circuit B, and the sampling switch SW C,B The second terminal, the sample-and-hold capacitor C H,BThe first terminal is connected to the voltage buffer B B The input terminal is connected, and the sample-and-hold capacitor C H,B The second terminal is connected to the output common-mode voltage of the operational transconductance amplifier, and the voltage buffer B B The output terminal is used as the output terminal of the second sample-and-hold circuit B.

[0064] It should be understood that Figure 4 The sample-and-hold circuit shown is merely one example of an embodiment of this disclosure. It can be used at the falling edge of the second switch control signal Φ2, i.e., at time t. sw The voltage V at the inverting output terminal of the differential output terminal of the operational transconductance amplifier OTA can be used to measure the voltage V at the inverting output terminal. OUT,N Any circuit that performs sample-and-hold operations can be used as sample-and-hold circuit A. It can be used at the falling edge of the first switch control signal Φ1, i.e., at time t. sw +0.5T S The voltage V at the inverting output terminal of the differential output terminal of the operational transconductance amplifier OTA can be used to measure the voltage V at the inverting output terminal. OUT,N Any circuit that performs sampling and holding can be used as sampling and holding circuit B. The embodiments of this disclosure do not limit the specific form of the sampling and holding circuit.

[0065] By setting up a sample-and-hold circuit, the first capacitor C can be... ACC,A (or the second capacitor C) ACC,B ) and the third capacitor C FIX The third capacitor C is taken away when the parallel connection is broken. FIX To compensate for the partial integral charge, the operational transconductance amplifier OTA only needs to compensate for the sample-and-hold capacitor C. H,A Or C H，B Charging is performed for compensation operations, and the accuracy required for these operations is lower than that required for the entire integrator. Therefore, the power consumption of the operational transconductance amplifier (OTA) is much lower than that of the integrator. Figure 1 The power consumption of OTA in a traditional active continuous-time integrator is shown.

[0066] In one possible implementation, when the first capacitor C ACC,A (or the second capacitor C) ACC,B The capacitance value of the integral capacitor is much smaller than the capacitance value C of the integral capacitor. INT (In this case, the first capacitor C) ACC,A Or the second capacitor C ACC,B With the third capacitor C FIX After the parallel connection is broken, it is controlled by the first capacitor C. ACC,A Or the second capacitor C ACC,B The integrated charge carried away is much smaller than the total integrated charge, or for applications where the accuracy requirements for analog-to-digital conversion are not high and the issue of the first capacitor C can be tolerated. ACC,A (or the second capacitor C)ACC,B When the charge is carried away from the integrating capacitor, resulting in integration loss, it is not necessary to adjust the first capacitor C. ACC,A (or the second capacitor C) ACC,B The charge carried away when leaving the integrating capacitor is compensated for; for cases where no compensation is needed, Figure 2 The first voltage V in S,A Second voltage V S,B The input common-mode voltage (also known as signal ground) is directly connected to the operational transconductance amplifier OTA.

[0067] Figure 5 A circuit diagram of an integrator without compensation circuitry according to an embodiment of the present disclosure is shown, as follows: Figure 5 As shown, the first terminal of the first switch S1 is connected to the first terminal of the seventh switch S7 as the input terminal of the integrator for receiving the input current I. IN The second terminal of the first switch S1, the first terminal of the fifth switch S5, and the first capacitor C ACC,A The first terminal is connected, and the first capacitor C ACC,A The second terminal of the sixth switch S6 is connected to the first terminal of the second switch S2. The second terminal of the second switch S2 is connected to the input common-mode voltage (i.e., signal ground) of the operational transconductance amplifier OTA. The second terminal of the sixth switch S6 is connected to the third capacitor C. FIX The first terminal of the fourth switch S4 is connected to the inverting input terminal of the operational transconductance amplifier OTA, and the non-inverting input terminal of the operational transconductance amplifier OTA is connected to the input common-mode voltage of the operational transconductance amplifier OTA. The third capacitor C FIX The second terminal of the fifth switch S5, the second terminal of the third switch S3, and the first terminal of the third switch S3 are connected to the non-inverting output terminal of the operational transconductance amplifier OTA as the output terminal of the integrator to provide the output voltage V. OUT The inverting output terminal of the operational transconductance amplifier OTA provides an inverted output voltage V. OUT,N , where V OUT =-V OUT,N The second terminal of the third switch S3, the second terminal of the seventh switch S7, and the second capacitor C ACC,B The first terminal is connected, and the second capacitor C ACC,B The second terminal of the fourth switch S4 is connected to the first terminal of the eighth switch S8, and the second terminal of the eighth switch S8 is connected to the input common-mode voltage (i.e., signal ground) of the operational transconductance amplifier OTA.

[0068] Figure 6The diagram illustrates a circuit schematic of a continuous-time ΔΣ analog-to-digital converter using the integrator proposed in this disclosure, according to an embodiment of the present disclosure. Specifically, it is a circuit schematic of a continuous-time ΔΣ analog-to-digital converter using the integrator of this disclosure. Figure 6 As shown, the analog-to-digital converter includes a first resistor R. IN The system includes a first current buffer (buffer1), a second current buffer (buffer2), a 1-bit resistive digital-to-analog converter (RDAC), a 1-bit quantizer, and an integrator as described above. The first resistor R... IN The first terminal is used to receive the input analog voltage V IN,ADC The first resistor R IN The second terminal is connected to the input terminal of the first current buffer buffer1. The output terminal of the first current buffer buffer1 is connected to the input terminal of the integrator and the output terminal of the second current buffer buffer2. The output terminal of the integrator is connected to the input terminal of the quantizer. The output terminal of the quantizer outputs the digital output of the analog-to-digital converter. Simultaneously, the output terminal of the quantizer is connected to the control terminal of the resistive digital-to-analog converter RDAC. The output terminal of the resistive digital-to-analog converter RDAC is connected to the input terminal of the second current buffer buffer2. The 1-bit resistive digital-to-analog converter RDAC may include a resistor R. FB And two switches.

[0069] Optionally, the first current buffer buffer1 includes two metal-oxide-semiconductor field-effect transistors (MOSFETs), namely transistor M1 and transistor M2 (transistor M1 is an N-type MOSFET and transistor M2 is a P-type MOSFET), and three current sources. The current magnitude is 2I. B Current source 2I B The first terminal is connected to the power supply voltage, and the current source is 2I. B The second terminal, the drain of transistor M1, and the source of transistor M2 are connected together. The gate of transistor M1 is used to receive the corresponding bias voltage V. B1 The gate of transistor M2 is used to receive the corresponding bias voltage V. B2 The source of transistor M1 is connected to current source I. B ( Figure 6 The first terminal of the current source on the left side of the first current buffer buffer1 is used as the input terminal of the first current buffer buffer1, and the drain of transistor M2 is connected to the current source I. B ( Figure 6The first terminal of the current source on the right side of the first current buffer (buffer1) is used as the output terminal of the first current buffer (buffer1). Figure 6 The two current sources I on the left and right sides of the first current buffer buffer1 B The second terminal is connected to a negative power supply voltage, usually ground with a potential of 0V.

[0070] Optionally, the second current buffer, buffer2, also includes two MOSFETs: transistor M3 and transistor M4 (transistor M3 is a P-type MOSFET, and transistor M4 is an N-type MOSFET), and three current sources. The current magnitude is 2I. BFB Current source 2I BFB The first terminal is connected to the power supply voltage, and the current source is 2I. BFB The second terminal of transistor M3 is connected to the source of transistor M3 and the drain of transistor M4. The gate of transistor M3 is used to receive the corresponding bias voltage V. B3 The gate of transistor M4 is used to receive the corresponding bias voltage V. B4 The drain connection current of transistor M3 is I. BFB Current source I BFB ( Figure 6 The first terminal of the current source on the left side of the second current buffer (buffer2) serves as the output terminal of the second current buffer (buffer2). The source connection current of transistor M4 is I. BFB Current source I BFB ( Figure 6 The first terminal of the current source on the right side of the second current buffer (buffer2) is used as the input terminal of the second current buffer (buffer2). Figure 6 The two current sources I on the left and right sides of the second current buffer buffer2 in the middle BFB The second terminal is connected to a negative power supply voltage, usually ground with a potential of 0V.

[0071] The four bias voltages V in the first current buffer buffer 1 and the second current buffer 2 B1， V B2， V B3， V B4 The size of the MOSFET should be selected to ensure that it operates in the saturation region.

[0072] Optionally, a 1-bit quantizer is a circuit that quantizes its input signal and outputs a 1-bit digital code (e.g., 0 or 1). It can be constructed from a comparator. The embodiments of this disclosure do not limit the circuit structure of the 1-bit quantizer.

[0073] Optional, in the 1-bit resistive digital-to-analog converter RDAC, R FBThe left end (first end) is connected to the source of transistor M4 in the second current buffer buffer2. The negative feedback inside the common-gate transistor M4, which is operating in the saturation region, causes R to... FB The first terminal sees an equivalent signal ground. The control terminal of the 1-bit resistive digital-to-analog converter (RDAC) is connected to the output of the 1-bit quantizer. If the control terminal of the 1-bit resistive digital-to-analog converter (RDAC) receives a digital signal of 1 from the 1-bit quantizer, the reference voltage V can be selected. REF+ Connect to R FB The second end (i.e., R) FB (right end); if the control terminal of the 1-bit resistive digital-to-analog converter RDAC receives a digital signal of 0 from the 1-bit quantizer, select the reference voltage V. REF- Connect to R FB The second end (i.e., R) FB (Right end). V REF+ V is the positive reference voltage. REF- The reference voltage is negative. It should be understood that the resistive digital-to-analog converter (RDAC) can also be a switched-capacitor digital-to-analog converter or a current-steering digital-to-analog converter. The embodiments of this disclosure do not limit the type of digital-to-analog converter.

[0074] like Figure 6 As shown, this embodiment is a first-order, 1-bit continuous-time ΔΣ analog-to-digital converter. Figure 6 The red dashed box in the middle represents the integrator proposed in this embodiment. The input analog voltage V... IN,ADC Through the first resistor R IN Can be converted into input current I IN After passing through the first current buffer buffer1 based on the MOSFET common gate, the input current I IN It enters the integrator. The output voltage of this first-order integrator is V. OUT At sampling clock CK Q The rising edge can affect the output voltage V of the integrator proposed in this embodiment. OUT Sampling is performed, and the result is quantized using a 1-bit quantizer. The quantization result is D. OUT,ADC This is the output of the continuous-time ΔΣ analog-to-digital converter. The quantization result D OUT,ADC It also serves as the input to the feedback digital-to-analog converter (DAC).

[0075] In this embodiment, the digital-to-analog converter (DAC) can be a resistor-based resistive digital-to-analog converter (RDAC). The output current of this DAC passes through a second current buffer (buffer2) based on a MOSFET common gate stage before entering the loop filter, where it is combined with the input current I. IN The residual current obtained by subtraction is then fed into the input of the integrator. The subtraction of the two currents can be achieved by inverting the output current of the RDAC and directly connecting it to the input current; conversely, inverting the output current of the RDAC can be achieved by inverting the control signal, i.e., if the control terminal of the 1-bit resistive digital-to-analog converter RDAC receives a digital signal of 0 from the 1-bit quantizer, the reference voltage V can be selected. REF+ Connect to R FB The second end (i.e., R) FB (right end); if the control terminal of the 1-bit resistive digital-to-analog converter RDAC receives a digital signal 1 from the 1-bit quantizer, select the reference voltage V. REF- Connect to R FB The second end (i.e., R) FB (right end).

[0076] In one possible implementation, the two clock signals (i.e., the first switch control signal Φ1 and the second switch control signal Φ2) of this embodiment are non-overlapping clocks with a period T. S With sampling clock CK Q The periods are the same, that is: sampling clock CK Q The frequency is denoted as f Q Then T S =1 / f Q However, the phase of the first switch control signal Φ1 is earlier than the sampling clock π / 2 (i.e., 90 degrees), and the phase of the second switch control signal Φ2 is later than the sampling clock π / 2 (i.e., 90 degrees), such as... Figure 6 The timing diagram on the left is shown.

[0077] In one possible implementation, a master clock can be used as input, and then a series of digital logic circuits can be used to generate the timing control signals required in the embodiments of this disclosure, namely the first switch control signal Φ1 and the second switch control signal Φ2.

[0078] Figure 7 A schematic diagram of a timing generation circuit according to an embodiment of the present disclosure is shown, such as... Figure 7 As shown, the timing generation circuit is used to generate a non-overlapping first switch control signal Φ1 and a second switch control signal Φ2, thereby controlling the order in which each switch in the integrator circuit is turned on or off, and realizing the timing control of the switches in the integrator circuit. Figure 7 Also shown Figure 6 The sampling clock CK of the quantizer in the embodiment shown in this disclosureQ Possible ways of generating it.

[0079] like Figure 7 As shown, the timing generation circuit includes a first D-type flip-flop D-FF1, a second D-type flip-flop D-FF2, a first inverter D1, a first NAND gate circuit NAND1, a second NAND gate circuit NAND2, 2N second inverters D2, 2N third inverters D3, a fourth inverter D4, a fifth inverter D5, and a sixth inverter D6, where N is an integer greater than or equal to 1;

[0080] The input terminal of the sixth inverter D6 is connected to the clock input terminal of the first D-type flip-flop D-FF1 to receive the first clock signal CK0. The frequency of the first clock signal CK0 is twice the sampling frequency, i.e., 2f. S The data input terminal of the first D-type flip-flop D-FF1 is connected to the inverting output terminal of the first D-type flip-flop D-FF1. The non-inverting output terminal of the first D-type flip-flop D-FF1, the input terminal of the first inverter D1, and the second input terminal of the second NAND gate circuit NAND2 are connected together. The output terminal of the first inverter D1 is connected to the first input terminal of the first NAND gate circuit NAND1. The output terminal of the first NAND gate circuit NAND1 is connected to the input terminals of 2N second inverters D2 connected in series. The output terminal is connected to the input terminal of the fourth inverter D4 and the first input terminal of the second NAND gate circuit NAND2. The output terminal of the second NAND gate circuit NAND2 is connected to the input terminals of 2N third inverters D3 connected in series. The output terminals of the 2N third inverters D3 connected in series are connected to the input terminal of the fifth inverter D5 and the second input terminal of the first NAND gate circuit NAND1. The output terminal of the fourth inverter D4 is used to provide the first switch control signal Φ1, and the output terminal of the fifth inverter D5 is used to provide the second switch control signal Φ2.

[0081] The output of the sixth inverter D6 is connected to the clock input of the second D-type flip-flop D-FF2, the data input of the second D-type flip-flop D-FF2 is connected to its inverting output, and the non-inverting output of the second D-type flip-flop D-FF2 is used to provide the second clock signal CK. Q The second clock signal CK Q Can be used as Figure 6 The sampling clock of the quantizer, the second clock signal CK Q The frequency is half the frequency of the first clock signal CK0, that is: f S .

[0082] In this configuration, the number of inverters D2 and D3 connected in series is the same, 2N, where N is an integer greater than or equal to 1. A larger value of N results in a longer non-overlapping time for the first switch control signal Φ1 and the second switch control signal Φ2; a smaller value of N results in a shorter non-overlapping time for the first switch control signal Φ1 and the second switch control signal Φ2. This disclosure does not impose any restrictions on the specific value of N and it can be set according to the actual application scenario.

[0083] In one possible implementation, the timing generation circuit can be a controller (such as a microcontroller, processor, etc.) that can generate timing control signals according to preset program code, namely: the first switch control signal Φ1 and the second switch control signal Φ2.

[0084] The timing generation circuit used to provide the first switch control signal Φ1 and the second switch control signal Φ2 for the integrator proposed in this disclosure is not unique. This disclosure does not limit the specific circuit structure for generating the first switch control signal Φ1 and the second switch control signal Φ2.

[0085] In summary, the integrator for a continuous-time ΔΣ analog-to-digital converter proposed in this disclosure can convert the input current I of the integrator into the output current I of the converter. IN Within a certain time period (e.g., 0.5T) S The accumulated integrated charge is directly "poured" onto the integrating capacitor of the integrator, achieving passive integration of the signal. This process does not require the participation of the active device, the operational transconductance amplifier (OTA). Furthermore, to avoid aliasing caused by switching operations during this process, the "charge pouring" operation is performed in a "ping-pong" manner, thus avoiding aliasing caused by switching operations in the early stages of the loop filter. This reduces the power consumption of the integrator in the continuous-time ΔΣ analog-to-digital converter without affecting its anti-aliasing function. Furthermore, a compensation circuit can be added to the integrator; when the first capacitor C... ACC,A (or the second capacitor C) ACC,B ) and the third capacitor C FIX When the parallel connection is broken, the first capacitor C ACC,A (or the second capacitor C) ACC,B The partial integration charge (i.e., the charge loss of the integrating capacitor) is compensated. Since the operational transconductance amplifier OTA only participates in this compensation operation, and the accuracy required for the compensation operation is lower than that required for the entire integration operation, the power consumption of the operational transconductance amplifier OTA in this disclosure is lower than that of the operational transconductance amplifier OTA in a conventional active integrator.

[0086] Since the integrator achieves integration through charge sharing and does not require the operational transconductance amplifier (OTA) to provide a large current to charge the integrating capacitor; and since the operational transconductance amplifier (OTA) can participate in compensation in the integrator, and the compensation circuit can tolerate a higher error than the integrating circuit, the power consumption of the operational transconductance amplifier (OTA) used in the integrator proposed in this disclosure is lower than the power consumption of the operational transconductance amplifier (OTA) in the active continuous-time integrators of the related prior art. Since the power consumption of the operational transconductance amplifier (OTA) is the dominant component of the power consumption of the active continuous-time integrator, the power consumption of the integrator in the embodiments of this disclosure is lower than the power consumption of the continuous-time integrator in the related art.

[0087] The integrator of this disclosure is applied to a wideband continuous-time ΔΣ analog-to-digital converter (ADC). Considering that wideband continuous-time ΔΣ ADCs tend to be designed using advanced CMOS processes, designing high-gain operational transconductance amplifiers (OTAs) is difficult in advanced CMOS processes, but advanced CMOS processes facilitate high-speed switching. If a conventional active integrator is used in a wideband continuous-time ΔΣ ADC, the operational transconductance amplifier (OTA) needs to have a high gain-bandwidth product, and implementing a high-speed operational transconductance amplifier (OTA) requires high power consumption. The integrator proposed in this disclosure fully utilizes the advantages of advanced CMOS processes for high-speed switching, achieving "passive" integration with no integration loss through a passive "charge-pour" method. This avoids the need for high-performance (i.e., high-speed, high-gain) active devices, reduces integrator power consumption, and thus helps reduce the overall power consumption of the wideband continuous-time ΔΣ ADC.

[0088] At the application level, the wideband continuous-time ΔΣ analog-to-digital converter can be used in portable communication devices. If the integrator proposed in this disclosure is applied to the wideband continuous-time ΔΣ analog-to-digital converter in such portable communication devices, the integrator can significantly reduce the power consumption of the wideband continuous-time ΔΣ analog-to-digital converter, which is beneficial to extending the usage time of such portable communication devices after each charge.

[0089] It should be understood that, for the sake of simplicity and clarity, the illustrations only show single-ended circuit implementations; however, this technique is equally applicable to differential circuits.

[0090] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of the disclosure with reference to the accompanying drawings.

[0091] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0092] This disclosure also proposes an electronic device comprising an integrator circuit for a continuous-time ΔΣ analog-to-digital converter as described above.

[0093] Electronic devices can be provided as terminals, servers, or other forms of devices. Among them, terminal devices can be user equipment (UE), mobile devices, user terminals, terminals, cellular phones, cordless phones, personal digital assistants (PDAs), handheld devices, computing devices, in-vehicle devices, wearable devices, etc.

[0094] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0095] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0096] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0097] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An integrator characterized by, The integrator comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, an operational transconductance amplifier, a first capacitor, a second capacitor, and a third capacitor, wherein a first end of the first switch is connected with a first end of the seventh switch as an input end of the integrator for receiving an input current, a second end of the first switch and a first end of the fifth switch are connected with a first end of the first capacitor, a second end of the first capacitor and a first end of the sixth switch are connected with a first end of the second switch, a second end of the second switch is for receiving a first voltage, a second end of the sixth switch, a first end of the third capacitor, and a first end of the fourth switch are connected with an inverting input end of the operational transconductance amplifier, a non-inverting input end of the operational transconductance amplifier is connected with an input common-mode voltage, a second end of the third capacitor, a second end of the fifth switch, and a first end of the third switch are connected with a non-inverting output end of the operational transconductance amplifier as an output end of the integrator for providing an output voltage, a second end of the third switch and a second end of the seventh switch are connected with a first end of the second capacitor, a second end of the second capacitor and a second end of the fourth switch are connected with a first end of the eighth switch, and a second end of the eighth switch is for receiving a second voltage; The first switch, the second switch, the third switch, and the fourth switch receive a first switch control signal, the fifth switch, the sixth switch, the seventh switch, and the eighth switch receive a second switch control signal, and the first switch control signal and the second switch control signal are non-overlapping signals. In response to the first switch control signal changing from a first level to a second level and the second switch control signal changing from a second level to a first level, the first capacitor and the third capacitor are connected in parallel to form an integral capacitor with a preset total capacitance value, the charge accumulated by the first capacitor and the charge on the third capacitor together form the charge amount of the integral capacitor, and the charge carried by the input current of the integrator starts to accumulate on the second capacitor. In response to the first switch control signal changing from the second level to the first level and the second switch control signal changing from the first level to the second level, the second capacitor and the third capacitor are connected in parallel to form an integral capacitor with a preset total capacitance value, the charge accumulated by the second capacitor and the charge on the third capacitor together form the charge amount of the integral capacitor, and the charge carried by the input current of the integrator starts to accumulate on the first capacitor.

2. Integrator according to claim 1, characterized in that In response to the first switch control signal being the first level, the first switch, the second switch, the third switch, and the fourth switch are closed. In response to the first switch control signal being the second level, the first switch, the second switch, the third switch, and the fourth switch are opened. In response to the second switch control signal being the first level, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are closed. In response to the second switch control signal being the second level, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are opened. In response to the second switch control signal being the second level, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are turned off.

3. Integrator according to claim 1 or 2, characterized in that The integrator further comprises a compensation circuit for compensating for part of the integral charge taken away when the parallel connection of the first capacitor or the second capacitor and the third capacitor is disconnected, the compensation circuit comprising a first sample-and-hold circuit, a second sample-and-hold circuit, and the operational transconductance amplifier, The inverting output terminal of the operational transconductance amplifier is connected to the input terminal of the first sample-and-hold circuit and the input terminal of the second sample-and-hold circuit, the output terminal of the first sample-and-hold circuit is connected to the second terminal of the second switch for providing the first voltage, and the output terminal of the second sample-and-hold circuit is connected to the second terminal of the eighth switch for providing the second voltage.

4. Integrator according to claim 3, characterized in that Each sample-and-hold circuit comprises a sampling switch, a sample-and-hold capacitor, and a voltage buffer, The first terminal of the sampling switch serves as the input terminal of the sample-and-hold circuit, the second terminal of the sampling switch and the first terminal of the sample-and-hold capacitor are connected to the input terminal of the voltage buffer, the second terminal of the sample-and-hold capacitor is connected to the output common-mode voltage of the operational transconductance amplifier, and the output terminal of the voltage buffer serves as the output terminal of the sample-and-hold circuit.

5. The integrator of claim 3, wherein, In response to the first switch control signal changing from the first level to the second level and the second switch control signal changing from the second level to the first level, the first capacitor and the third capacitor are connected in parallel to form an integral capacitor with a total capacitance value of a preset value, the charge accumulated by the first capacitor and the charge on the third capacitor together form the amount of charge of the integral capacitor, the parallel connection of the second capacitor and the third capacitor is disconnected to take away part of the integral charge, and the charge carried by the input current of the integrator starts to accumulate on the second capacitor together with the lost charge compensated by the second voltage output by the second sample-and-hold circuit; In response to the first switch control signal changing from the second level to the first level and the second switch control signal changing from the first level to the second level, the second capacitor and the third capacitor are connected in parallel to form an integral capacitor with a total capacitance value of a preset value, the charge accumulated by the second capacitor and the charge on the third capacitor together form the amount of charge of the integral capacitor, the parallel connection of the first capacitor and the third capacitor is disconnected to take away part of the integral charge, and the charge carried by the input current of the integrator starts to accumulate on the first capacitor together with the lost charge compensated by the first voltage output by the first sample-and-hold circuit.

6. Integrator according to claim 5, characterized in that The charge accumulated by the first capacitor includes the charge formed by the accumulation of the input current and the part of the integral charge taken away by the second capacitor when the second switch control signal changes from the first level to the second level half a sampling clock period ago; The charge accumulated by the second capacitor includes the charge formed by the accumulation of the input current and the part of the integral charge taken away by the first capacitor when the first switch control signal changes from the first level to the second level half a sampling clock period ago.

7. Integrator according to claim 1 or 2, characterized in that The first voltage and the second voltage are the input common-mode voltage of the operational transconductance amplifier.

8. An analog-to-digital converter, characterized by The analog-digital converter comprises a first resistor, a first current buffer, a second current buffer, a digital-analog converter, a quantizer, and the integrator as claimed in any one of claims 1 to 7, a first end of the first resistor is configured to receive an analog voltage, a second end of the first resistor is connected to an input end of the first current buffer, an output end of the first current buffer is connected to an input end of the integrator and an output end of the second current buffer, an output end of the integrator is connected to an input end of the quantizer, an output end of the quantizer outputs a digital output of the analog-digital converter, and meanwhile, the output end of the quantizer is connected to a control end of the digital-analog converter, and an output end of the digital-analog converter is connected to an input end of the second current buffer.

9. An electronic device, comprising: The electronic device comprises the integrator as claimed in any one of claims 1 to 7.

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