Image scaling method and system based on bicubic interpolation

Abstract

The present invention discloses an image scaling method and system based on bicubic interpolation, which utilizes the on-chip resources of FPGA to achieve real-time image scaling without relying on SDRAM cache. Interpolation calculations are performed through a simplified cubic function formula, which reduces the computational complexity while retaining the high-quality characteristics of bicubic interpolation. The system dynamically enables the number of RAM modules to adapt to different image resolutions and effectively manages storage resources. The system in this case includes modules such as image acquisition, cache management, neighboring pixel extraction, bicubic interpolation calculation, reading control, and output, and has the function of dynamically adjusting the processing speed according to the complexity of the image. The system can efficiently process image scaling tasks, provide high-quality scaled images, and is suitable for various image processing applications. By optimizing resource utilization and improving processing efficiency, the present invention provides strong technical support for real-time image processing.

Description

Technical Field

[0001] The present invention relates to the technical field of LED display screen image scaling, and in particular to an image scaling method and system based on bicubic interpolation. Background Art

[0002] In the LED display industry, image scaling is a key technology for achieving high-quality displays. While traditional image scaling methods, such as nearest neighbor interpolation, linear interpolation, and bilinear interpolation, can meet basic scaling requirements to a certain extent, they lack the ability to process image edges and achieve smoothness. Especially at large scaling ratios, these methods can easily lead to jagged edges, affecting the overall visual quality.

[0003] To overcome these shortcomings, the industry has begun exploring more complex interpolation methods. Bicubic interpolation has attracted much attention for its ability to create smoother image edges and achieve better display effects. However, in actual bicubic interpolation applications, for example, given n+1 data nodes divided into n intervals, a cubic function is constructed in each interval. Assume that each segment of the cubic function is defined by the following equation:

[0004] Si(x)=ai+bi(x-xi)+ci(x-xi)^2+di(x-xi)^3,i=0,1,……,n-1.

[0005] In this method, the value of function f at a point (x, y) is obtained by taking the weighted average of the sixteen nearest sample points in a rectangular grid. This requires using two polynomial interpolation cubic functions, one for each direction. However, the cubic polynomial coefficients ai, bi, ci, and di require numerous multiplications and tedious matrix operations, making them difficult to solve in real time on an FPGA.

[0006] Furthermore, Chinese Patent Publication No. CN115359135A discloses an image scaling system and method for baseboard management and control. This system improves image scaling quality by splitting image scaling into two steps: horizontal and vertical scaling, and applying different filtering methods based on the zoom factor. While these methods achieve a good scaling effect, they are still limited to one-dimensional filtering combinations, failing to fully utilize two-dimensional spatial correlations. Furthermore, their implementation efficiency on FPGAs needs to be improved.

[0007] Therefore, how to efficiently implement bicubic interpolation on the FPGA platform has become an urgent problem to be solved. Summary of the Invention

[0008] The present invention overcomes the deficiencies of the above-mentioned technologies and provides an image scaling method and system based on bicubic interpolation.

[0009] To achieve the above object, the present invention adopts the following technical solutions:

[0010] A first aspect of an embodiment of the present invention discloses an image scaling method based on bicubic interpolation, comprising the following steps:

[0011] Step S1: Utilize the storage resources of the FPGA and divide it into multiple RAM modules for caching image data;

[0012] Step S2: obtaining the original image data inputted from the outside, and caching the data into multiple RAM modules in an alternating row manner;

[0013] Among them, one RAM module is used to write the image row currently being processed, that is, write the current row; the remaining RAM modules are used to read and store the image rows that have been processed before, that is, read the history row;

[0014] Step S3: extracting the corresponding 4x4 neighboring pixel matrix from the RAM module storing the history row according to the position to be interpolated in the target image and the scaling factor;

[0015] Step S4: for each row of the extracted 4x4 adjacent pixel matrix, perform bicubic interpolation calculation within the row using a cubic function;

[0016] Step S5: performing inter-column bicubic interpolation calculation based on the intra-row bicubic interpolation result obtained in step S4 to obtain preliminary pixel values;

[0017] Step S6: Based on the preliminary pixel values ​​obtained in step S5, the final pixel values ​​are obtained according to the final size of the target image and the scaling factor;

[0018] Step S7: Output the final pixel value obtained in step S6 to form a scaled image.

[0019] As another optional implementation, the cubic function formula is: pixel[1]+0.5*x*(pixel[2]-pixel[0]+x*(2.0*pixel[0]-5.0*pixel[1]+4.0*pixel[2]-pixel[3]+x*(3.0*(pixel[1]-pixel[2])+pixel[3]-pixel[0]))); wherein pixel[0] to pixel[3] are adjacent pixels in a row, and x is a normalized offset.

[0020] As another optional embodiment, the method further includes: before step S1 , dynamically enabling the number of RAM modules according to the image resolution;

[0021] When the input image resolution is lower than the preset threshold, it is judged as a small-size image and three RAM modules are enabled, one of which is used to write the current row; the remaining two RAM modules are used to read the history rows;

[0022] When the input image resolution is higher than the preset threshold, it is judged as a large-size image and 5 RAM modules are enabled, of which 1 RAM module is used to write the current row; the remaining 4 RAM modules are used to read the historical rows.

[0023] As another optional implementation, the preset threshold is the product of the image width and height, and is dynamically calculated based on the available Block RAM capacity of the FPGA. The calculation formula is:

[0024] Threshold = (total available Block RAM) / (RAM space occupied by single-line pixel data × 4)

[0025] The coefficient 4 in the denominator is the redundancy required to ensure that at least 4 rows of historical data are cached.

[0026] As another optional implementation, the following steps are further included between step S5 and step S6:

[0027] Sub-pixel displacement compensation is performed on the preliminary pixel value, a sub-pixel offset is calculated according to a scaling factor, and a coordinate position of the preliminary pixel value is adjusted by linear interpolation.

[0028] A second aspect of an embodiment of the present invention discloses an image scaling system based on bicubic interpolation, comprising:

[0029] The upstream image acquisition module 1 is used to acquire the original image data and is configured to output the original image data in row arrangement;

[0030] Cache management module 2 is used to cache raw image data. It includes multiple RAM modules differentiated from the FPGA's storage resources. One RAM module is dedicated to writing the image row currently being processed, i.e., writing the current row. The remaining RAM modules are used to read and store previously processed image rows, i.e., reading the history rows.

[0031] a neighboring pixel extraction module 3, configured to extract a 4x4 pixel matrix from a plurality of RAM modules according to a position in the target image that requires interpolation and a scaling factor;

[0032] Bicubic interpolation calculation module 4, performs bicubic interpolation calculation on the read 4x4 pixel matrix;

[0033] The reading control module 5 controls the reading of the correct pixel value from the bicubic interpolation module 4 according to the size and scaling factor of the target image;

[0034] The output module 6 selects corresponding pixel values ​​from the pixel values ​​read by the control module 5 and outputs and sends the scaled image data.

[0035] As another optional implementation, the bicubic interpolation calculation module 4 includes:

[0036] Intra-row bicubic interpolation calculation unit 41: configured to calculate intra-row bicubic interpolation for each row of pixels in the 4x4 pixel matrix;

[0037] The inter-column bicubic interpolation calculation unit 42 is configured to calculate inter-column bicubic interpolation based on the result calculated by the intra-row bicubic interpolation calculation unit 41 .

[0038] As another optional implementation, the bicubic interpolation calculation module 4 includes at least one independent intra-row bicubic interpolation calculation unit 41 and at least one independent inter-column bicubic interpolation calculation unit 42: each bicubic interpolation calculation unit 41 corresponds to one bicubic interpolation calculation unit 42 and one scaling factor; when images of different sizes need to be scaled, the final pixel values ​​corresponding to the different scaling factors are synchronously output through the bicubic interpolation calculation module 4 to form a multi-resolution image stream.

[0039] As another optional implementation, the method further includes:

[0040] Image complexity analysis module 7 is responsible for analyzing the currently processed image area and outputting a signal indicating the image complexity;

[0041] A clock management module 8, configured to dynamically adjust the clock frequency of the bicubic interpolation calculation module 4 according to the output of the image complexity analysis module 7;

[0042] The clock interface module 9 is used to receive the clock signal from the clock management module 8 and adjust its operating speed according to the change of the clock frequency;

[0043] The control logic module 10 receives the output of the image complexity analysis module 7 and sends a corresponding control signal to the clock management module 9 to indicate the adjustment of the clock frequency; and monitors the status of the bicubic interpolation calculation module 4 to ensure that it runs at the correct clock frequency.

[0044] A third aspect of an embodiment of the present invention discloses a control system comprising:

[0045] A memory 601 storing executable program code;

[0046] a processor 602 coupled to the memory 601;

[0047] The processor 602 calls the executable program code stored in the memory 601 to execute the method described in the first aspect.

[0048] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0049] 1. By employing bicubic interpolation, this method more accurately captures high-frequency details in images and significantly reduces edge jaggedness compared to traditional bilinear interpolation. Interpolation using 16 neighboring pixels, compared to just four, allows for smoother transitions in image changes, resulting in a more natural and detailed scaled image, thus meeting the requirements for high-quality image processing.

[0050] 2. This invention achieves efficient management and access of image data by rationally allocating FPGA storage resources and alternating row-by-row buffering of image data into multiple RAM modules. Dynamically enabling the number of RAM modules to be flexibly adjusted based on image resolution conserves storage resources while avoiding waste of hardware resources. Furthermore, leveraging the FPGA's parallel computing capabilities, this method enables parallel processing of intra-row and inter-column bicubic interpolation, improving processing efficiency.

[0051] 3. The method of the present invention can scale images in real time, bypassing SDRAM caching and relying solely on FPGA on-chip resources. Through pipelined parallel processing and a simplified cubic function formula, the additional delay introduced by step-by-step filtering is avoided, enabling real-time output of the scaled image, meeting the real-time requirements of practical applications.

[0052] 4. This invention introduces an image complexity analysis module that analyzes the currently processed image region in real time and dynamically adjusts the processing speed based on image complexity. This ensures sufficient computing resources when processing complex images while avoiding wasted computing resources when processing simple images, thereby improving the system's flexibility and adaptability.

[0053] 5. By introducing dynamic threshold calculation based on FPGA-based block RAM, this invention eliminates the need for manual threshold reconfiguration, reducing deployment costs. Furthermore, the system's control logic is simple and clear, facilitating subsequent maintenance and upgrades. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] Figure 1 This is a schematic diagram of the steps of the first embodiment of the present invention;

[0056] Figure 2 This is a structural block diagram of the second embodiment disclosed in the present invention;

[0057] Figure 3 It is a structural diagram of a control system according to the third embodiment disclosed in the present invention; DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "first," "second," "third," "fourth," etc. in the description and claims of the present invention are used to distinguish different objects rather than to describe a specific order. The terms "including" and "having," as well as any variations thereof, in the embodiments of the present invention, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products, or apparatuses.

[0060] The present invention discloses a bicubic interpolation-based image scaling method and system. This method utilizes on-chip FPGA resources to scale images in real time, bypassing SDRAM caching. Furthermore, the polynomial coefficients of cubic interpolation can be defined as separate variables using a relatively simple interpolation formula, simplifying code implementation.

[0061] Example 1

[0062] See also Figure 1 , an image scaling method based on bicubic interpolation, comprising the following steps:

[0063] Step S1: Utilize the storage resources of the FPGA and divide it into multiple RAM modules for caching image data;

[0064] Step S2: obtaining the original image data inputted from the outside, and caching the data into multiple RAM modules in an alternating row manner;

[0065] Among them, one RAM module is dedicated to writing the image row currently being processed, that is, writing the current row; the remaining RAM modules are used to read and store the image rows that have been processed before, that is, reading the history rows;

[0066] Step S3: According to the position to be interpolated in the target image and the scaling factor, the corresponding 4x4 neighboring pixel matrix is ​​extracted from the RAM module storing the history row; this matrix will be used for subsequent interpolation calculations.

[0067] Step S4: for each row of the extracted 4x4 adjacent pixel matrix, perform bicubic interpolation calculation within the row using a cubic function;

[0068] The cubic function formula is: pixel[1]+0.5*x*(pixel[2]-pixel[0]+x*(2.0*pixel[0]-5.0*pixel[1]+4.0*pixel[2]-pixel[3]+x*(3.0*(pixel[1]-pixel[2])+pixel[3]-pixel[0]))); where pixel[0] to pixel[3] represent the four adjacent pixel values ​​in the current processing row (this is done for each row of the 4x4 matrix), and x is the normalized offset of the current target image position relative to the known pixel position in the row. The characteristic of bicubic interpolation is that it takes into account the 16 neighboring pixels around the target pixel (forming a 4x4 grid), which can better capture changes in the image and provide smoother and more natural scaling results.

[0069] Step S5: performing inter-column bicubic interpolation calculation based on the intra-row bicubic interpolation result obtained in step S4 to obtain preliminary pixel values;

[0070] Step S6: Based on the preliminary pixel values ​​obtained in step S5, the final pixel values ​​are obtained according to the final size of the target image and the scaling factor. In specific implementation, necessary adjustments (such as rounding, truncation, etc.) can be made to the preliminary pixel values.

[0071] Step S7: Output the final pixel value obtained in step S6 to obtain a scaled image.

[0072] In addition, in step S2, the scaling factor is calculated in the following manner: if the target image width is W_d and the original image width is W_s, then the scaling factor scale_x=W_s / W_d.

[0073] As described above, this solution utilizes bicubic interpolation, which, compared to traditional bilinear interpolation, utilizes more neighboring pixels (16 instead of 4) for interpolation calculations. This allows for more accurate capture of high-frequency image details, reduces edge jaggedness, and significantly improves image scaling quality. By rationally allocating the FPGA's storage resources, image data is cached alternately row-by-row in multiple RAM modules (1 write + 4 reads / 1 write + 2 reads), enabling efficient management and access of image data. Furthermore, by parallelizing bicubic interpolation calculations within rows and between columns, pipelined parallel processing is supported, fully utilizing the FPGA's parallel computing capabilities and improving processing efficiency. Furthermore, image scaling can be performed in real time, bypassing the SDRAM cache and relying on the FPGA's on-chip resources. Furthermore, to avoid the complexity of solving cubic polynomial coefficients in real time within the FPGA, this solution employs a simplified cubic function formula for interpolation calculations. This formula not only retains the core concept of bicubic interpolation but also significantly reduces computational complexity, making FPGA implementation feasible. Moreover, since this solution implements parallel calculation of bicubic interpolation on FPGA, it avoids the additional delay caused by step filtering, so that the scaled image can be output in real time, meeting the real-time requirements in practical applications.

[0074] As a preferred embodiment, the method of this case further includes: before step S1, dynamically enabling the number of RAM modules according to the image resolution;

[0075] When the input image resolution is lower than the preset threshold, it is judged as a small-size image and three RAM modules are enabled, one of which is used to write the current row; the remaining two RAM modules are used to read the history rows;

[0076] When the input image resolution is higher than the preset threshold, it is judged as a large-size image and 5 RAM modules are enabled, of which 1 RAM module is used to write the current row; the remaining 4 RAM modules are used to read the historical rows.

[0077] As mentioned above, the mechanism of dynamically enabling RAM modules in this case can enable 3 RAM modules (1 write + 2 read) in small-size image scenarios, which saves 40% of storage resources compared to fixed 5 modules and avoids waste of hardware resources. In large-size image scenarios, 5 RAM modules (1 write + 4 read) are enabled to ensure the complete reading of the 4x4 neighborhood pixel matrix and avoid interpolation errors caused by insufficient historical row cache. Moreover, dynamically shutting down unenabled RAM modules can reduce static power consumption. In addition, when fewer RAM modules are enabled for small-size images, the data addressing path length is reduced, the access delay is shortened, and the interpolation calculation throughput is improved.

[0078] As a preferred embodiment, the preset threshold is the product of the image width and height, and is dynamically calculated based on the available Block RAM capacity of the FPGA. The calculation formula is:

[0079] Threshold = (total available Block RAM) / (RAM space occupied by single-line pixel data × 4)

[0080] The coefficient 4 in the denominator is the redundancy required to ensure that at least 4 rows of historical data are cached.

[0081] Specifically, taking Xilinx UltraScale FPGA as an example, assuming that a single row of pixel data occupies 1KB of RAM space and the total available block RAM is 800KB, the threshold is:

[0082] Threshold = 800 / (1×4) = 200 rows → 200×1024 pixels / row, that is, when the input image resolution is less than 200 rows×1024 pixels, 3 RAM modules are enabled, otherwise 5 are enabled.

[0083] The effect verification data is as follows:

[0084]

[0085] Thus, by introducing dynamic threshold calculation based on the available Block RAM of the FPGA, this solution can dynamically calculate the threshold (200 rows × 1024 pixels / row) based on the actual available Block RAM capacity of the FPGA (e.g., 800KB) and the size of a single row of data (e.g., 1KB), thus avoiding the waste or shortage of resources caused by fixed thresholds. Furthermore, the "total amount of available Block RAM" in the threshold formula can be automatically adapted to different FPGA models, eliminating the need for manual reconfiguration of the threshold and reducing deployment costs. The denominator coefficient of 4 ensures that even in the presence of storage fragmentation or bursty data streams, a redundant cache of at least 4 rows of historical data can be retained, preventing interpolation interruptions caused by instantaneous data congestion.

[0086] As a preferred embodiment, the following steps are further included between step S5 and step S6:

[0087] Sub-pixel displacement compensation is performed on the preliminary pixel value, the sub-pixel offset is calculated according to the scaling factor, and the coordinate position of the preliminary pixel value is adjusted by linear interpolation. In specific implementation, sub-pixel displacement compensation refers to fine-tuning the pixel position during image processing to correct the slight position deviation caused by integer pixel interpolation or scaling. This fine-tuning is based on the sub-pixel level, that is, the accuracy is less than one pixel unit. Through sub-pixel displacement compensation, the pixel position deviation caused by rounding errors and the like during the bicubic interpolation process can be corrected, so that the scaled image is closer to the size and proportion of the original image. Especially when the scaling ratio is large or the image is rich in details, sub-pixel displacement compensation can significantly improve the quality of image scaling and reduce image distortion and blurring. In this way, by introducing the sub-pixel displacement compensation step, the solution of this case has stronger adaptability and flexibility when dealing with different scaling ratios, different image resolutions and different image contents.

[0088] Example 2

[0089] The second embodiment provides an image scaling system based on bicubic interpolation, which adopts the image scaling method described in the first embodiment. The system can efficiently process image scaling tasks and dynamically adjust the processing speed according to the complexity of the image.

[0090] First, the upstream image acquisition module 1 acquires raw image data and outputs it in rows. Then, the cache management module 2 uses the FPGA's storage resources to create multiple RAM modules to cache the raw image data. One RAM module is dedicated to writing the currently processed image row, while the remaining RAM modules are used to read and store previously processed image rows.

[0091] Next, the neighboring pixel extraction module 3 extracts a 4x4 pixel matrix from multiple RAM modules based on the location in the target image that requires interpolation and the scaling factor. The bicubic interpolation calculation module 4 then performs bicubic interpolation on the read 4x4 pixel matrix. This calculation process is divided into two steps: first, the intra-row bicubic interpolation calculation unit 41 performs intra-row bicubic interpolation on each row of pixels, and then the inter-column bicubic interpolation calculation unit 42 performs inter-column bicubic interpolation on the intra-row interpolation results.

[0092] The read control module 5 controls the reading of the correct pixel values ​​from the bicubic interpolation module according to the size and scaling factor of the target image. Finally, the output module 6 selects the corresponding pixel value from the pixel values ​​of the read control module and outputs the scaled image data.

[0093] Furthermore, the image complexity analysis module 7 is responsible for analyzing the currently processed image region and outputting a signal indicating the image complexity. The clock management module 8 dynamically adjusts the clock frequency of the bicubic interpolation module based on this signal. The clock interface module 9 receives the clock signal from the clock management module and adjusts its operating speed based on changes in the clock frequency. The control logic module 10 receives the output of the image complexity analysis module and sends corresponding control signals to the clock management module to instruct the clock frequency to adjust. It also monitors the status of the bicubic interpolation module to ensure it operates at the correct clock frequency.

[0094] As described above, the cache management module of the system in this case utilizes the storage resources of the FPGA to achieve caching and efficient access to the original image data through multiple RAM modules, thereby improving the throughput of data processing. Through the setting of the image complexity analysis module, it is possible to analyze the currently processed image area in real time and output a corresponding signal based on the image complexity. The clock management module dynamically adjusts the clock frequency of the bicubic interpolation module based on the signal, thereby achieving the function of dynamically adjusting the processing speed according to the image content. This ensures that sufficient computing resources can be obtained when processing complex images, and avoids wasting computing resources when processing simple images. The bicubic interpolation calculation module adopts a two-step interpolation calculation method within the row and between the columns, which can more accurately calculate the value of each pixel in the target image, so as to create smoother image edges and improve the quality of the scaled image.

[0095] Example 3

[0096] like Figure 3 As shown, a control system includes:

[0097] A memory 601 storing executable program code;

[0098] a processor 602 coupled to the memory 601;

[0099] The processor 602 calls the executable program code stored in the memory 601 to execute the method of the gantry mechanism for taking materials from the rectangular tray in the first embodiment.

[0100] An embodiment of the present invention discloses a computer-readable storage medium storing a computer program, wherein the computer program enables a computer to execute Figure 1 method.

[0101] An embodiment of the present invention further discloses a computer program product, wherein when the computer program product is run on a computer, the computer is caused to execute part or all of the steps of the methods in the above method embodiments.

[0102] In summary, the bicubic interpolation-based image scaling method and system provided in this embodiment offer the following advantages: efficient processing of image scaling tasks, dynamic activation of RAM modules, dynamic adjustment of processing speed, and high-quality image scaling. These advantages make this system promising for broad application in the LED display industry and other fields requiring high-quality image scaling.

[0103] The above describes in detail an image scaling method and system based on bicubic interpolation disclosed in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the method and core concept of the present invention. At the same time, for those skilled in the art, based on the concept of the present invention, there may be changes in the specific implementation methods and application scope. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. An image scaling method based on bicubic interpolation, characterized in that: The following steps are involved: Step S1: Utilize the storage resources of the FPGA to divide into multiple RAM modules for caching image data; Step S2: obtaining the original image data inputted from the outside, and caching the data into multiple RAM modules in an alternating row manner; Among them, one RAM module is used to write the image row currently being processed, that is, write the current row; the remaining RAM modules are used to read and store the image rows that have been processed before, that is, read the history row; Step S3: extracting the corresponding 4x4 neighboring pixel matrix from the RAM module storing the history row according to the position to be interpolated in the target image and the scaling factor; Step S4: for each row of the extracted 4x4 adjacent pixel matrix, perform bicubic interpolation calculation within the row using a cubic function; Step S5: performing inter-column bicubic interpolation calculation based on the intra-row bicubic interpolation result obtained in step S4 to obtain preliminary pixel values; Step S6: Based on the preliminary pixel values ​​obtained in step S5, the final pixel values ​​are obtained according to the final size of the target image and the scaling factor; Step S7: Output the final pixel value obtained in step S6 to form a scaled image.

2. The image scaling method according to claim 1, wherein: The cubic function formula is: pixel[1]+ 0.5 * x * (pixel[2] - pixel[0] + x * (2.0 * pixel[0] - 5.0 * pixel[1] + 4.0* pixel[2] - pixel[3] + x * (3.0 * (pixel[1] - pixel[2]) + pixel[3] - pixel[0]))); where pixel[0]~pixel[3] are adjacent pixels in a row, and x is the normalized offset.

3. The image scaling method according to claim 1, wherein: Also includes: Before step S1, dynamically enable the number of RAM modules according to the image resolution; When the input image resolution is lower than the preset threshold, it is judged as a small-size image and three RAM modules are enabled, one of which is used to write the current row; the remaining two RAM modules are used to read the history rows; When the input image resolution is higher than the preset threshold, it is determined to be a large-size image and 5 RAM modules are enabled, of which 1 RAM module is used to write the current row; The remaining 4 RAM modules are used to read history lines.

4. The method according to claim 3, characterized in that The preset threshold is the product of the image width and height, and is dynamically calculated based on the available Block RAM capacity of the FPGA. The calculation formula is: Threshold = (total available Block RAM) / (RAM space occupied by single-line pixel data × 4); The coefficient 4 in the denominator is the redundancy required to ensure that at least 4 rows of historical data are cached.

5. The method according to claim 1, wherein The following steps are also included between step S5 and step S6: Sub-pixel displacement compensation is performed on the preliminary pixel value, a sub-pixel offset is calculated according to a scaling factor, and a coordinate position of the preliminary pixel value is adjusted by linear interpolation.

6. An image scaling system based on bicubic interpolation, characterized in that: include: An upstream image acquisition module (1) is used to acquire original image data and is configured to output the original image data in row arrangement; A cache management module (2) is used to cache the original image data, and includes: a plurality of RAM modules differentiated by using the storage resources of the FPGA; wherein one RAM module is specifically used to write the image row currently being processed, i.e., write the current row; and the remaining RAM modules are used to read and store the image rows that have been processed before, i.e., read the history rows; a neighboring pixel extraction module (3) configured to extract a 4x4 pixel matrix from the plurality of RAM modules according to a position in the target image to be interpolated and a scaling factor; A bicubic interpolation calculation module (4) performs bicubic interpolation calculation on the read 4x4 pixel matrix; A reading control module (5) controls the reading of correct pixel values ​​from the bicubic interpolation module (4) according to the size and scaling factor of the target image; An output module (6) selects a corresponding pixel value from the pixel values ​​read from the control module (5) and outputs and sends the scaled image data; Wherein, the bicubic interpolation calculation module (4) includes: Intra-row bicubic interpolation calculation unit (41): configured to calculate intra-row bicubic interpolation for each row of pixels in the 4x4 pixel matrix; An inter-column bicubic interpolation calculation unit (42) is configured to calculate inter-column bicubic interpolation based on the result calculated by the intra-row bicubic interpolation calculation unit (41).

7. The image scaling system according to claim 6, wherein: The bicubic interpolation calculation module (4) comprises at least one set of independent intra-row bicubic interpolation calculation units (41) and at least one set of independent inter-column bicubic interpolation calculation units (42): each bicubic interpolation calculation unit (41) corresponds to a set of bicubic interpolation calculation units (42) and a corresponding scaling factor; when images of different sizes need to be scaled, final pixel values ​​corresponding to different scaling factors are synchronously output through the bicubic interpolation calculation module (4) to form a multi-resolution image stream.

8. The image scaling system according to claim 6, wherein: Also includes: Image complexity analysis module (7), responsible for analyzing the currently processed image area and outputting a signal representing the image complexity; A clock management module (8) for dynamically adjusting the clock frequency of the bicubic interpolation calculation module (4) according to the output of the image complexity analysis module (7); A clock interface module (9) is used to receive a clock signal from the clock management module (8) and adjust its operating speed according to changes in the clock frequency; The control logic module (10) receives the output of the image complexity analysis module (7) and sends a corresponding control signal to the clock management module (9) to indicate the adjustment of the clock frequency; and monitors the status of the bicubic interpolation calculation module (4) to ensure that it operates at the correct clock frequency.

Images