Semiconductor structure and its formation method

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate having a device region, a first isolation region, and a second isolation region, wherein the second isolation region is disposed between the device region and the first isolation region; the second isolation region also has a first semiconductor material region disposed adjacent to the first isolation region. The semiconductor structure provided by this disclosure compensates for dimensional differences between the device region and the isolation region caused by differences in pattern density by reserving a portion of the semiconductor material region within the isolation region adjacent to the device region, thereby achieving a semiconductor structure with higher yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used for data storage. DRAM consists of multiple memory cells composed of transistors and capacitors, arranged in an array. Word lines extend along the rows of the array, and bit lines extend along the columns. Word lines can be coupled to transistors in the memory cells. Each memory cell can be uniquely addressed by a combination of one word line and one bit line.

[0003] As the integration of semiconductor devices increases and manufacturing processes are constantly updated, the interaction between various process steps becomes increasingly important for product yield. Summary of the Invention

[0004] This disclosure provides semiconductor structures with higher yields and methods for forming them.

[0005] The technical spirit of this disclosure aims to solve problems not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Some embodiments of this disclosure provide a semiconductor structure, including: a substrate having a device region, a first isolation region, and a second isolation region, the second isolation region being disposed between the device region and the first isolation region; the second isolation region also having a first semiconductor material region disposed adjacent to the first isolation region.

[0007] The device region of the semiconductor structure provided in this embodiment includes a plurality of spaced second semiconductor material regions, a first conductive structure corresponding to each second semiconductor material region, and an isolation structure that isolates each first conductive structure. In the direction perpendicular to the substrate, the extension depth of the isolation structure is less than the extension depth of the first isolation region or the second isolation region, and the extension depth of the second isolation region is not greater than the extension depth of the first isolation region.

[0008] The device region of the semiconductor structure provided in this embodiment further includes a second conductive structure, which is correspondingly disposed with a plurality of second semiconductor material regions. An isolation structure is also disposed between each first conductive structure and the second conductive structure, and the second conductive structure is connected to each corresponding second semiconductor material region.

[0009] The surface of the second conductive structure in the device region of the semiconductor structure provided in this embodiment is not lower than the surfaces of the first isolation region and the second isolation region.

[0010] The first isolation region of the semiconductor structure provided in this disclosure includes at least one isolation material, and the second isolation region includes at least two isolation materials, wherein at least one isolation material in the second isolation region is different from the isolation material in the first isolation region.

[0011] At least one surface of the first semiconductor material region of the semiconductor structure provided in this disclosure embodiment is not exposed by the surface of the second isolation region.

[0012] The semiconductor structure provided in this embodiment includes at least two isolation materials, and the isolation material in the isolation structure is the same as the isolation material in the second isolation region, and at least one isolation material in the isolation structure is different from the isolation material in the first isolation region.

[0013] This disclosure also provides a method for forming a semiconductor structure, including: providing a substrate, patterning the substrate, and forming a first isolation region in the substrate; patterning the substrate and forming a device region and a second isolation region in the substrate, the second isolation region being disposed between the device region and the first isolation region; wherein, when the second isolation region is formed in the patterned substrate, a portion of the substrate located in the second isolation region is retained to form a first semiconductor material region, the first semiconductor material region being disposed adjacent to the first isolation region.

[0014] In the semiconductor structure formation method provided in this disclosure, the substrate has a first surface and a second surface, which are disposed opposite to each other. The substrate is patterned, and a device region and a second isolation region are formed in the substrate. The method includes: patterning the first surface of the substrate; forming a plurality of first trenches and second trenches in the substrate; dividing the substrate by the plurality of first trenches to form a plurality of spaced second semiconductor material regions; filling each of the first trenches and second trenches; forming an isolation structure in each of the first trenches; forming a second isolation region in the second trenches; forming a first conductive structure between the isolation structure and each of the second semiconductor material regions; and forming a device region by the first conductive structure, each of the second semiconductor material regions, and the isolation structure. In the direction perpendicular to the substrate, the extension depth of the isolation structure is less than the extension depth of the second isolation region or the extension depth of the first isolation region, and the extension depth of the second isolation region is not greater than the extension depth of the first isolation region.

[0015] The method for forming a semiconductor structure provided in this disclosure further includes forming a second conductive structure in the device region, including:

[0016] The second surface of the substrate is thinned so that a portion of the substrate in the device region is retained, while the substrates in the first isolation region and the second isolation region are removed; a second conductive structure is formed on the surface of the substrate in the device region, and the second conductive structure connects to the corresponding second semiconductor material regions.

[0017] In the semiconductor structure formation method provided in this embodiment, when thinning the second surface of the substrate, the first isolation region is used as the thinning stop region.

[0018] In the semiconductor structure formation method provided in this disclosure, when the second surface of the substrate is thinned, the second isolation region is not thinned, and the surface of the first semiconductor region is exposed by the surface of the second isolation region.

[0019] The semiconductor structure provided in this disclosure compensates for the size difference between the device region and the isolation region caused by the difference in pattern density by reserving a portion of the semiconductor material region in the isolation region adjacent to the device region, thereby obtaining a semiconductor structure with higher yield. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0021] Figure 1 This is a schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0022] Figure 2 , Figure 4 as well as Figure 6 This is a top view of the semiconductor structure during the formation process.

[0023] Figure 3 , Figure 5 , Figures 7 to 13 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0024] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0025] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely illustrative of the relevant disclosure and not intended to limit it. Furthermore, it should be noted that only relevant parts are shown in the accompanying drawings for ease of description. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first," "second," and "third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects.

[0026] Figure 1 A schematic flowchart illustrating the formation of a semiconductor structure according to some embodiments is shown. The corresponding method for forming a semiconductor structure includes the following steps:

[0027] S11: Provide a substrate, pattern the substrate, and form a first isolation region in the substrate.

[0028] S12: Pattern the substrate to form a device region and a second isolation region in the substrate, the second isolation region being disposed between the device region and the first isolation region; wherein, when the substrate is patterned to form the second isolation region, a portion of the substrate located in the second isolation region is retained to form a first semiconductor material region, the first semiconductor material region being disposed adjacent to the first isolation region.

[0029] The method for forming a semiconductor structure provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0030] First execute S11, see [link / details]. Figure 2 and Figure 3 , Figure 2 This is a schematic top view of a semiconductor structure provided in some embodiments of this disclosure. Figure 3 This is a schematic cross-sectional view of a semiconductor structure provided in some embodiments of this disclosure. The semiconductor structure provided in step S11 includes a substrate 100, and the substrate 100 has a first isolation region 200. The first isolation region 200 disposed in the substrate 100 is mainly used to separate the substrate 100, dividing the substrate 100 into an electrical region and an isolation region. Figure 2 and Figure 3As shown, the substrate 100 can be divided into a device region I and an isolation region II. Device region I is an electrical region comprising multiple substrates 100 extending in the Y direction and isolated from each other in the X direction. The substrates 100 in device region I provide active regions for subsequent semiconductor device formation. The spaced-apart substrates 100 in device region I are isolated from each other by a first dielectric layer 300. Isolation region II is an isolation region containing substrates 100, and a first isolation region 200 is disposed on the substrate 100 of isolation region II. Figure 3 They respectively indicate along Figure 2 The schematic diagram of the cross-sectional structure obtained along lines A1-A2 and B1-B2 is shown. Lines A1-A2 and B1-B2 are parallel to the Y direction, and the X and Y directions are perpendicular to each other. Line A1-A2 is a schematic diagram of the cross-sectional position of the substrate 100 extending along the Y direction and dummy in the substrate 100. Line B1-B2 is a schematic diagram of the cross-sectional position of the substrate 100 extending along the Y direction and dummy between adjacent substrates 100.

[0031] In some embodiments, the step of patterning the substrate 100 and forming the first isolation region 200 in the substrate 100 can be performed by mask deposition, photolithography to define the mask pattern, etching the mask pattern, and transferring the mask pattern to the substrate 100 to form the first isolation region 200.

[0032] In some embodiments, substrate 100 may be made of or may comprise various types of semiconductor materials, including, for example, silicon, germanium, group III to V, or other suitable materials. In some embodiments, substrate 100 is made of silicon (doped or undoped), and in alternative embodiments, substrate 100 is a silicon-on-insulator (SOI) wafer or a silicon carbide wafer. Alternatively, any other suitable semiconductor material may be used for substrate 100, such as semiconductor composite materials, such as gallium arsenide (GaAs), indium phosphide (InP), and any suitable ternary or quaternary semiconductor composite material, such as indium gallium arsenide (InGaAs). In these embodiments, substrate 100 may be a thin or ultrathin substrate or wafer, for example having a thickness ranging from about a few micrometers to about several hundred micrometers, for example, from about 5 μm to about 100 μm, for example having a thickness less than about 100 μm or less than about 50 μm.

[0033] In some embodiments, the material of the first dielectric layer 300 may be a dielectric material such as silicon oxide, silicon nitride, or silicon carbonitride. The material filling the first isolation region 200 may be an insulating dielectric material such as silicon oxide, silicon nitride, or silicon carbonitride, or other types of dielectric materials. In some embodiments, the first dielectric layer 300 and the first isolation region 200 contain the same dielectric material.

[0034] See also Figure 3In some embodiments, the substrate 100 has a first surface 100A and a second surface 100B disposed opposite to the first surface 100A. A first isolation region 200 extends along the first surface 100A to the second surface 100B. In this extension direction, the first isolation region 200 has a first extension depth H1, which is not greater than the extension depth of the substrate 100 in the first region I. In some embodiments, the first surface 100A of the substrate 100 in the device region I is coplanar with the surface of the first isolation region 200, i.e., their surfaces are flush or substantially flush. In these embodiments, the first dielectric layer 300 also extends along a direction perpendicular to the X or Y direction. In this extension direction, the first dielectric layer 300 has a second extension depth H2 in the device region I. The second extension depth H2 can be equal to or approximately equal to the first extension depth H1, for example, the difference between the two is controlled within 10-20 nm; the second extension depth H2 can also be less than the first extension depth H1, for example, the difference between the two is greater than 20 nm.

[0035] Perform step S12 to form a device region and a second isolation region. In some embodiments, forming the device region and the second isolation region includes the following steps:

[0036] S121: A first surface of a patterned substrate, in which a plurality of first trenches and second trenches are formed, and the substrate is divided by the plurality of first trenches to form a plurality of spaced second semiconductor material regions.

[0037] The following is combined with Figure 4 and Figure 5 The above steps will be explained in detail. Figure 4 This is a schematic top view of a semiconductor structure provided in some embodiments of this disclosure. Figure 5 This is a schematic cross-sectional view of a semiconductor structure provided in some embodiments of this disclosure. The first surface of the patterned substrate includes: forming a mask layer 400 on the first surface 100A of the substrate 100, the mask layer 400 further covering the surface of a first isolation region 200. A mask pattern is formed on the mask layer 400, the mask pattern including a mask pattern 402 disposed on a device region I and a mask pattern 401 disposed on the first isolation region 200. A plurality of trenches 403 are formed between the mask patterns 402 on the device region I, each trench 403 exposing the surface of the mask layer 400. No trenches are formed in the mask pattern 401 on the first isolation region 200, that is, the mask pattern 401 completely covers the mask layer 400 on the first isolation region 200. In some embodiments, a trench 404 is further formed between the mask patterns 402 and 401, the mask layer 400 exposed by the trench 404 corresponding to isolation region III in the substrate 100. Figure 5 They respectively indicate along Figure 4The cross-sectional structural diagrams obtained along lines A1-A2 and B1-B2 show that the mask pattern 402 and trench 403 are also formed on the first dielectric layer 300. To more clearly illustrate the correspondence between the mask pattern and the substrate, Figure 4 The mask layer 400 is omitted in the text.

[0038] In some embodiments, the width of trench 403 is smaller than the width of trench 404.

[0039] In some embodiments, isolation region III may have multiple trenches 404, and the number of trenches 404 on isolation region III is less than the number of trenches 403 on device region I. In embodiments of this disclosure, the number of trenches 404 is illustrated as one, but is not limited thereto.

[0040] See also Figure 6 and Figure 7 , Figure 6 This is a schematic top view of a semiconductor structure provided in some embodiments of this disclosure. Figure 7 This is a schematic cross-sectional view of a semiconductor structure provided in some embodiments of this disclosure. After trenches 403 and 404 are formed, an etching process is used to etch the substrate 100 and the first dielectric layer 300 downwards along trenches 403 and 404, forming a first trench 101 and a second trench 103 in the substrate 100. The first trench 101 and the second trench 103 are also simultaneously formed in the first dielectric layer 300. In the Y direction, the first trench 101 divides the substrate 100 on the device region I into a plurality of second semiconductor material regions 102 arranged at intervals; at the same time, the first trench 101 divides the first dielectric layer 300 into a plurality of dielectric structures 105 arranged at intervals. After the formation of the first trench 101 and the second trench 103, the mask layer 400 and the mask patterns thereon are removed.

[0041] In some embodiments, the second semiconductor material region 102 may have the same or different structure as the substrate 100.

[0042] See also Figure 6 and Figure 7 In some embodiments, when the substrate 100 on the isolation region III is etched downward along the trench 404 to form the second trench 103, a portion of the substrate 100 located on the isolation region III is retained to form the first semiconductor material region 104.

[0043] In some embodiments, in device region I, a first trench 101 between adjacent second semiconductor material regions 102 in the Y direction has a third extension depth H3 in the direction along the first surface 100A to the second surface 100B of the substrate 100; in isolation region III, a second trench 103 between adjacent second semiconductor material regions 102 and first semiconductor material regions 104 in the Y direction has a fourth extension depth H4. Furthermore, in device region I, a first trench 101 between adjacent dielectric structures 105 in the Y direction has a fifth extension depth H5; in isolation region III, a second trench 103 between adjacent dielectric structures 105 and the first isolation region 200 in the Y direction has a sixth extension depth H6.

[0044] In some embodiments, the values ​​of the third extension depth H3 to the sixth extension depth H6 are all less than the first extension depth H1. In other embodiments, the values ​​of the third extension depth H3 to the sixth extension depth H6 are also less than the second extension depth H2. In the above embodiments, the third extension depth H3 is less than the fourth extension depth H4, the fifth extension depth H5 is less than the sixth extension depth H6, and the difference between the third extension depth H3 and the fourth extension depth H4 is controlled within a first predetermined numerical range, for example, the difference between the two is between 10nm and 50nm, and the difference between the fifth extension depth H5 and the sixth extension depth is controlled within a second predetermined numerical range, for example, the difference between the two is between 10nm and 50nm. In some embodiments, while the third extension depth H3 is less than the fourth extension depth H4, the fifth extension depth H5 is less than the sixth extension depth H6, and the fourth extension depth H4 is less than the sixth extension depth H6. In other embodiments, the fourth extension depth H4 may be equal to or approximately equal to the sixth extension depth H6, and the difference between the two is controlled within 10nm to 50nm.

[0045] In these embodiments, it is necessary to overcome the problem of different etching rates caused by the non-monomeric nature of the etched material. For example, during the etching process, the etched objects include a substrate and a first dielectric layer isolating the substrates. The substrate and the first dielectric layer exhibit different etching rates. For instance, when the substrate is made of silicon and the first dielectric layer is made of silicon oxide, the etching rate of silicon oxide is greater than that of silicon. This results in a difference between the fourth and sixth extension depths. Furthermore, since the mask pattern density in device region I is greater than that in isolation region III, the difference between the fourth and sixth extension depths will be further amplified due to the etching load effect. An excessively large difference between the two will adversely affect subsequent processes. This phenomenon of over-etching of the material in isolation region III can even lead to the fourth and sixth extension depths H4 being greater than the first extension depth H1. To improve this problem, in these embodiments, when forming the second trench located between the second semiconductor material region and the first isolation region, a portion of the substrate is retained on the sidewall of the second trench to form the first semiconductor material region. The retained first semiconductor material region can alleviate the etching load effect when etching to form the first trench and the second trench, shorten the fourth extension depth and the sixth extension depth, prevent the fourth extension depth or the sixth extension depth from exceeding the first extension depth, and improve the reliability of subsequent processes.

[0046] In some embodiments, the first semiconductor material region 104 is disposed adjacent to the first isolation region 200, such as... Figure 7 As shown, during the etching process, a portion of the substrate adjacent to the first isolation region 200 is retained, and at this time, the surface of the first semiconductor material region 104 is lower than the surface of the first isolation region 200. In other embodiments, the first semiconductor material region 104 may be disposed adjacent to the second semiconductor material region, that is, during the etching process, a portion of the substrate adjacent to the device region I is retained.

[0047] After step S121, step S122 is executed to fill each of the first and second trenches, forming an isolation structure in each of the first trenches and forming a second isolation area in the second trenches.

[0048] The following is combined with Figure 8 and Figure 9 Detailed explanation Figure 8 and Figure 9 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0049] First see Figure 8A second dielectric layer 301 and a third dielectric layer 302 are used to fill the first trench 101 and the second trench 103, respectively. The second dielectric layer 301 and the third dielectric layer 302 form a stacked structure filling the first trench 101 and the second trench 103, wherein the second dielectric layer 301 is formed in the first trench 101 and the second trench 103 before the third dielectric layer 302. In some embodiments, the second dielectric layer 301 and the third dielectric layer 302 are made of different materials. For example, the second dielectric layer 301 can be at least one of silicon oxide, silicon nitride, silicon carbonitride, etc., and the third dielectric layer 302 can be another of silicon oxide, silicon nitride, silicon carbonitride, etc. Figure 8 As shown, the second dielectric layer 301 and the third dielectric layer 302 are also simultaneously formed on the surface of the first isolation region 200.

[0050] See also Figure 9 After filling the first trench 101 and the second trench 103, excess second dielectric layer 301 and third dielectric layer 302 are removed, leaving only portions of the second dielectric layer 301 and third dielectric layer 302 located in the first trench 101 and the second trench 103, as well as the second dielectric layer 301 and third dielectric layer 302 located on the first isolation region 200. The second dielectric layer 301 and third dielectric layer 302 retained in the first trench form an isolation structure 31 in the first trench, and the second dielectric layer 301 and third dielectric layer 302 retained in the second trench form a second isolation region 32 in the second trench. The isolation structure 31 is simultaneously formed between each second semiconductor material region 102 and each dielectric structure 105 in device region I; the second isolation region 32 is simultaneously formed between the second semiconductor material region 102 and the first isolation region 200, and between the dielectric structure 105 and the first isolation region 200 in isolation region III.

[0051] After step S122, step S123 is executed, in which a first conductive structure is formed between the isolation structure and each of the second semiconductor material regions, and the first conductive structure, each of the second semiconductor material regions, and the isolation structure form a device region.

[0052] The following is combined with Figure 10 Detailed explanation of steps S123. Figure 10 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0053] After forming the isolation structure and the second isolation region, a first conductive structure 106 is formed between each of the second semiconductor material regions 102 in device region I. The first conductive structure 106 comprises multiple strands, which extend along the X direction and surround each of the second semiconductor material regions 102. The multiple first conductive structures 106 are spaced apart from each other in the Y direction. In these embodiments, a conduction control layer 107 is also provided between the first conductive structure 106 and each of the second semiconductor material regions 102, and the conduction control layer 107 covers the surface of each of the second semiconductor material regions 102. In the above embodiments, the first conductive structure is also simultaneously formed between each of the dielectric structures 105 in device region I.

[0054] In some embodiments, each second semiconductor material region 102, its corresponding conduction control layer 107, and its corresponding first conductive structure 106 form a transistor structure. That is, the second semiconductor material region 102 can be an active region, the conduction control layer 107 can be a gate dielectric layer, the first conductive structure 106 can be a gate, and the transistor structure formed can be a GAA (GateAll Around) transistor.

[0055] In some embodiments, in order to form the first conductive structure 106 in the device region I, it is necessary to first... Figure 9 Based on this, a portion of the second dielectric layer 301 is etched away along the first surface of the substrate 100 of device region I, thereby forming gaps between each second semiconductor material region 102 and the third dielectric layer 302. Simultaneously, each dielectric structure 105 and the second dielectric layer 301 on line B1-B2 are also partially removed, thereby forming gaps between each third dielectric layer 302 on line B1-B2. After forming these gaps, a dielectric layer is backfilled into the gaps, thereby forming... Figure 10 The dielectric structure 303 shown here forms an isolation structure 31 for each of the first conductive structures 106, consisting of the dielectric structure 303, the second dielectric layer 301, and the third dielectric layer 302. Simultaneously, the dielectric structure 303 is also formed in the second isolation region 32. In some embodiments, the dielectric structure 303 and the third dielectric layer 302 are made of the same material, for example, both are made of silicon oxide, silicon nitride, or silicon carbonitride. In this case, the dielectric structure 303 and the third dielectric layer 302 may not be directly distinguishable in the second isolation region 32 and the isolation structure 31, and there is no clear boundary between them.

[0056] In some embodiments, when backfilling the dielectric structure 303 in these gaps, each gap on the A1-A2 line is completely filled, and the gaps between each third dielectric layer 302 on the B1-B2 line are partially filled. That is, the gaps on the B1-B2 line are only partially filled by the dielectric structure 303. The unfilled gaps are used in subsequent steps to continue etching the second dielectric layer 301 and the window of the dielectric structure 105, providing space for the subsequently formed first conductive structure 106.

[0057] See also Figure 10 After the first conductive structure 106 is formed, the device region I at this time includes the first conductive structure 106, each second semiconductor material region 102, and an isolation structure that isolates each second semiconductor material region 102 and each first conductive structure 106. The isolation structure of device region I includes a second dielectric layer 301, a third dielectric layer 302, and a dielectric structure 303. Since the third dielectric layer 302 and the dielectric structure 303 in device region I use the same material, therefore... Figure 10 The medium structure 303 is used to identify both the third medium layer 302 and the medium structure 303.

[0058] See also Figure 7 and Figure 10 Since the isolation structure and the second isolation region are formed by filling the first trench 101 and the second trench 103, respectively, in some embodiments, the extension depth of the formed isolation structure is less than the extension depth of the second isolation region 32 or less than the extension depth of the first isolation region 200 in the direction along the first surface 100A to the second surface 100B of the substrate 100, i.e., in the direction perpendicular to the substrate 100. In some embodiments, the extension depth of the isolation structure is less than the extension depth of both the first isolation region 200 and the second isolation region 32.

[0059] See also Figure 10 In some embodiments, after forming the isolation structure, the second isolation region, and the first conductive structure, the surface of the semiconductor structure is planarized to remove excess material from the surface of each region, keeping the surfaces of device region I, isolation region II, and isolation region III flush or substantially flush.

[0060] In these embodiments, the surface of the first semiconductor material region 104 adjacent to the first surface 100A of the substrate 100 is covered by the second isolation region 32, that is, the top surface of the first semiconductor material region 104 is not exposed by the second isolation region 32. In other embodiments, the top surface of the first semiconductor material region 104 may also be exposed by the second isolation region 32, that is, the top surface of the first semiconductor material region 104 is coplanar with the top surfaces of the second isolation region 32, the first isolation region 200, and the isolation structure in the device region I.

[0061] In some embodiments, after forming the isolation structure, the second isolation region, and the first conductive structure, a charge storage structure is further formed in the device region I.

[0062] The following is combined with Figure 11 Describe in detail the process of forming a charge storage structure. Figure 11 This is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure. A lower electrode 503, a dielectric layer 502, and an upper electrode 501 are deposited on the surfaces of the formed isolation structure and the second isolation region, respectively. The lower electrode 503 is in electrical contact with each of the second semiconductor material regions 102 in device region I. The dielectric layer 502 covers the surface of the lower electrode 503, and the upper electrode 501 covers the surface of the dielectric layer 502. The upper electrode 501, lower electrode 503, and dielectric layer 502 constitute a charge storage structure. Each first conductive structure 106 in device region I controls the switching between each of the second semiconductor material regions 102 and the charge storage structure. Each first conductive structure 106 can be a word line of a DRAM memory structure. Each second semiconductor material region 102 is responsible for providing a transport channel and charge supply for the charge in the charge storage structure. Each second semiconductor material region 102 can be an active region of a DRAM transistor.

[0063] In some embodiments, see Figure 11 An isolation dielectric layer 500 is formed on the first isolation region 200 and the second isolation region 32. The isolation dielectric layer 500 is used to isolate the charge storage structure from the surrounding environment. The isolation dielectric layer 500 may be made of the same or different material as the first isolation region 200. For example, the isolation dielectric layer 500 may be one or more of silicon oxide, silicon nitride, and silicon carbonitride.

[0064] In some embodiments, after performing step S122, step S123 is further performed. Step S123 includes forming a second conductive structure in the device region, including: thinning the second surface of the substrate such that a portion of the substrate in the device region is retained and the substrates of the first isolation region and the second isolation region are removed; forming a second conductive structure on the surface of the substrate retained in the device region, the second conductive structure being connected to the second semiconductor material region.

[0065] The following is combined with Figure 12 and Figure 13 Describe step S123 in detail. Figure 12 and Figure 13This is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure. After forming the charge storage structure, the semiconductor structure is flipped 180°, and the second surface 100B of the substrate 100 is used as the surface to be processed, and the substrate 100 is thinned. During this process, the bottom of the substrate 100 on the A1-A2 line, i.e., the second semiconductor material region 102, is partially removed, and the retained portion of the substrate is marked as substrate 108. At the same time, the bottom surface of the first semiconductor material region 104 in the second isolation region 32 is also partially removed. The substrate on the first isolation region 200 and the substrate 100 on the B1-B2 line are also removed simultaneously until the dielectric structure 105 is exposed. In some embodiments, during the above thinning process, the surface of the first isolation region 200 is used as a thinning stop region, i.e., when thinning is performed, the thinning process stops when the first isolation region 200 is reached. In the above embodiments, the second isolation region 32 may not be thinned, for example, the thinning process may be stopped at the second dielectric layer 301; the second isolation region 32 may also be thinned, for example, the thinning process may be stopped at the third dielectric layer 302.

[0066] When thinning a semiconductor structure, the difference in the extension depth between the isolation structure and / or the first isolation region in device region I is reduced by retaining a portion of the first semiconductor material region in the second isolation region during the aforementioned process steps. This prevents the second isolation region and the isolation structure from having a deeper extension depth in the direction toward the second surface of the substrate. If the extension depth of the second isolation region and the isolation structure is too deep, during substrate thinning, the second isolation region 32 and the isolation structure will be exposed before the first isolation region 200 and even the substrate 100 as thinning progresses. Only after they are further thinned will the thinning of the substrate 100 and the dielectric structure 105 proceed. This requires further thinning of the isolation structure and / or the dielectric in the second isolation region during the thinning process, introducing serious risks to the thinning process, increasing the cost of the thinning process, and affecting the yield of the process. For example, when the first isolation region 200 is used as the thinning process stop area, only the substrate 100 of device region I, isolation region II, and isolation region III needs to be thinned. This is because the extension depth of the isolation structure, the second isolation region 32, etc., does not exceed the extension depth of the first isolation region 200. The isolation structure and the second isolation region 32, etc., will not adversely affect the thinning process, resulting in better stability of the thinning process. Conversely, when the extension depth of the isolation structure and the second isolation region 32, etc., exceeds that of the first isolation region 200, the thinning process needs to simultaneously thin the substrate 100, the second dielectric layer 301, and even the third dielectric layer 302. In this case, the thinning process needs to balance the thinning uniformity of the silicon substrate, the second dielectric layer, and the third dielectric layer, greatly increasing the process difficulty.

[0067] In the above embodiments, the thinning process can be achieved by chemical mechanical polishing or other surface planarization processes.

[0068] See also Figure 13 A second conductive structure 109 is formed on the thinned substrate 108 in device region I, and the second conductive structure 109 is in direct contact with the substrate 108. The process for forming the second conductive structure 109 can be a conductive thin film deposition process. After the conductive thin film deposition is completed, an annealing process can be performed to achieve an efficient electrical connection between the second conductive structure 109 and the substrate 108. For example, annealing can achieve an ohmic contact between the second conductive structure 109 and the substrate 108.

[0069] In some embodiments, the second conductive structure 109 is formed on the surface of the substrate 108 corresponding to the second semiconductor material region 102. The region between adjacent second semiconductor material regions 102 in the X direction, i.e., the region where the dielectric structure 105 is located, does not have the second conductive structure 109. The second conductive structure 109 is arranged perpendicularly to the first conductive structure 106, and the first conductive structure 106 connects to a plurality of second semiconductor material regions 102 extending in the X direction. The second conductive structure 109 connects to a plurality of second semiconductor material regions 102 extending in the Y direction. The second conductive structure 109 is used to implement read and write operations on the capacitor in the charge storage structure. The second conductive structure 109 can be a bit line of a DRAM memory structure. The number of second conductive structures 109 is the same as that of the first conductive structures 106, and there can be multiple second conductive structures 109. Each first conductive structure 106 extends in the X direction and is spaced apart in the Y direction, and each second conductive structure 109 extends in the Y direction and is spaced apart in the X direction.

[0070] In some embodiments, the material of the first conductive structure 106 may be one or more of the following metals or their silicides: titanium, tungsten, cobalt, nickel, platinum, gold, etc., and the material of the second conductive structure 109 may be one or more of the following metals or their silicides: titanium, tungsten, cobalt, nickel, platinum, gold, etc.

[0071] See also Figure 13 In some embodiments, after the second conductive structure 109 is formed, an isolation dielectric layer 600 is deposited on the surface of the semiconductor structure, and a contact pad 700 is formed in the isolation dielectric layer 600 to interconnect with the second conductive structure 109 in the device region I. The second conductive structure 109 is interconnected with other functional units through the contact pad 700.

[0072] In some embodiments, during the substrate thinning process, one surface of the first semiconductor material region 104 is also exposed, so the second conductive structure 109 may also be formed on the surface of the first semiconductor material region 104.

[0073] Some embodiments of this disclosure also provide a semiconductor structure, the semiconductor structure including: a substrate having a device region, a first isolation region and a second isolation region, wherein the second isolation region is disposed between the device region and the first isolation region; the second isolation region is further disposed with a first semiconductor material region, the first semiconductor material region being disposed adjacent to the first isolation region.

[0074] A schematic diagram of the semiconductor structure can be found here. Figure 13 As shown in the figure, the semiconductor structure includes device region I, isolation region II, and isolation region III, with isolation region III disposed between device region I and isolation region II. Device region I has a substrate 108, which is a semiconductor substrate; isolation region II has a first isolation region 200, and isolation region III has a second isolation region 32. The second isolation region 32 also has a first semiconductor material region 104, which can be disposed adjacent to the first isolation region 200 or adjacent to device region I. Figure 13 The diagram illustrates the arrangement of the first semiconductor material region 104 adjacent to the first isolation region 200.

[0075] In some embodiments, the first semiconductor material region 104 may be part of the substrate 108 or may be made of the same material as the substrate 108.

[0076] In some embodiments, a first semiconductor material region 104 is formed between adjacent second isolation regions 32 and first isolation regions 200 on line A1-A2, and no first semiconductor material region 104 is formed between adjacent second isolation regions 32 and first isolation regions 200 on line B1-B2. At least one surface of the first semiconductor material region 104 is not exposed by the second isolation region 32, that is, at least one surface of the first semiconductor material region 104 is not exposed on the surface of isolation region III. The positions of lines A1-A2 and B1-B2 in the semiconductor structure can be referenced. Figure 3 And a description of the corresponding figures.

[0077] In the semiconductor structure provided in the embodiments of this disclosure, by retaining a portion of the semiconductor material region in the isolation region adjacent to the device region, the size difference caused by the difference in pattern density between the device region and the isolation region is compensated, thereby obtaining a semiconductor structure with higher yield.

[0078] See also Figure 13The device region I of the semiconductor structure includes multiple second semiconductor material regions 102 arranged at intervals in the X and Y directions, first conductive structures 106 corresponding to each second semiconductor material region 102, and isolation structures (301+302+303) that isolate each first conductive structure. The second semiconductor material regions 102 arranged along the Y direction share a common substrate 108, and dielectric structures 105 are disposed between the second semiconductor material regions 102 arranged along the X direction to isolate them. Each first conductive structure 106 extends in the X direction and is isolated from each other along the Y direction. Each first conductive structure 106 extending in the X direction is correspondingly connected to each row of second semiconductor material regions 102 arranged along the X direction. The isolation structures are disposed between adjacent second semiconductor material regions 102 in the X and Y directions and between adjacent first conductive structures 106 in the Y direction, achieving isolation between the second semiconductor material regions 102 and the first conductive structures 106.

[0079] In some embodiments, the first semiconductor material region 104 and the second semiconductor material region 102 are both derived from the substrate 108 or use the same material as the substrate 108.

[0080] In some embodiments, the isolation structure includes a second dielectric layer 301 and a dielectric structure 303. The isolation structure near the substrate 108 includes a stacked structure composed of the second dielectric layer 301 and a third dielectric layer 302, while the isolation structure away from the substrate 108 includes a composite structure composed of the third dielectric layer 302 and the dielectric structure 303. The second dielectric layer 301 and the third dielectric layer 302 can be different dielectric materials; for example, the second dielectric layer 301 may be silicon oxide, and the third dielectric layer 302 may be silicon nitride, or vice versa. The third dielectric layer 302 and the dielectric structure 303 can be the same dielectric material; for example, both may be silicon nitride or silicon oxide.

[0081] In some embodiments, the first isolation region 200 may include at least one isolation material, such as silicon nitride or silicon oxide. In other embodiments, the first isolation region 200 may also include two or more types of isolation materials to achieve better isolation effect.

[0082] In some embodiments, the second isolation region 32 includes at least two isolation materials, such as a stacked structure consisting of a second dielectric layer 301 and a third dielectric layer 302.

[0083] In some embodiments, in the direction perpendicular to the substrate 108, i.e., in the direction perpendicular to the X and Y directions, the extension depth of the isolation structure is less than the extension depth of the first isolation region 200 or the second isolation region 32, and the extension depth of the second isolation region 32 is not greater than the extension depth of the first isolation region 200. The difference in extension depth between the isolation structure and the first or second isolation region in the semiconductor structure obtained by the embodiments of this disclosure can be further reduced, and the excessive extension depth of the second isolation region can be avoided, thereby affecting the performance of the semiconductor structure.

[0084] In some embodiments, the device region I of the semiconductor structure further includes a second conductive structure 109, which is correspondingly disposed with a plurality of second semiconductor material regions 102. There are multiple second conductive structures 109, each extending along the Y direction and spaced apart in the X direction, with the second conductive structures 109 arranged perpendicularly to the first conductive structure 106. Each second conductive structure 109 is connected to a second semiconductor material region 102 arranged in the Y direction. The second conductive structures 109 arranged in rows in the X direction are electrically isolated from each other by a dielectric structure 105. The first conductive structure 106 and the second conductive structure 109 are isolated from each other by an isolation structure, for example, by a second dielectric layer 301.

[0085] In the semiconductor structure provided in the above embodiments, the first conductive structure 106 in device region I can be a word line, the second conductive structure 109 can be a bit line, and the second semiconductor material region 102 can be an active region constituting a transistor. Device region I also includes a conduction control layer 107, which can be the gate dielectric layer of a transistor.

[0086] In some embodiments, device region I further includes a charge storage structure, which consists of an upper electrode 501, a dielectric layer 502, and a lower electrode 503. Each charge storage structure is connected to its corresponding second semiconductor material region 102. The charge storage structure may be a DRAM capacitor.

[0087] In some embodiments, the semiconductor structure further includes an isolation dielectric layer 500 disposed on the first isolation region 200 and / or the second isolation region 32, the isolation dielectric layer 500 being further disposed on the outer periphery of the charge storage structure for isolation of the charge storage structure.

[0088] In the above embodiment, the first conductive structure 106 is disposed between the second conductive structure 109 and the capacitor storage structure.

[0089] In some embodiments, the semiconductor structure further includes an isolation dielectric layer 600, which is disposed on device region I, isolation region II, and isolation region III, covering the second conductive structure 109, dielectric structure 105, first isolation region 200, and second isolation region 32. Contact pads 700 are provided in the isolation dielectric layer 600 for interconnecting the second conductive structure 109 with other functional units.

[0090] In some embodiments, the surface of the second conductive structure 109 is not lower than the surfaces of the first isolation region 200 and the second isolation region 32. Here, the surface of the second conductive structure 109 refers to the surface of the second conductive structure 109 away from the substrate 108, and the surfaces of the first isolation region 200 and the second isolation region 32 also refer to the surfaces in the same direction.

[0091] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, comprising: a substrate having a first surface and a second surface opposite to the first surface, the substrate having a device region; a first isolation region extending from the first surface to the second surface; a second isolation region disposed between the device region and the first isolation region; the second isolation region further having a first semiconductor material region disposed adjacent to the first isolation region, a surface of the first semiconductor material region being lower than a surface of the first isolation region in a direction adjacent to the first surface; the device region comprising a plurality of spaced-apart second semiconductor material regions, a first conductive structure disposed corresponding to each of the second semiconductor material regions, and an isolation structure separating each of the first conductive structures, the isolation structure having a depth of extension less than a depth of extension of the first isolation region or the second isolation region, the depth of extension of the second isolation region being not greater than the depth of extension of the first isolation region; the device region further comprising a second conductive structure disposed corresponding to the plurality of second semiconductor material regions, the isolation structure further being disposed between each of the first conductive structures and the second conductive structure, each of the second conductive structures being connected to a corresponding one of the second semiconductor material regions; a surface of the second conductive structure being not lower than the surfaces of the first isolation region and the second isolation region; the first isolation region comprising at least one isolation material, the second isolation region comprising at least two isolation materials, at least one of the isolation materials in the second isolation region being different from the isolation material in the first isolation region; at least one surface of the first semiconductor material region being not exposed by a surface of the second isolation region; the isolation structure comprising at least two isolation materials, the isolation materials in the isolation structure being the same as the isolation materials in the second isolation region, at least one of the isolation materials in the isolation structure being different from the isolation material of the first isolation region. 8.A method of forming a semiconductor structure, comprising: providing a substrate, and patterning the substrate to form a first isolation region in the substrate; patterning the substrate to form a device region and a second isolation region in the substrate, the second isolation region being disposed between the device region and the first isolation region; wherein, when the substrate is patterned to form the second isolation region, a portion of the substrate located at the second isolation region is retained to form a first semiconductor material region, the first semiconductor material region being disposed adjacent to the first isolation region. the substrate having a first surface and a second surface opposite to the first surface, the substrate being patterned to form a device region and a second isolation region in the substrate, comprising: patterning the first surface of the substrate to form a plurality of first trenches and second trenches in the substrate, the substrate being divided by the plurality of first trenches to form a plurality of spaced-apart second semiconductor material regions; filling each of the first trenches and the second trenches to form an isolation structure in each of the first trenches and the second isolation region in each of the second trenches; ​ ​ 2. The semiconductor structure of claim 1, wherein, ​ 3. The semiconductor structure of claim 2, wherein, ​ 4. The semiconductor structure of claim 3, wherein, ​ 5. The semiconductor structure of claim 1, wherein, ​ 6. The semiconductor structure of claim 1, wherein, ​ 7. The semiconductor structure of claim 1, wherein, ​ ​ ​ ​ ​ 9. The method of forming of claim 8, wherein, ​ ​ ​ A first conductive structure is formed between the isolation structure and each of the second semiconductor material regions, the first conductive structure, each of the second semiconductor material regions and the isolation structure form the device region; wherein, In a direction perpendicular to the substrate, the extension depth of the isolation structure is less than the extension depth of the second isolation region or the extension depth of the first isolation region, the extension depth of the second isolation region is not greater than the extension depth of the first isolation region.

10. The method of forming of claim 9, wherein, Further comprising forming a second conductive structure in the device region, including: Thinning the second surface of the substrate so that part of the substrate of the device region is reserved, the substrate of the first isolation region and the second isolation region is removed; Forming the second conductive structure on the surface of the substrate reserved in the device region, the second conductive structure connects each of the second semiconductor material regions respectively.

11. The method of forming of claim 10, wherein, When thinning the second surface of the substrate, the first isolation region is used as a thinning stop region.

12. The method of forming of claim 10, wherein, When thinning the second surface of the substrate, the second isolation region is not thinned, and the surface of the first semiconductor region is exposed by the surface of the second isolation region.

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