High-speed longitudinal GaN switching device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and particularly discloses a high-speed longitudinal GaN switching device and a preparation method thereof. The high-speed longitudinal GaN switching device comprises an n-type GaN substrate, an n-type GaN layer, an n + GaN layer and an intrinsic GaN layer which are sequentially arranged from bottom to top in the longitudinal direction. The switching device further comprises an AlGaN layer which is horizontally arranged with the intrinsic GaN layer. The switching device further comprises drain electrode metal arranged at the bottom of the n-type GaN substrate, source electrode metal arranged at the top of the junction of the intrinsic GaN layer and the AlGaN, and grid electrode metal arranged on the side portion, away from the intrinsic GaN layer, of the AlGaN. The switching device further comprises a gate medium arranged between the gate metal and the AlGaN and an insulating medium arranged between the gate metal and the n + GaN layer. The parasitic capacitance between the gate metal and the drain metal of the device is shielded, so that the inherent Miller capacitance of the longitudinal device is reduced, and the switching speed of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-speed vertical GaN switch device and a preparation method thereof. Background Art

[0002] As one of the representatives of wide bandgap semiconductor devices, GaN and its high electron mobility transistor (HEMT) use materials such as gallium nitride (GaN) or gallium arsenide (GaAs), which have higher electron mobility than traditional silicon materials and have the characteristics of low drive loss, low on-resistance and high operating frequency. In practical applications, since the voltage withstand capability of lateral devices is determined by the device volume, the distance between the drain and the source is relatively short, and the electric field is concentrated in a small area, it is easy to cause device breakdown, thereby limiting the voltage withstand capability of the device, especially in high voltage applications where the power density of the device is relatively low.

[0003] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0004] The main purpose of the present invention is to provide a high-speed vertical GaN switching device and a preparation method thereof, aiming to solve the technical problem of low power density of lateral switching devices in the prior art.

[0005] To achieve the above object, the present invention provides a high-speed vertical GaN switch device, the high-speed vertical GaN switch device comprising: an n-type GaN substrate, an n-type GaN layer, an n+GaN layer and an intrinsic GaN layer arranged in sequence from bottom to top vertically;

[0006] The high-speed vertical GaN switch device further includes: AlGaN disposed horizontally with the intrinsic GaN layer;

[0007] The high-speed vertical GaN switch device further comprises: a drain metal disposed at the bottom of the n-type GaN substrate, a source metal disposed at the top of the junction of the intrinsic GaN layer and the AlGaN, and a gate metal disposed at the side of the AlGaN away from the intrinsic GaN layer;

[0008] The high-speed vertical GaN switch device further includes: a gate dielectric disposed between the gate metal and the AlGaN layer and an insulating dielectric disposed between the gate metal and the n+GaN layer.

[0009] Optionally, the gate dielectric is Al2O3, and the insulating dielectric is SiO2;

[0010] The top of the gate dielectric is flush with the top of the AlGaN, and the bottom of the gate dielectric is flush with the bottom of the gate metal;

[0011] The top of the insulating medium is flush with the bottom of the gate metal, and the bottom of the insulating medium is flush with the top of the n+GaN layer.

[0012] Optionally, the drain metal, the source metal and the gate metal are made of aluminum-nickel alloy.

[0013] Optionally, setting the doping concentration of the n-type GaN substrate within a first concentration range;

[0014] Setting the doping concentration of the n-type GaN layer within a second concentration range;

[0015] The doping concentration of the n+GaN layer is set within a third concentration range.

[0016] In addition, to achieve the above object, the present invention also proposes a method for preparing a high-speed vertical GaN switch device, which is applied to the preparation of the above high-speed vertical GaN switch device, and the method comprises the following steps:

[0017] Depositing drain metal at the bottom of the n-type GaN substrate;

[0018] epitaxially growing an n-type GaN layer on the n-type GaN substrate;

[0019] depositing an n+GaN layer on the n-type GaN layer;

[0020] Depositing an intrinsic GaN layer and AlGaN on the n+GaN layer;

[0021] Depositing an insulating dielectric, a gate dielectric and a gate metal on the n+GaN layer;

[0022] A source metal is deposited on the intrinsic GaN layer.

[0023] Optionally, the step of depositing an intrinsic GaN layer and AlGaN on the n+GaN layer includes:

[0024] depositing a first barrier layer on the n+GaN layer;

[0025] Etching an intrinsic GaN layer through hole on the first barrier layer to deposit the intrinsic GaN layer in the intrinsic GaN layer through hole;

[0026] removing the first barrier layer, and depositing a second barrier layer on the n+GaN layer;

[0027] An AlGaN through hole is etched on the second barrier layer to deposit the AlGaN in the AlGaN through hole.

[0028] Optionally, the step of depositing an insulating dielectric, a gate dielectric and a gate metal on the n+GaN layer includes:

[0029] removing the second barrier layer, and depositing a third barrier layer on the n+GaN layer;

[0030] Etching an insulating medium through hole on the third barrier layer to deposit the insulating medium in the insulating medium through hole;

[0031] The gate dielectric and the gate metal are deposited on the insulating dielectric.

[0032] Optionally, the step of depositing the gate dielectric and the gate metal on the insulating dielectric includes:

[0033] removing the third barrier layer and re-depositing a fourth barrier layer;

[0034] Etching a gate dielectric through hole on the fourth barrier layer to deposit the gate dielectric in the gate dielectric through hole;

[0035] The gate metal is deposited on the insulating dielectric.

[0036] Optionally, the step of depositing the gate metal on the insulating medium further includes:

[0037] removing the fourth barrier layer and re-depositing a fifth barrier layer;

[0038] A gate metal through hole is etched on the fifth barrier layer to deposit the gate metal in the gate metal through hole.

[0039] The step of depositing a source metal on the intrinsic GaN layer comprises:

[0040] removing the fifth barrier layer, and re-depositing a sixth barrier layer on the AlGaN layer and the intrinsic GaN layer;

[0041] A source metal via is etched on the sixth barrier layer to deposit the source metal in the source metal via.

[0042] The technical solution of the present invention proposes a high-speed vertical GaN switch device and a preparation method thereof. The high-speed vertical GaN switch device comprises: an n-type GaN substrate, an n-type GaN layer, an n+GaN layer and an intrinsic GaN layer arranged in sequence from bottom to top vertically; the high-speed vertical GaN switch device also comprises: AlGaN arranged horizontally with the intrinsic GaN layer; the high-speed vertical GaN switch device also comprises: a drain metal arranged at the bottom of the n-type GaN substrate, a source metal arranged at the top of the junction of the intrinsic GaN layer and the AlGaN, and a gate metal arranged on the side of the AlGaN away from the intrinsic GaN layer; the high-speed vertical GaN switch device also comprises: a gate dielectric arranged between the gate metal and the AlGaN and an insulating dielectric arranged between the gate metal and the n+GaN layer. By shielding the parasitic capacitance between the gate metal and the drain metal of the device, the inherent Maitreya capacitance of the vertical device is reduced, and the switching speed of the device is improved. During the device opening and closing process, electrons flow in one direction, avoiding the on-resistance introduced by the change of current direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic structural diagram of a first embodiment of a high-speed vertical GaN switch device proposed by the present invention;

[0044] Figure 2 A schematic flow chart of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention;

[0045] Figure 3 A first structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention;

[0046] Figure 4 A second structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention;

[0047] Figure 5 A third structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention;

[0048] Figure 6 A fourth structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention;

[0049] Figure 7 A fifth structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention;

[0050] Figure 8 A sixth structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention;

[0051] Fig. 9 It is a seventh structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention;

[0052] Fig.10 It is an eighth structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention;

[0053] Fig.11 This is a ninth structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention.

[0054] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0055] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0058] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0059] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the high-speed vertical GaN switch device proposed by the present invention. Figure 1 A first embodiment of a high-speed vertical GaN switching device of the present invention is proposed.

[0060] In this embodiment, the high-speed vertical GaN switch device includes: an n-type GaN substrate 10, an n-type GaN layer 20, an n+GaN layer 30 and an intrinsic GaN layer 40 arranged in sequence from bottom to top vertically; the high-speed vertical GaN switch device also includes: AlGaN 50 arranged horizontally with the intrinsic GaN layer; the high-speed vertical GaN switch device also includes: a drain metal 101 arranged at the bottom of the n-type GaN substrate, a source metal 301 arranged at the top of the junction between the intrinsic GaN layer and the AlGaN, and a gate metal 201 arranged on the side of the AlGaN away from the intrinsic GaN layer; the high-speed vertical GaN switch device also includes: a gate dielectric 70 arranged between the gate metal and the AlGaN and an insulating dielectric 60 arranged between the gate metal and the n+GaN layer.

[0061] It should be noted that the high-speed vertical GaN switching device adopts a thick epitaxial process and uses a vertical thick epitaxial structure to withstand the drain voltage, which can reduce the lateral expansion of the device and improve the power density of the device. The gate structure of the device adopts the HEMT device structure mechanism, which can effectively suppress the gate capacitance of the device and improve the switching speed of the device. An n+GaN layer is constructed inside the device, which has two functions. The first is to redistribute the electrons from the source through the two-dimensional electron gas to the n+GaN layer in this area, so that the current is more uniform inside the device, and does not gather at the interface of the AlGaN and intrinsic GaN layers, thereby avoiding current concentration and improving device reliability. The second is that it can effectively shield the parasitic capacitance between the gate metal and the drain metal of the device, thereby reducing the inherent Maitreya capacitance of the vertical device and increasing the switching speed of the device. During the device opening and closing process, electrons flow in one direction, avoiding the on-resistance introduced by the change in current direction.

[0062] It should be understood that the gate-drain capacitance of the device, that is, the capacitance from the gate metal to the drain metal, continues to extend downward due to the low doping concentration of the n-type GaN layer, and the capacitance value is relatively large. By adding the n+GaN layer, which has a low resistivity, the other end of the capacitor is directly formed, avoiding the introduction of capacitance due to the n-type GaN layer, thereby reducing parasitic capacitance.

[0063] Among them, the n-type GaN layer is a semiconductor material formed by doping a small amount of donor impurities such as Si, Ge and other elements into the intrinsic semiconductor GaN. The general doping concentration is 1e16cm -3 -5e17cm -3 In the range, the n+GaN layer belongs to the heavily doped n-type GaN layer, that is, the doping concentration of donor impurities is further increased on the basis of n-type GaN, making its electron concentration higher, generally around 1e18cm -3 -5e18cm -3 within the range.

[0064] In one possible implementation, the thickness of the n-type GaN substrate can be set to 1um to ensure the support of the substrate for subsequent processes. The thickness of the n-type GaN layer can be set to 30-50um to ensure the voltage resistance of the device. The thickness of the n+GaN layer can be set to 300nm to ensure a compromise between the process and the current sharing capability. The thickness of the intrinsic GaN layer and the AlGaN layer can be set to 500nm, the width of the intrinsic GaN layer can be set to 300nm, and the width of the AlGaN can be set to 500nm. This is a compromise between the manufacturing process and the realization of the two-dimensional electron gas structure. The thickness of the insulating medium can be set to 100nm, the thickness of the gate medium can be set to 400nm, and the width can be set to 30nm. The thickness of the gate metal can be set to 400nm and the width can be set to 300nm. The gate structure is to ensure the switching characteristics of the device. The insulating medium is to increase the voltage shock from the drain while reducing the gate-drain capacitance of the device. The insulating medium material is SiO 2 , the gate dielectric material is Al 2 O 3 The purpose of the insulating medium is to achieve insulation properties and small capacitance. SiO 2 The gate dielectric material has high requirements on work function, so Al is selected. 2 O 3 , the drain metal, source metal and gate metal are made of aluminum-nickel alloy to ensure the high temperature characteristics and manufacturability of the device.

[0065] It should be understood that the device is turned on when a positive voltage is applied to the gate (greater than the threshold voltage, generally 5V when fully turned on), and electrons flow downward from the two-dimensional electron gas channel of the source metal AlGaN and the intrinsic GaN layer. After reaching the n+GaN layer, the current is evenly distributed laterally in the n+GaN layer, making the current more evenly distributed inside the device, and then flows to the substrate through the n-type GaN layer until it reaches the drain metal. When no voltage is applied to the gate of the device, the large voltage at the drain forms a space charge region withstand voltage from bottom to top in the n-type GaN layer.

[0066] It should be noted that the gate structure of the device adopts the HEMT device structure mechanism, and controls the formation and disappearance of the two-dimensional electron gas in the AlGaN and intrinsic GaN layers through the gate metal and gate dielectric to control the on and off of the device, which can effectively suppress the gate capacitance of the device and improve the switching speed of the device.

[0067] Furthermore, the doping concentration of the n-type GaN substrate can be set to be within a first concentration range (1e18cm -3 -5e18cm -3) to achieve low resistance ohmic contact with the drain metal; setting the doping concentration of the n-type GaN layer to be within the second concentration range (2e16cm -3 -2e17cm -3 ) to achieve a compromise between device withstand voltage and on-resistance; setting the doping concentration of the n+GaN layer to be within a third concentration range (5e17cm -3 -2e18cm -3 ) to ensure the current sharing capability of the n+GaN layer. At the same time, the ratio of Al to GaN in AlGaN is set between 2:8-4:6, and the corresponding device threshold voltage is 1-4V.

[0068] It should be understood that the higher the doping concentration, the lower the on-resistance, but due to the limitation of the critical breakdown field strength of the material, an increase in the doping concentration will lead to an increase in the electric field strength, affecting the withstand voltage of the device. The lower the doping concentration, the higher the withstand voltage and the higher the on-resistance. An n+GaN layer is constructed inside the device, which has two functions. The first is to redistribute the electrons from the source through the two-dimensional electron gas to the n+GaN layer in this area, so that the current is more uniform inside the device, instead of gathering at the interface between the AlGaN and the intrinsic GaN layer, thereby avoiding current concentration and improving device reliability. The second is that it can effectively shield the parasitic capacitance between the gate metal and the drain metal of the device, thereby reducing the inherent Maitreya capacitance of the vertical device and increasing the switching speed of the device. During the device opening and closing process, electrons flow in one direction, avoiding the on-resistance introduced by the change in current direction.

[0069] In this embodiment, the high-speed vertical GaN switch device includes: an n-type GaN substrate, an n-type GaN layer, an n+GaN layer and an intrinsic GaN layer arranged in sequence from bottom to top vertically; the high-speed vertical GaN switch device also includes: AlGaN arranged horizontally with the intrinsic GaN layer; the high-speed vertical GaN switch device also includes: a drain metal arranged at the bottom of the n-type GaN substrate, a source metal arranged at the top of the junction of the intrinsic GaN layer and the AlGaN, and a gate metal arranged on the side of the AlGaN away from the intrinsic GaN layer; the high-speed vertical GaN switch device also includes: a gate dielectric arranged between the gate metal and the AlGaN and an insulating dielectric arranged between the gate metal and the n+GaN layer. By shielding the parasitic capacitance between the gate metal and the drain metal of the device, the inherent Maitreya capacitance of the vertical device is reduced, and the switching speed of the device is improved. During the device opening and closing process, electrons flow in one direction, avoiding the on-resistance introduced by the change of current direction.

[0070] In addition, the present invention also provides a method for preparing a high-speed vertical GaN switching device. Figure 2 , Figure 2The figure is a flow chart of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention.

[0071] In this embodiment, the method for preparing the high-speed vertical GaN switch device includes the following steps:

[0072] Step S10: depositing a drain metal on the bottom of the n-type GaN substrate.

[0073] Reference Figure 3 , Figure 3 This is a first structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention.

[0074] It should be noted that the thickness of the n-type GaN substrate can be set to 1um to ensure the support of the substrate for subsequent processes. The drain metal can be made of aluminum-nickel alloy to ensure the high temperature characteristics and manufacturability of the device. The doping concentration of the n-type GaN substrate can be within the first concentration range (1e18cm -3 -5e18cm -3 ) to achieve low-resistance ohmic contact with the drain metal.

[0075] Step S20: epitaxially growing an n-type GaN layer on the n-type GaN substrate.

[0076] It should be noted that the thickness of the n-type GaN layer can be set to 30-50um to ensure the voltage resistance of the device. The doping concentration of the n-type GaN layer can be within the second concentration range (2e16cm -3 -2e17cm -3 ) to achieve a compromise between device withstand voltage and on-resistance. Figure 4 , Figure 4 This is a second structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention.

[0077] Step S30: depositing an n+GaN layer on the n-type GaN layer.

[0078] It should be noted that the thickness of the n+GaN layer can be set to 300nm to ensure a compromise between the process and the current sharing capability. The doping concentration of the n+GaN layer can be set within the third concentration range (5e17cm -3 -2e18cm -3 ) to ensure the current sharing capability of the n+GaN layer. Figure 5 , Figure 5 This is a third structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention.

[0079] Step S40: depositing an intrinsic GaN layer and AlGaN on the n+GaN layer.

[0080] It should be noted that the thickness of the intrinsic GaN layer and AlGaN can be set to 500nm, the width of the intrinsic GaN layer can be set to 300nm, and the width of AlGaN can be set to 500nm. This is a compromise between the manufacturing process and the realization of the two-dimensional electron gas structure. The ratio of Al to GaN in AlGaN is between 2:8-4:6, and the corresponding device threshold voltage is 1-4V. The gate structure of the device adopts the HEMT device structure mechanism, and controls the formation and disappearance of the two-dimensional electron gas of the AlGaN and intrinsic GaN layers through the gate metal and gate dielectric to control the on and off of the device, which can effectively suppress the gate capacitance of the device and improve the switching speed of the device.

[0081] Specifically, refer to Figure 6 and Figure 7 , Figure 6 This is a fourth structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention. Figure 7 The fifth structural schematic diagram of an embodiment of the method for preparing a high-speed vertical GaN switch device proposed in the present invention. The step of depositing an intrinsic GaN layer and AlGaN on the n+GaN layer may include: depositing a first barrier layer on the n+GaN layer (refer to the dotted line portion in the figure); etching an intrinsic GaN layer through hole on the first barrier layer to deposit the intrinsic GaN layer in the intrinsic GaN layer through hole; removing the first barrier layer and depositing a second barrier layer on the n+GaN layer; etching an AlGaN through hole on the second barrier layer to deposit the AlGaN in the AlGaN through hole.

[0082] Step S50: depositing an insulating dielectric, a gate dielectric and a gate metal on the n+GaN layer.

[0083] It should be noted that the thickness of the insulating medium is 100nm, the thickness of the gate medium is 400nm, the width is 30nm, the thickness of the gate metal is 400nm, and the width is 300nm. The gate structure is to ensure the switching characteristics of the device, and the insulating medium is to increase the voltage impact from the drain while reducing the gate-drain capacitance of the device. The insulating medium material is SiO 2 , the gate dielectric material is Al 2 O 3 The purpose of the insulating medium is to achieve insulation properties and small capacitance. SiO 2 The gate dielectric material has high requirements on work function, so Al is selected. 2 O 3 .

[0084] It should be understood that the n+GaN layer constructed inside the device redistributes the electrons from the source via the two-dimensional electron gas to the n+GaN layer in this area, making the current more uniform inside the device instead of gathering at the interface between the AlGaN and intrinsic GaN layers, thereby avoiding current concentration and improving device reliability. At the same time, it can effectively shield the parasitic capacitance between the gate metal and the drain metal of the device, thereby reducing the inherent Maitreya capacitance of the vertical device and improving the switching speed of the device.

[0085] The step of epitaxially growing an n-type GaN layer on the n-type GaN substrate may include: depositing a first barrier layer on the n-type GaN layer; etching an n+GaN layer through hole on the first barrier layer to perform ion implantation in the n+GaN layer through hole to form the n+GaN layer. The top of the n+GaN layer is flush with the top of the n-type GaN layer.

[0086] Specifically, refer to Figures 8 to 10 , Figure 8 This is a sixth structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention. Fig. 9 This is a seventh structural schematic diagram of an embodiment of a method for preparing a high-speed vertical GaN switch device proposed by the present invention. Fig.10 The eighth structural schematic diagram of an embodiment of the method for preparing a high-speed vertical GaN switch device proposed in the present invention. The second barrier layer is removed, and a third barrier layer is deposited on the n+GaN layer; an insulating dielectric through hole is etched on the third barrier layer to deposit the insulating dielectric in the insulating dielectric through hole; the gate dielectric and the gate metal are deposited on the insulating dielectric. The third barrier layer is removed, and a fourth barrier layer is re-deposited; a gate dielectric through hole is etched on the fourth barrier layer to deposit the gate dielectric in the gate dielectric through hole; the gate metal is deposited on the insulating dielectric.

[0087] Step S60: depositing a source metal on the intrinsic GaN layer.

[0088] It should be noted that the device is turned on when a positive voltage is applied to the gate (greater than the threshold voltage, generally 5V when fully turned on), and electrons flow downward from the two-dimensional electron gas channel of the source metal AlGaN and the intrinsic GaN layer. After reaching the n+GaN layer, the current flows laterally in the n+GaN layer, making the current more evenly distributed inside the device, and then flows to the substrate through the n-type GaN layer until it reaches the drain metal. When no voltage is applied to the gate of the device, the large voltage at the drain forms a space charge region withstand voltage from bottom to top in the n-type GaN layer.

[0089] Reference Fig.11 , Fig.11The ninth structural diagram of an embodiment of the method for preparing a high-speed vertical GaN switch device proposed in the present invention is as follows: the fifth barrier layer is removed, and a sixth barrier layer is re-deposited on the AlGaN and intrinsic GaN layers; a source metal through hole is etched on the sixth barrier layer to deposit the source metal in the source metal through hole.

[0090] In this embodiment, the method for preparing a high-speed vertical GaN switch device may include: depositing a layer of drain metal on an n-type GaN substrate. Epitaxially growing an n-type GaN layer on an n-type GaN substrate. Epitaxially growing an n+GaN layer on the n-type GaN layer. Depositing a barrier layer on the n+GaN layer, etching an intrinsic GaN layer through hole, and depositing and growing an intrinsic GaN layer through the through hole. Removing the original barrier layer, depositing a barrier layer on the n+GaN layer, etching an AlGaN through hole, and depositing and growing AlGaN through the through hole. Removing the original barrier layer, depositing a barrier layer on the n+GaN layer, etching an insulating dielectric through hole, and depositing an insulating dielectric through the through hole. Removing the original barrier layer, re-depositing a barrier layer, etching a gate dielectric through hole, and depositing a gate dielectric through the through hole. Removing the original barrier layer, re-depositing a barrier layer, etching a gate metal through hole, and depositing a gate metal through the through hole. Remove the original barrier layer, deposit a barrier layer, etch the source metal through hole, and deposit the source metal through the through hole. By shielding the parasitic capacitance between the gate metal and the drain metal of the device, the inherent Maitreya capacitance of the vertical device is reduced and the switching speed of the device is improved. During the device opening and closing process, the electrons flow in one direction, avoiding the on-resistance introduced by the change of current direction.

[0091] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0092] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high-speed vertical GaN switching device, characterized in that: The high-speed vertical GaN switch device comprises: an n-type GaN substrate, an n-type GaN layer, an n+GaN layer and an intrinsic GaN layer which are arranged in sequence from bottom to top vertically; The high-speed vertical GaN switch device further includes: AlGaN disposed horizontally with the intrinsic GaN layer; The high-speed vertical GaN switch device further comprises: a drain metal disposed at the bottom of the n-type GaN substrate, a source metal disposed at the top of the junction of the intrinsic GaN layer and the AlGaN, and a gate metal disposed at the side of the AlGaN away from the intrinsic GaN layer; The high-speed vertical GaN switch device further includes: a gate dielectric disposed between the gate metal and the AlGaN layer and an insulating dielectric disposed between the gate metal and the n+GaN layer.

2. The high-speed vertical GaN switch device according to claim 1, characterized in that: The gate dielectric is Al2O3, and the insulating dielectric is SiO2; The top of the gate dielectric is flush with the top of the AlGaN, and the bottom of the gate dielectric is flush with the bottom of the gate metal; The top of the insulating medium is flush with the bottom of the gate metal, and the bottom of the insulating medium is flush with the top of the n+GaN layer.

3. The high-speed vertical GaN switch device according to claim 2, characterized in that: The drain metal, the source metal and the gate metal are made of aluminum-nickel alloy.

4. The high-speed vertical GaN switch device according to claim 3, characterized in that: Setting the doping concentration of the n-type GaN substrate within a first concentration range; Setting the doping concentration of the n-type GaN layer within a second concentration range; The doping concentration of the n+GaN layer is set within a third concentration range.

5. A method for preparing a high-speed vertical GaN switch device, applied to the preparation of the high-speed vertical GaN switch device according to any one of claims 1 to 4, characterized in that: The preparation method comprises the following steps: Depositing drain metal at the bottom of the n-type GaN substrate; epitaxially growing an n-type GaN layer on the n-type GaN substrate; depositing an n+GaN layer on the n-type GaN layer; Depositing an intrinsic GaN layer and AlGaN on the n+GaN layer; Depositing an insulating dielectric, a gate dielectric and a gate metal on the n+GaN layer; A source metal is deposited on the intrinsic GaN layer.

6. The preparation method according to claim 5, characterized in that: The step of depositing an intrinsic GaN layer and AlGaN on the n+GaN layer comprises: depositing a first barrier layer on the n+GaN layer; Etching an intrinsic GaN layer through hole on the first barrier layer to deposit the intrinsic GaN layer in the intrinsic GaN layer through hole; removing the first barrier layer, and depositing a second barrier layer on the n+GaN layer; An AlGaN through hole is etched on the second barrier layer to deposit the AlGaN in the AlGaN through hole.

7. The preparation method according to claim 6, characterized in that: The step of depositing an insulating dielectric, a gate dielectric and a gate metal on the n+GaN layer comprises: removing the second barrier layer, and depositing a third barrier layer on the n+GaN layer; Etching an insulating medium through hole on the third barrier layer to deposit the insulating medium in the insulating medium through hole; The gate dielectric and the gate metal are deposited on the insulating dielectric.

8. The preparation method according to claim 7, characterized in that: The step of depositing the gate dielectric and the gate metal on the insulating dielectric comprises: removing the third barrier layer and re-depositing a fourth barrier layer; Etching a gate dielectric through hole on the fourth barrier layer to deposit the gate dielectric in the gate dielectric through hole; The gate metal is deposited on the insulating dielectric.

9. The preparation method according to claim 8, characterized in that: The step of depositing the gate metal on the insulating medium further includes: removing the fourth barrier layer and re-depositing a fifth barrier layer; A gate metal through hole is etched on the fifth barrier layer to deposit the gate metal in the gate metal through hole.

10. The preparation method according to claim 9, characterized in that: The step of depositing a source metal on the intrinsic GaN layer comprises: removing the fifth barrier layer, and re-depositing a sixth barrier layer on the AlGaN layer and the intrinsic GaN layer; A source metal via is etched on the sixth barrier layer to deposit the source metal in the source metal via.

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