Gallium nitride enhanced vertical transistor with high-k insulation CBL and preparation method of gallium nitride enhanced vertical transistor

Abstract

The invention discloses a gallium nitride enhanced vertical transistor with a high-k insulation CBL and a preparation method thereof, and mainly solves the problems of difficult p-type ion implantation process, serious current leakage phenomenon and insufficient voltage endurance capability of the existing gallium nitride-based power device. The GaN / GaN heterojunction field effect transistor comprises a bottom drain electrode (1), a heavily-doped N-type GaN substrate (2), a lightly-doped N-type GaN drift region (3), a gallium nitride current aperture (4), a current blocking layer (5), an N-type GaN channel layer (6), an AlGaN barrier layer (7), a SiN passivation layer (8), a grid electrode (9) and a source electrode (10) from bottom to top, wherein the grid electrode (9) and the source electrode (10) are parallel to each other at the top. The current blocking layer adopts a high-k insulating medium, and the top gate adopts a groove structure to extend into the AlGaN barrier layer so as to exhaust two-dimensional electron gas. According to the invention, p-type ion implantation is avoided, and the device has good performances of small leakage current and high voltage resistance in a turn-off state, and can be used in the fields of power management power devices, aerospace, charging piles and the like.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a gallium nitride enhanced vertical transistor, which can be used in power management power devices, aerospace, charging piles and other fields. Background Art

[0002] As a wide bandgap semiconductor material, gallium nitride has shown great application potential in power management power devices, aerospace and other fields due to its excellent physical properties, such as high critical electric field, excellent electron mobility and saturation velocity, and relatively high thermal conductivity. At present, lateral gallium nitride devices have been successfully commercialized, with voltage coverage extending from 15V to 900V, and examples of 10kV have been demonstrated. Compared with planar GaN devices, vertical GaN devices have several significant advantages. First, its current channel is located in the body of the device, so it is less disturbed by surface trap states, thereby ensuring more stable dynamic performance. Secondly, vertical structure devices can improve the withstand voltage by simply increasing the thickness of the drift region without expanding the device area, which makes it easier to achieve high breakdown voltage. In addition, the structure also has a large current conduction path area, which is sufficient to withstand high current density. Finally, because the current is more evenly distributed inside the device, the thermal stability of vertical structure devices is also better.

[0003] For conventional GaN vertical current aperture transistors, most of the voltage is borne by the reverse biased pn junction formed between the p-type current blocking layer and the n-type drift layer, and the vertical electric field strength will gradually decrease as it moves away from the pn junction surface. When the peak electric field in the device reaches the critical electric field or the leakage current reaches the threshold, the width of the depletion region in the n-GaN drift layer determines the breakdown voltage of the device. However, when the thickness of the n-GaN drift layer exceeds a certain value, the width of the depletion region in the n-GaN reaches saturation during breakdown, and the breakdown voltage of the device also reaches saturation, limiting the application of GaN vertical transistors under high withstand voltage conditions. In addition, Mg ions are currently the most ideal impurities for achieving p-type doping, but their activation energy is too high, which makes activation difficult, and the selective p-type ion injection of traditional current blocking layers is still a problem. At the same time, the current blocking effect of p-GaN depends on the quality of the p-GaN layer, and the reverse biased pn junction itself has a small current passing through it, and current leakage cannot be avoided.

[0004] Niraj Man Shrestha et al. proposed a GaN vertical device that introduced the insulating material SiO2 as a current blocking layer, such as Figure 1As shown in the figure, the insulating material current blocking layer is inserted into the drift region, and a planar gate is used on top. The device avoids the difficulty of p-type ion implantation of GaN, effectively suppresses vertical leakage under high drain bias, and increases the breakdown voltage to 1270V. However, due to the natural conduction of the two-dimensional electron gas channel inside the device, the device is a depletion-type device, which increases the complexity of circuit design in the circuit and reduces the reliability of the system.

[0005] Jiancheng Ma et al. proposed a gallium nitride current aperture transistor with a superjunction structure, which greatly improves the device's voltage resistance through an internal step-doped columnar p-type superjunction. Although the device has the advantages of high breakdown voltage and low on-resistance, it is difficult to achieve because it requires high-energy, high-dose p-type ion implantation and precisely controlled doping to realize the p-type current blocking layer.

[0006] Patent document with publication number CN106252404B discloses a longitudinally enhanced MISHEMT device with a high-K dielectric groove, such as Figure 2 As shown, a high-K dielectric material is introduced under the source electrode, and the high-K dielectric material extends to the buffer layer; a barrier layer with a conductivity type opposite to that of the buffer layer is introduced under the channel layer, and the barrier layer contacts both sides of the gate. The device modulates the internal electric field and reduces the on-resistance by two-dimensional depletion of the buffer layer. However, its structure still requires high-quality p-type ion implantation to realize the current blocking layer, and the layer structure is complex and the process is difficult to implement, so it is not practical. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and provide a gallium nitride enhanced vertical transistor with a high-k insulating CBL and a preparation method, so as to improve the internal electric field distribution of the device and increase the breakdown voltage; and to reduce the reverse leakage of the device to a greater extent while avoiding gallium nitride p-type ion injection, thereby improving energy utilization efficiency.

[0008] To achieve the above object, the technical solution of the present invention includes:

[0009] 1. A gallium nitride enhancement mode vertical transistor with a high-k insulating CBL, comprising a bottom drain, a heavily doped N-type GaN substrate, a lightly doped N-type GaN drift region, a gallium nitride current aperture, a current blocking layer, an N-type GaN channel layer, an AlGaN barrier layer, a SiN passivation layer, a top gate, and a top source, characterized in that:

[0010] The current blocking layer adopts a high-k insulating medium to avoid P-type ion injection, weaken the internal electric field of the device, and increase the breakdown voltage of the device;

[0011] The top gate adopts a trench structure to reduce the thickness of the AlGaN barrier layer below the gate, deplete the two-dimensional electron gas, and realize an enhanced device.

[0012] Furthermore, the bottom drain, the heavily doped N-type GaN substrate, and the lightly doped N-type GaN drift region are arranged from bottom to top;

[0013] The gallium nitride current aperture is located at the center of the lightly doped N-type GaN drift region;

[0014] The current blocking layer is located on both sides of the gallium nitride current aperture;

[0015] The N-type GaN channel layer is located above the current blocking layer and the GaN current aperture; the upper part of the N-type GaN channel layer is the AlGaN barrier layer and the SiN dielectric layer in sequence;

[0016] The top gate penetrates into the AlGaN barrier layer to form a trench gate;

[0017] The top source is located on both sides of the AlGaN barrier layer and the SiN dielectric layer;

[0018] The SiN dielectric layer is located between the top gate and the top source for isolation.

[0019] Furthermore, the top source and the bottom drain are both ohmic contacts; the top gate is a Schottky contact; the top source and the bottom drain are both made of Ti / Al / Ni / Au or Mo / Al / Mo / Au alloy; the top gate is made of Ni / Au or Ti / Au alloy with a larger work function.

[0020] Furthermore, the heavily doped N-type GaN substrate has a doping concentration of 5×10 19 cm -3 ~1×10 20 cm -3 The lightly doped N-type GaN drift region has a thickness of 8um to 15um and a doping concentration of 8×10 15 cm -3 ~1×10 16 cm -3 .

[0021] Furthermore, the gallium nitride current aperture has a width of 3um to 5um; the current blocking layer is made of one of SiN, HfO2, and TiO2 materials, has a width of 4um to 6um, and a thickness of 1um to 3um.

[0022] Furthermore, the thickness of the N-type GaN channel layer is 30nm to 50nm; the thickness of the AlGaN barrier layer is 10nm to 20nm; the length of the top gate is 20nm to 3um, the depth is 150nm to 200nm, and the distance between the top gate and the top source is 2um to 5um.

[0023] 2. A method for preparing a gallium nitride enhanced vertical transistor with a high-k insulating CBL, comprising:

[0024] S1) Based on a GaN self-supporting substrate, epitaxially growing N-type GaN on the substrate as a device drift layer;

[0025] S2) forming a current through hole above the drift region by dry etching technology;

[0026] S3) depositing a current blocking layer at both sides of the through hole using PECVD technology;

[0027] S4) directly growing a GaN channel layer on the GaN through hole and the current blocking layer by MOVPE, and then growing an AlGaN barrier layer on the channel layer;

[0028] S5) performing groove etching on the grown AlGaN barrier layer;

[0029] S6) depositing metal in the etched groove to form a top gate and a top source, and performing contact annealing;

[0030] S7) depositing a SiN passivation layer on the upper layer of the AlGaN barrier layer for isolation protection;

[0031] S8) growing a drain metal on the back of the substrate and annealing it to complete the device fabrication.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] Firstly, compared with the traditional CAVET structure, the current blocking layer in the present invention can avoid p-type ion injection due to the use of high-k insulating dielectric material, significantly reducing the reverse bias leakage phenomenon of the pn junction, thereby effectively improving the current switching ratio of the device, further reducing energy loss, and improving the overall performance of the device; at the same time, the insulating medium can partially weaken the internal electric field of the device, so that the upper limit of the breakdown voltage of the device is significantly improved, thereby providing a safer and more stable performance guarantee for high-voltage applications.

[0034] Secondly, the present invention uses a structure in which the trench gate penetrates deep into the AlGaN barrier layer, thereby locally thinning the barrier layer thickness, thereby reducing the two-dimensional electron gas concentration generated by the polarization effect under the gate, making the two-dimensional electron gas discontinuous in the channel layer without an external bias, thereby realizing a stable and reliable enhancement-mode device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a diagram of the GaN vertical device structure of the existing SiO2 current blocking layer;

[0036] Figure 2 This is the structure diagram of the existing vertical enhancement type MIS HEMT device with high-K dielectric groove;

[0037] Figure 3 is a structural diagram of the device of the present invention;

[0038] Figure 4 It is a schematic flow chart of the method for preparing the device of the present invention;

[0039] Figure 5 Schematic diagram of two-dimensional electron gas distribution when there is no external bias in three example devices of the present invention;

[0040] Figure 6 1 is a diagram showing the internal electric field strength distribution of the device according to Example 1 of the present invention. DETAILED DESCRIPTION

[0041] The technical solution of the present invention will be clearly and completely described below in conjunction with the drawings and embodiments. The described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0042] Reference Figure 3 The present invention is a gallium nitride enhanced vertical transistor with a high-k insulating CBL, comprising a bottom drain 1, a GaN substrate 2, a GaN drift region, a gallium nitride current aperture 4, a current blocking layer 5, an N-type GaN channel layer 6, an AlGaN barrier layer 7, a SiN passivation layer 8, a top gate 9, and a top source 10. Among them: the top source 10 and the bottom drain 1 are both ohmic contacts, and the top gate 9 is a Schottky contact.

[0043] The GaN substrate 2 has a thickness of 8um to 15um and a doping concentration of 5×10 19 cm -3 ~1×10 20 cm -3 , N-type heavily doped to provide good conductivity.

[0044] The GaN drift region 3 is located on the upper part of the GaN substrate 2 and has a thickness of 8um to 15um. The doping concentration is 8×10 15 cm -3 ~1×10 16 cm -3 The N-type light doping is used to balance the stress during the epitaxial growth process and improve the device's voltage resistance.

[0045] The gallium nitride current aperture 4 is located between two current blocking layers 5 on the upper part of the GaN drift region 3 , has a width of 3 um to 5 um, and has the same doping concentration as that of the N-type GaN drift region 3 .

[0046] The current blocking layer 5 is made of one of SiN, HfO2, and TiO2 materials, has a width of 4um to 6um, and a thickness of 1um to 3um, and is located on both sides of the upper part of the GaN drift region 3 to limit the vertical flow path of the current.

[0047] The N-type GaN channel layer 6 is located on the upper part of the current blocking layer 5 and has a thickness of 30 nm to 50 nm, and is used to provide a conductive channel.

[0048] The AlGaN barrier layer 7 is located on the upper part of the N-type GaN channel layer 6 and has a thickness of 10 nm to 20 nm. It is used to generate two-dimensional electron gas through polarization effect.

[0049] The SiN passivation layer 8 is located on both sides of the upper part of the AlGaN barrier layer 7 and has a thickness of 500nm-1um, and is used for isolation protection.

[0050] The top gate 9 is made of Ni / Au or Ti / Au metal alloy with a large work function, has a trench structure with a length of 20nm-3um and a depth of 150nm-200nm, and is located in the middle of the upper part of the AlGaN barrier layer 7 .

[0051] The top source 10 is made of Ti / Al / Ni / Au or Mo / Al / Mo / Au metal alloy. The top source 10 is located on both sides of the top gate 9 and the distance between the top source 10 and the top gate 9 is 2um to 5um.

[0052] The bottom drain 1 is located on the lower surface of the GaN substrate 2 and is made of Ti / Al / Ni / Au or Mo / Al / Mo / Au metal alloy.

[0053] Reference Figure 4 The present invention provides three embodiments for fabricating a GaN enhanced vertical transistor with a high-k insulating CBL.

[0054] Embodiment 1: The current blocking layer 5 is made of high-k insulating dielectric SiN, the top gate 9 has a length of 20nm and a depth of 150nm, the top gate 9 is made of Ni / Au metal alloy, the top source 10 and the bottom drain 1 are both made of Ti / Al / Ni / Au metal alloy, and the distance between the top source 10 and the top gate 9 is 2um to form a gallium nitride enhanced vertical transistor.

[0055] Step 1, depositing a drift layer 3 on a substrate 2, such as Figure 4 (a).

[0056] Based on the GaN self-supporting substrate 2, the process conditions are set to 400°C, 46mTorr, 4300sccm of hydrogen, 4300sccm of ammonia, and 20umol / min of gallium source. The MOVPE technology is used to deposit an epitaxial doping concentration of 8×10 15 cm -3 , an N-type GaN drift layer 3 with a thickness of 8um.

[0057] Step 2, etching the current through hole 4, such as Figure 4 (b).

[0058] The process conditions are set to an etching power of 150 W, a chlorine gas flow rate of 10 sccm, and a pressure of 12 mTorr, and the two sides of the drift layer 3 are etched by dry etching technology to form a current through hole 4 with a width of 3 um above the drift layer 3 .

[0059] Step 3, depositing a current blocking layer 5, such as Figure 4 (c).

[0060] The process conditions are set to 430° C., 1700 mTorr, 2800 W of power, and 2000 sccm of total gas flow rate, and a SiN current blocking layer 5 with a thickness of 1 um is deposited on both sides of the through hole using PECVD technology.

[0061] Step 4, growing a GaN channel layer 6 and an AlGaN barrier layer 7, such as Figure 4 (d).

[0062] The process conditions are set at a temperature of 400° C. and a pressure of 46 mTorr. The MOVPE technology is used to directly grow a 30 nm thick GaN channel layer 6 on the GaN through hole 4 and the current blocking layer 5, and then grow a 10 nm thick AlGaN barrier layer 7 on the channel layer.

[0063] Step 5, etching the groove of the AlGaN barrier layer 7, such as Figure 4 (e).

[0064] The process conditions are set as etching power of 150 W, chlorine gas flow rate of 10 sccm, and pressure of 12 mTorr, and a dry etching technique is used to perform etching with a depth of 5 nm on the grown AlGaN barrier layer 7 to form three parallel grooves.

[0065] Step 6, depositing the top gate 9 and the top source 10, as shown in Figure 4 (f).

[0066] The annealing temperature was set to 300 °C and the ambient gas was N 2, and the annealing time is 50s. Metals are deposited in the middle groove and the grooves on both sides of the etched AlGaN barrier layer 7 to form a top gate 9 and a top source 10, and annealed. The top gate 9 adopts Ni / Au metal alloy, with a length of 20nm and a depth of 150nm; the top source 10 adopts Ti / Al / Ni / Au metal alloy, and the distance between the top source 10 and the top gate 9 is 2um.

[0067] Step 7, depositing a SiN passivation layer 8, such as Figure 4 (g).

[0068] The process conditions are set to 430° C., 1700 mTorr, 2800 W of power, and 2000 sccm of total gas flow rate. The SiN passivation layer 8 is deposited on the AlGaN barrier layer 7 by PECVD technology for isolation protection.

[0069] Step 8, depositing drain metal 1, such as Figure 4 (h).

[0070] Ti / Al / Ni / Au composite metal is deposited on the back of substrate 2 to form drain 1, and the temperature is set to 300°C and the ambient gas is N 2 The device is annealed under the process condition of annealing time of 50s to complete the device manufacturing.

[0071] Embodiment 2: The current blocking layer 5 is made of high-k insulating dielectric HfO2, the top gate 9 has a length of 500nm and a depth of 180nm, the top gate 9 is made of Ni / Au metal alloy, the top source 10 and the bottom drain 1 are both made of Ti / Al / Ni / Au metal alloy, and the distance between the top source 10 and the top gate 9 is 3um to form a gallium nitride enhanced vertical transistor.

[0072] Step 1: deposit a drift layer 3 on the substrate 2, such as Figure 4 (a).

[0073] Based on GaN self-supporting substrate 2, hydride vapor phase epitaxy technology HVPE is used to epitaxially grow the GaN substrate 2 with a doping concentration of 9×10 15 cm -3 , N-type GaN with a thickness of 10um is used as the device drift layer 3.

[0074] The process conditions of the hydride vapor phase epitaxy technology HVPE are: temperature of 450° C., pressure of 47 mTorr, hydrogen flow rate of 4300 sccm, ammonia flow rate of 4300 sccm, and gallium source flow rate of 20 umol / min.

[0075] Step 2: etching the current through hole 4, such as Figure 4 (b).

[0076] The two sides of the drift layer 3 are etched by dry etching technology to form a current through hole 4 with a width of 4 um above the drift layer 3 .

[0077] The process conditions of the dry etching are: etching power of 200W, chlorine gas flow rate of 15sccm, and pressure of 13mTorr.

[0078] Step three, depositing a current blocking layer 5, such as Figure 4 (c).

[0079] A HfO2 current blocking layer 5 with a thickness of 2 μm is deposited on both sides of the current through hole 4 using PECVD technology.

[0080] The process conditions of the PECVD technology are: temperature of 440°C, pressure of 1700mTorr, power of 3000w, and total gas flow of 2000sccm.

[0081] Step 4: grow a GaN channel layer 6 and an AlGaN barrier layer 7, such as Figure 4 (d).

[0082] 4.1) A GaN channel layer 6 with a thickness of 40 nm is directly grown on the GaN through hole 4 and the current blocking layer 5 using MOVPE technology.

[0083] 4.2) An AlGaN barrier layer 7 with a thickness of 15 nm is grown on the channel layer 6 using MOVPE technology.

[0084] The process conditions of the MOVPE technology are: temperature of 450° C. and pressure of 47 mTorr.

[0085] Step 5: etching the groove of the AlGaN barrier layer 7, such as Figure 4 (e).

[0086] Groove etching is performed on the grown AlGaN barrier layer 7 , with an etching depth of 7 nm, an etching power of 150 W, a chlorine gas flow rate of 10 sccm, and a pressure of 12 mTorr, to form three parallel grooves in the barrier layer 7 .

[0087] Step 6: deposit the top gate 9 and the top source 10, as shown in FIG. Figure 4 (f).

[0088] 6.1) Metal is deposited in the middle groove of the etched AlGaN barrier layer 7 to form a top gate 9. The top gate 9 is made of Ni / Au metal alloy and has a length of 500 nm and a depth of 180 nm.

[0089] 6.2) A metal top source 10 is deposited in two grooves on both sides of the top gate 9 and annealed, and the distance between the top source 10 and the top gate 9 is 3 um. The top source 10 is made of Ti / Al / Ni / Au metal alloy.

[0090] The process conditions of the annealing technology are: annealing temperature is 500°C, ambient gas is N 2 , annealing time is 40s.

[0091] Step 7: deposit a SiN passivation layer 8, such as Figure 4 (g).

[0092] The SiN passivation layer 8 is deposited on the upper surface of the AlGaN barrier layer 7 by using PECVD technology for isolation protection.

[0093] The process conditions of the PECVD technology are: process temperature of 440°C, pressure of 1700mTorr, power of 3000w, and total gas flow rate of 2000sccm.

[0094] Step eight, depositing drain metal 1, such as Figure 4 (h).

[0095] 8.1) growing a drain metal 1 on the back of the substrate 2, wherein the drain metal 1 is made of a Ti / Al / Ni / Au metal alloy;

[0096] 8.2) Anneal the device after the above steps. The annealing process conditions are: annealing temperature is 500℃, ambient gas is N 2 , annealing time is 40s, and device fabrication is completed.

[0097] Embodiment 3: The current blocking layer 5 is made of high-k insulating dielectric TiO2, the top gate 9 has a length of 1um and a depth of 200nm, the top gate 9 is made of Ti / Au metal alloy, the top source 10 and the bottom drain 1 are both made of Mo / Al / Mo / Au metal alloy, and the distance between the top source 10 and the top gate 9 is 5um to form a gallium nitride enhanced vertical transistor.

[0098] Step A, depositing a drift layer 3 on a substrate 2, such as Figure 4 (a).

[0099] Under the process conditions of temperature of 500℃, pressure of 48mTorr, hydrogen flow rate of 4300sccm, ammonia flow rate of 4300sccm, and gallium source flow rate of 20umol / min, based on GaN self-supporting substrate, molecular beam epitaxy (MBE) technology was used to epitaxially grow the doping concentration of 1×10 16 cm -3 , N-type GaN with a thickness of 15um is used as the device drift layer 3.

[0100] Step B, etching the current through hole 4, such as Figure 4 (b).

[0101] Under the process conditions of etching power of 300 W, chlorine gas flow of 20 sccm and pressure of 14 mTorr, both sides of the drift layer 3 are etched by dry etching technology to form a current through hole 4 with a width of 5 um on the drift layer 3 .

[0102] Step C, depositing a current blocking layer 5, such as Figure 4 (c).

[0103] Under the process conditions of temperature of 450°C, pressure of 1700mTorr, power of 3500w and total gas flow of 2000sccm, a TiO2 current blocking layer 5 with a thickness of 3um is deposited on both sides of the current through hole 4 using PECVD technology.

[0104] Step D, growing a GaN channel layer 6 and an AlGaN barrier layer 7, such as Figure 4 (d).

[0105] Under the process conditions of a temperature of 500° C. and a pressure of 48 mTorr, a 50 nm thick GaN channel layer 6 is directly grown on the GaN through hole 4 and the current blocking layer 5 by MOVPE technology, and then a 20 nm thick AlGaN barrier layer 7 is grown on the channel layer 6 .

[0106] Step E, etching the groove of the AlGaN barrier layer 7, such as Figure 4 (e).

[0107] Under the process conditions of etching power of 150 W, chlorine gas flow rate of 10 sccm and pressure of 12 mTorr, the grown AlGaN barrier layer 7 is etched to a depth of 10 nm to form a middle groove and two grooves on both sides of the barrier layer 7 .

[0108] Step F, depositing the top gate 9 and the top source 10, such as Figure 4 (f).

[0109] The annealing temperature is 850°C and the ambient gas is N 2 Under the process condition of annealing time of 30s, metals are deposited in three grooves of the etched AlGaN barrier layer 7 to form a top gate 9 and a top source 10 and annealed, wherein:

[0110] A Ti / Au alloy with a metal length of 1um and a depth of 200nm is deposited in the middle groove to form a gate.

[0111] Mo / Al / Mo / Au metal alloy is deposited in the grooves on both sides to form a source electrode, and the distance between the top source electrode 10 and the top gate electrode 9 on both sides is 5 um.

[0112] Step G, depositing a SiN passivation layer 8, such as Figure 4 (g).

[0113] Under the process conditions of temperature of 450°C, pressure of 1700mTorr, power of 3500w and total gas flow of 2000sccm, PECVD technology is used to deposit a SiN passivation layer 8 between the top source 10 and the top gate 9 on the upper surface of the AlGaN barrier layer 7 for isolation protection.

[0114] Step H, depositing drain metal 1, such as Figure 4 (h).

[0115] Mo / Al / Mo / Au metal alloy is deposited on the back of substrate 2 to form drain metal 1, and annealed at 850°C in an ambient gas of N 2 , annealing is carried out under process conditions with an annealing time of 30s to complete device manufacturing.

[0116] The effect of the present invention is further illustrated by the following simulation experiment:

[0117] Simulation 1, using Silvaco simulation software to simulate the two-dimensional electron gas distribution of the device in Example 1 of the present invention, the result is as follows Figure 5 As shown. Figure 5 It can be seen that in the device of the present invention, since the trench gate 9 penetrates deep into the AlGaN barrier layer 7, the thickness of the barrier layer is locally thinned, thereby reducing the concentration of the two-dimensional electron gas generated by the polarization effect under the gate, so that the two-dimensional electron gas is discontinuous in the channel layer without an external bias, thereby realizing a stable and reliable normally-off device.

[0118] Simulation 2, using Silvaco simulation software to simulate the internal electric field intensity distribution of the device of Example 1 of the present invention, the results are as follows Figure 6 As shown. Figure 6 It can be seen that SiN, as a high-k dielectric, has a much higher dielectric constant than GaN or SiO2, and therefore has better withstand voltage characteristics. The different dielectric constants of different materials in the device lead to discontinuity of the internal electric field, causing part of the high electric field to fall on the current blocking layer, that is, Figure 6 In the darkest part, the drift layer withstands lower voltage, thereby increasing the device breakdown voltage.

[0119] The above descriptions are only a few specific examples of the present invention and do not constitute any limitation to the present invention. It is obvious that for professionals in this field, after understanding the content and principles of the present invention, they may make various modifications and changes in form and details without departing from the principles and structures of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A gallium nitride enhanced vertical transistor with a high-k insulating CBL, comprising a bottom drain (1), a heavily doped N-type GaN substrate (2), a lightly doped N-type GaN drift region (3), a gallium nitride current aperture (4), a current blocking layer (5), an N-type GaN channel layer (6), an AlGaN barrier layer (7), a SiN passivation layer (8), a top gate (9), and a top source (10), characterized in that: The current blocking layer (5) uses high-k insulating medium SiN to avoid p-type ion injection, weaken the internal electric field of the device, and increase the breakdown voltage of the device; The top gate (9) adopts a trench structure to reduce the thickness of the AlGaN barrier layer (7) below the gate, deplete the two-dimensional electron gas, and realize an enhanced device.

2. The transistor according to claim 1, characterized in that: The bottom drain (1), the heavily doped N-type GaN substrate (2), and the lightly doped N-type GaN drift region (3) are arranged from bottom to top; The gallium nitride current aperture (4) is located at a central position above the lightly doped N-type GaN drift region (3); The current blocking layer (5) is located on both sides of the gallium nitride current aperture (4); The N-type GaN channel layer (6) is located above the SiN current blocking layer (5) and the gallium nitride current aperture (4); the upper part of the N-type GaN channel layer (6) is sequentially provided with the AlGaN barrier layer (7) and the SiN dielectric layer (8); The top gate (9) penetrates into the interior of the AlGaN barrier layer (7) to form a trench-shaped gate; The top source (10) is located on both sides of the AlGaN barrier layer (7) and the SiN dielectric layer (8); The SiN dielectric layer (8) is located between the top gate (9) and the top source (10) for isolation.

3. The transistor according to claim 1, characterized in that: The top source (10) and the bottom drain (1) are both ohmic contacts; The top gate (9) is a Schottky contact; The top source (10) and the bottom drain (1) are both made of Ti / Al / Ni / Au or Mo / Al / Mo / Au metal alloy; The top gate (9) is made of Ni / Au or Ti / Au metal alloy with a relatively large work function.

4. The transistor according to claim 1, characterized in that: The lightly doped N-type GaN drift region (3) has a thickness of 8 um to 15 um and a doping concentration of 8×10 15 cm -3 ~1×10 16 cm -3 .

5. The transistor according to claim 1, characterized in that: The gallium nitride current aperture (4) has a width of 3um to 5um; The current blocking layer (5) is made of one of SiN, HfO2 and TiO2 materials, and has a width of 4um to 6um and a thickness of 1um to 3um.

6. The transistor according to claim 1, characterized in that: The N-type GaN channel layer (6) has a thickness of 30 nm to 50 nm; The AlGaN barrier layer (7) has a thickness of 10 nm to 20 nm. The top gate (9) has a length of 20nm to 3um and a depth of 150nm to 200nm, and a distance between the top gate and the top source (10) of 2um to 5um.

7. A method for preparing a gallium nitride enhancement mode vertical transistor with a high-k insulating CBL, characterized in that: include: S1) Based on a GaN self-supporting substrate, epitaxially growing N-type GaN on the substrate (2) as a device drift layer (3); S2) forming a current through hole (4) above the drift region by using a dry etching technique; S3) depositing a current blocking layer (5) at both sides of the through hole using PECVD technology; S4) using MOVPE to directly grow a GaN channel layer (6) on the GaN through hole (4) and the current blocking layer (5), and then growing an AlGaN barrier layer (7) on the channel layer; S5) performing groove etching on the grown AlGaN barrier layer (7); S6) depositing metal in the etched groove to form a top gate (9) and a top source (10), and performing contact annealing; S7) depositing a SiN passivation layer (8) on the upper layer of the AlGaN barrier layer (7) for isolation protection; S8) growing a drain metal (1) on the back of the substrate (2) and annealing the same to complete device fabrication.

8. The transistor manufacturing method according to claim 7, characterized in that: Step (S1) epitaxy of the drift layer (3) is performed by using any one of metal organic chemical vapor deposition technology MOVPE, hydride vapor phase epitaxy technology HVPE and molecular beam epitaxy technology MBE.

9. The method according to claim 7, characterized in that: The annealing process conditions are: annealing temperature is 300℃~850℃, ambient gas is N2, annealing time is 30s~50s The process conditions of the etching are: power of 150w-300w, chlorine gas flow rate of 10sccm-20sccm, and pressure of 12mTorr-14mTorr.

10. The method according to claim 7, characterized in that The process conditions of the MOVPE technology are: temperature of 400°C to 500°C, pressure of 46mTorr to 48mTorr, hydrogen flow rate of 4300sccm, ammonia flow rate of 4300sccm, and gallium source flow rate of 20umol / min. The process conditions of the PECVD technology are: temperature of 430°C to 450°C, pressure of 1700mTorr, power of 2800w to 3500w, and total gas flow of 2000sccm.

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