Packaging structure, manufacturing method and integrated circuit structure

Abstract

The embodiment of the invention provides a packaging structure, a manufacturing method and an integrated circuit structure, the packaging structure comprises an adapter plate, a plurality of heterogeneous chips are integrated on the adapter plate, and gaps exist between the heterogeneous chips; the at least one target semiconductor structure is located in a gap between the heterogeneous chips, and the target semiconductor structure comprises a substrate; the groove is formed in the substrate; the layer stacking structure covers the substrate and the side wall and the bottom of the groove in a shape-preserving mode, the layer stacking structure comprises n + 1 metal layers and n dielectric layers, the metal layers and the dielectric layers are stacked alternately, and the dielectric layers are located between the adjacent metal layers; wherein n is a positive integer; wherein the number of the target semiconductor structures is multiple, the multiple target semiconductor structures are arranged in an array mode, and the size of the target semiconductor structures arranged in the array mode and the size of the gaps between the heterogeneous chips are arranged in a matched mode based on a preset rule. According to the embodiment of the invention, the warping phenomenon of the packaging structure can be effectively improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and specifically to a packaging structure, a manufacturing method, and an integrated circuit structure. Background Art

[0002] In semiconductor packaging, different materials have different thermal expansion coefficients. When the temperature changes, different materials will expand or contract at different rates due to the difference in thermal expansion coefficients, causing stress inside the packaging structure and causing warping.

[0003] In this context, how to provide a method for manufacturing a packaging structure to improve the warping phenomenon of the packaging structure has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0004] In view of this, embodiments of the present application provide a packaging structure, a manufacturing method and an integrated circuit structure to improve the warping phenomenon of the packaging structure.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a packaging structure, including:

[0007] An adapter board, on which a plurality of heterogeneous chips are integrated, and there are gaps between the heterogeneous chips;

[0008] At least one target semiconductor structure, the target semiconductor structure is located in the gap between the heterogeneous chips, and the target semiconductor structure includes a substrate; a groove located in the substrate; a layer stack structure conformally covering the substrate and the sidewalls and bottom of the groove, the layer stack structure includes n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; wherein n is a positive integer;

[0009] There are multiple target semiconductor structures, and the multiple target semiconductor structures are arranged in an array, and the size of the target semiconductor structures after the array arrangement and the size of the gap between the heterogeneous chips are matched and set based on preset rules.

[0010] Optionally, the dielectric layer exposes an edge of the metal layer covered by it, and the metal layer on the dielectric layer conformally covers the dielectric layer.

[0011] Optionally, the target semiconductor structure further includes:

[0012] a conductive layer located on the layer stack structure, the conductive layer completely filling the groove and covering a portion of the metal layer at the top layer in the layer stack structure to expose edges of each metal layer in the layer stack structure;

[0013] A welding structure is located at the edge of each metal layer in the layer stack structure and at the center of the conductive layer, and the welding structure is used to weld the target semiconductor structure to the transfer board.

[0014] Optionally, the layer stack structure includes three metal layers and two dielectric layers, and the layer stack structure conformally covering the substrate and the sidewalls and bottom of the trench includes:

[0015] a first metal layer conformally covering the substrate and the sidewalls and bottom of the trench;

[0016] a first dielectric layer located on the first metal layer, wherein the first dielectric layer exposes an edge of the first metal layer;

[0017] a second metal layer conformally covering the first dielectric layer;

[0018] a second dielectric layer located on the second metal layer, wherein the second dielectric layer exposes an edge of the second metal layer;

[0019] A third metal layer conformally covers the second dielectric layer.

[0020] Optionally, the target semiconductor structure further includes:

[0021] a first insulating layer conformally covering the substrate, and the sidewalls and bottom of the trench; wherein the layer stack structure is located on the first insulating layer;

[0022] A second insulating layer is located on the layer stack structure, and the second insulating layer covers a partial area of ​​the top metal layer in the layer stack structure to expose the edges of each metal layer in the layer stack structure; wherein the conductive structure is located on the second insulating layer.

[0023] Optionally, the preset rule at least includes: a distance between the target semiconductor structure and the heterogeneous chip is 70 microns to 100 microns.

[0024] Optionally, the aspect ratio of the groove is greater than or equal to 8:1.

[0025] Optionally, the width of the target semiconductor structure ranges from 40 microns to 60 microns.

[0026] Optionally, the thickness of the substrate is greater than the thickness of the adapter plate; and the thickness of the target semiconductor structure is equal to the thickness of the heterogeneous chip.

[0027] Optionally, the material of the dielectric layer is a low dielectric constant material.

[0028] In a second aspect, an embodiment of the present application provides a method for manufacturing a packaging structure, comprising:

[0029] Provide an adapter plate and a target semiconductor structure, wherein a plurality of heterogeneous chips are integrated on the adapter plate, and there are gaps between the heterogeneous chips; the target semiconductor structure comprises a substrate; a groove located in the substrate; a layer stacking structure conformally covering the substrate and the sidewalls and bottom of the groove, wherein the layer stacking structure comprises n+1 metal layers and n dielectric layers, wherein the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; wherein n is a positive integer;

[0030] welding the target semiconductor structure to the gap between the heterogeneous chips;

[0031] There are multiple target semiconductor structures, and the multiple target semiconductor structures are arranged in an array, and the size of the target semiconductor structures after the array arrangement and the size of the gap between the heterogeneous chips are matched and set based on preset rules.

[0032] Optionally, the step of providing an adapter plate and a target semiconductor structure includes:

[0033] Provide adapter plate;

[0034] A target semiconductor structure is formed.

[0035] Optionally, the step of forming a target semiconductor structure includes:

[0036] providing a substrate;

[0037] forming a groove on the substrate;

[0038] Forming a layer stack structure conformally covering the substrate, and the sidewalls and bottom of the trench, the layer stack structure comprising n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; wherein n is a positive integer;

[0039] The dielectric layer exposes the edge of the metal layer covered by it, and the metal layer on the dielectric layer conformally covers the dielectric layer.

[0040] Optionally, the step of forming the target semiconductor structure further includes:

[0041] forming a conductive layer on the layer stack structure, wherein the conductive layer completely fills the groove and covers a portion of the metal layer at the top layer in the layer stack structure to expose edges of each metal layer in the layer stack structure;

[0042] A welding structure is formed at the edge of each metal layer in the layer stack structure and at the center of the conductive layer, and the welding structure is used to weld the target semiconductor structure to the transfer board.

[0043] Optionally, the layer stack structure includes three metal layers and two dielectric layers, and the step of forming the layer stack structure conformally covering the substrate and the sidewalls and bottom of the trench is specifically:

[0044] forming a first metal layer conformally covering the substrate, and the sidewalls and bottom of the trench;

[0045] forming a first dielectric layer on the first metal layer, wherein the first dielectric layer exposes an edge of the first metal layer;

[0046] forming a second metal layer conformally covering the first dielectric layer;

[0047] forming a second dielectric layer on the second metal layer, wherein the second dielectric layer exposes an edge of the second metal layer;

[0048] A third metal layer is formed conformally covering the second dielectric layer.

[0049] Optionally, after the step of forming a groove on the substrate and before the step of forming a layer stack structure conformally covering the substrate and the sidewalls and bottom of the groove, the method further includes:

[0050] A first insulating layer is formed conformally covering the substrate, and the sidewalls and bottom of the trench.

[0051] Optionally, after the step of forming a layer stack structure conformally covering the substrate and the sidewalls and bottom of the trench, and before the step of forming a conductive layer on the layer stack structure, the method further includes:

[0052] A second insulating layer is formed on the layer stack structure, wherein the second insulating layer covers a partial area of ​​the top metal layer in the layer stack structure to expose edges of each metal layer in the layer stack structure.

[0053] Optionally, the preset rule at least includes: a distance between the target semiconductor structure and the heterogeneous chip is 70 microns to 100 microns.

[0054] Optionally, the aspect ratio of the groove is greater than or equal to 8:1.

[0055] Optionally, the width of the target semiconductor structure ranges from 40 microns to 60 microns.

[0056] Optionally, the step of forming a groove on the substrate includes:

[0057] forming a patterned mask layer on the substrate;

[0058] An etching process is adopted to remove the portion of the substrate exposed by the mask layer to form the trench.

[0059] Optionally, the etching process is a dry etching process or a wet etching process, or a combination of both.

[0060] Optionally, the thickness of the substrate is greater than the thickness of the adapter plate; and the thickness of the target semiconductor structure is equal to the thickness of the heterogeneous chip.

[0061] Optionally, the material of the dielectric layer is a low dielectric constant material.

[0062] In a third aspect, an embodiment of the present application provides an integrated circuit structure, which includes the packaging structure as described in the first aspect above.

[0063] Compared with the prior art, the technical solution of the embodiment of the present application has the following advantages:

[0064] The embodiments of the present application provide a packaging structure, a manufacturing method and an integrated circuit structure, wherein the packaging structure includes: an adapter board, on which a plurality of heterogeneous chips are integrated, and there are gaps between the heterogeneous chips; at least one target semiconductor structure, the target semiconductor structure is located in the gap between the heterogeneous chips, and the target semiconductor structure includes a substrate; a groove located in the substrate; a layer stacking structure conformally covering the substrate, and the sidewalls and bottom of the groove, the layer stacking structure includes n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; wherein n is a positive integer; wherein there are multiple target semiconductor structures, and the multiple target semiconductor structures are arranged in an array, and the size of the target semiconductor structure after the array arrangement is matched with the size of the gap between the heterogeneous chips based on a preset rule.

[0065] It can be seen that the packaging structure provided in the embodiment of the present application places a target semiconductor structure in the gap between heterogeneous chips, and multiple target semiconductor structures are arranged in an array to fill the gap between heterogeneous chips, thereby enhancing the overall rigidity of the packaging structure, thereby reducing the stress generated by different materials in the packaging structure due to differences in thermal expansion coefficients, and thereby effectively improving the warping phenomenon of the packaging structure.

[0066] At the same time, the metal layer in the target semiconductor structure has a low resistivity and can provide a low-impedance current path, so that high-frequency noise can be released through this path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0068] Figure 1 is a top view of the packaging structure provided by an embodiment of the present application;

[0069] Figure 2 is a side cross-sectional view of a packaging structure provided in an embodiment of the present application;

[0070] Figure 3 is an optional structural schematic diagram of a target semiconductor structure provided in an embodiment of the present application;

[0071] Figures 4 to 16 It is a structural schematic diagram corresponding to each step in an embodiment of a method for forming a target semiconductor structure of an embodiment of the present application. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0073] As described in the background technology, in semiconductor packaging, different materials have different thermal expansion coefficients. When the temperature changes, different materials will expand or contract at different rates due to the difference in thermal expansion coefficients, which will cause stress inside the packaging structure and cause warping. In this context, how to provide a method for manufacturing a packaging structure to improve the warping phenomenon of the packaging structure has become a technical problem that technicians in this field need to solve urgently.

[0074] In view of this, an embodiment of the present application provides a packaging structure, a manufacturing method and an integrated circuit structure, wherein the packaging structure includes: an adapter board, on which a plurality of heterogeneous chips are integrated, and there are gaps between the heterogeneous chips; at least one target semiconductor structure, the target semiconductor structure is located in the gap between the heterogeneous chips, and the target semiconductor structure includes a substrate; a groove located in the substrate; a layer stacking structure conformally covering the substrate, and the sidewalls and bottom of the groove, the layer stacking structure includes n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; wherein n is a positive integer; wherein there are multiple target semiconductor structures, and the multiple target semiconductor structures are arranged in an array, and the size of the target semiconductor structure after the array arrangement is matched with the size of the gap between the heterogeneous chips based on a preset rule.

[0075] It can be seen that the packaging structure provided in the embodiment of the present application places a target semiconductor structure in the gap between heterogeneous chips, and multiple target semiconductor structures are arranged in an array to fill the gap between heterogeneous chips, thereby enhancing the overall rigidity of the packaging structure, thereby reducing the stress generated by different materials in the packaging structure due to differences in thermal expansion coefficients, and thereby effectively improving the warping phenomenon of the packaging structure.

[0076] At the same time, the metal layer in the target semiconductor structure has a low resistivity and can provide a low-impedance current path, so that high-frequency noise can be released through this path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0077] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0078] refer to Figure 1 , Figure 1 is a top view of the packaging structure provided by the embodiment of the present application. Figure 1 As shown, the packaging structure includes:

[0079] An adapter board 10, on which a plurality of heterogeneous chips (such as chip 1, chip 2, chip 3, chip 4 and chip 5 in the figure) are integrated, and there are gaps between the heterogeneous chips;

[0080] At least one target semiconductor structure 20, wherein the target semiconductor structure 20 is located in a gap between the heterogeneous chips, wherein there are multiple target semiconductor structures 20, and the multiple target semiconductor structures 20 are arranged in an array, and the size of the target semiconductor structure after the array arrangement and the size of the gap between the heterogeneous chips are matched and set based on preset rules.

[0081] In an optional implementation, the preset rule at least includes: the distance between the target semiconductor structure and the heterogeneous chip (such as Figure 1 L 1 and L 2 ) is 70 μm to 100 μm.

[0082] Maintaining a certain distance between the target semiconductor structure and the heterogeneous chip helps reduce crosstalk and interference during signal transmission, ensuring signal integrity and accuracy. At the same time, appropriate spacing helps reduce electromagnetic radiation and electromagnetic interference, and improves the electromagnetic compatibility of the entire system.

[0083] The embodiment of the present application places a target semiconductor structure in the gap between heterogeneous chips, and multiple target semiconductor structures are arranged in an array to fill the gap between heterogeneous chips, thereby enhancing the overall rigidity of the packaging structure, thereby reducing the stress generated by the difference in thermal expansion coefficients of different materials in the packaging structure, and effectively improving the warping phenomenon of the packaging structure.

[0084] Next, refer to Figure 2 , Figure 2 is a side cross-sectional view of the packaging structure provided by the embodiment of the present application. Figure 2 As shown, the gap between the target semiconductor structure 20 and the adapter board 10, and between the heterogeneous chips (such as chip 4 and chip 5 in the figure) and the adapter board 10 can be filled with primer, and plastic encapsulation can be performed to enhance the stability and protection of the packaging structure. Then, a plurality of metal bumps 11 are formed at the bottom of the adapter board 10 to achieve electrical connection with the external circuit. In an optional implementation, the packaging structure after the metal bumps 11 are formed can be further cut to meet specific size or shape requirements.

[0085] For further reference, Figure 3 , Figure 3 is an optional structural diagram of the target semiconductor structure provided in the embodiment of the present application. Figure 3 As shown, the target semiconductor structure 20 includes a substrate 300; a groove 302 located in the substrate 300; a layer stack structure 400 conformally covering the substrate 300 and the sidewalls and bottom of the groove 302; a conductive layer 305 located on the layer stack structure 400, the conductive layer 305 completely filling the groove 302 and covering a portion of the top metal layer in the layer stack structure 400 to expose the edges of each metal layer in the layer stack structure 400; and a welding structure 306 located at the edge of each metal layer in the layer stack structure 400 and the center of the conductive layer 305, the welding structure 306 is used to weld the target semiconductor structure 20 to the adapter board 10.

[0086] The layer stack structure 400 includes n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers, while the dielectric layers expose the edges of the metal layers they cover, and the metal layers on the dielectric layers conformally cover the dielectric layers, wherein n is a positive integer.

[0087] The metal layer in the target semiconductor structure has a low resistivity and can provide a low-impedance current path, so that high-frequency noise can be released through the path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0088] The present application embodiment is described by taking the layer stack structure including 3 metal layers and 2 dielectric layers as an example. Figure 3 As shown, the layer stacking structure comprises:

[0089] A first metal layer 401 conformally covers the substrate 300 and the sidewalls and bottom of the trench 302 .

[0090] The material of the first metal layer 401 can be, for example, a highly conductive metal such as gold, silver or copper, to ensure that the first metal layer 401 can provide a low-impedance current path so that high-frequency noise can be released through the path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0091] The first dielectric layer 402 is located on the first metal layer 401 , and the first dielectric layer 402 exposes an edge of the first metal layer 401 .

[0092] The first dielectric layer 402 is used to prevent short circuit between the first metal layer 401 and the second metal layer 403 and allow current to flow in a predetermined path. The material of the first dielectric layer 402 can be, for example, a low dielectric constant material. The low dielectric constant material is a material with a dielectric constant lower than 4.

[0093] A second metal layer 403 conformally covers the first dielectric layer 402 .

[0094] The material of the second metal layer 403 can be, for example, a highly conductive metal such as gold, silver or copper, to ensure that the second metal layer 403 can provide a low-impedance current path so that high-frequency noise can be released through the path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0095] The second dielectric layer 404 is located on the second metal layer 403 , and the second dielectric layer 404 exposes an edge of the second metal layer 403 .

[0096] The second dielectric layer 404 is used to prevent short circuit between the second metal layer 403 and the third metal layer 405 and allow current to flow in a predetermined path. The material of the second dielectric layer can be, for example, a low dielectric constant material. The low dielectric constant material is a material with a dielectric constant lower than 4.

[0097] A third metal layer 405 conformally covers the second dielectric layer 404 .

[0098] The material of the third metal layer 405 can be, for example, a highly conductive metal such as gold, silver or copper, to ensure that the third metal layer 405 can provide a low-impedance current path so that high-frequency noise can be released through the path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0099] Continue to refer Figure 3 , the target semiconductor structure may further include:

[0100] a first insulating layer 303 conformally covering the substrate 300 and the sidewalls and bottom of the trench 302; wherein the layer stack structure 400 is located on the first insulating layer 303;

[0101] The first insulating layer 303 can prevent the layer stack structure 400 from making electrical contact with the substrate 300, thereby ensuring the stability of the circuit. The material of the first insulating layer 303 can be, for example, silicon oxide or silicon nitride.

[0102] It should be noted that the material of the above-mentioned first insulating layer is only an optional example. In practical applications, the material of the first insulating layer can be selected from various materials familiar to those skilled in the art according to actual conditions. The embodiment of the present application does not limit the material of the first insulating layer.

[0103] A second insulating layer 304 is located on the layer stacking structure 400, and the second insulating layer 304 covers a partial area of ​​the top metal layer in the layer stacking structure 400 to expose the edges of each metal layer in the layer stacking structure 400; wherein the conductive structure is located on the second insulating layer.

[0104] The second insulating layer 304 can prevent the stacked structure 400 from making electrical contact with the conductive layer 305, thereby ensuring the stability of the circuit. The material of the second insulating layer 304 can be, for example, silicon oxide or silicon nitride.

[0105] It should be noted that the material of the second insulating layer is only an optional example. In practical applications, the material of the second insulating layer can be selected from various materials known to those skilled in the art according to actual conditions. The embodiment of the present application does not limit the material of the second insulating layer.

[0106] In an optional implementation, the aspect ratio of the groove is greater than or equal to 8:1, for example, the width of the groove is 12 microns and the depth is 100 microns. The embodiment of the present application adopts a groove with a high aspect ratio, so that the subsequently formed layer stacking structure can achieve a higher capacitance density on the same horizontal area, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0107] In an optional implementation, the target semiconductor structure can be evenly distributed on the wafer, and then the array of the target semiconductor structure can be adjusted and cut into corresponding sizes according to the requirements of different gaps, and welded to the gaps between the heterogeneous chips on the adapter board. In the embodiment of the present application, the width of the target semiconductor structure ranges from 40 microns to 60 microns.

[0108] Since the grooves on the substrate are high aspect ratio grooves, a thicker substrate is required to provide a foundation. At the same time, the target semiconductor structure is located in the gap between the heterogeneous chips to enhance the overall rigidity of the packaging structure, thereby reducing the stress caused by the difference in thermal expansion coefficients of different materials in the packaging structure, thereby effectively improving the warping phenomenon of the packaging structure. Therefore, in the embodiment of the present application, the thickness of the substrate is set to be greater than the thickness of the adapter plate, and the thickness of the target semiconductor structure is equal to the thickness of the heterogeneous chip.

[0109] In an embodiment of the present application, a pad is provided on the adapter plate for welding with the welding structure of the target semiconductor structure. In an optional implementation, a power supply can be led out at the pad and connected to the target semiconductor structure. Among them, the relevant power domain (such as HBM power supply, SOC power supply, etc.) can be selected and led out according to demand. In an embodiment of the present application, a power domain that is physically close to the target semiconductor structure on the adapter plate is selected and led out, so that high-frequency noise can be quickly released through the current path in the target semiconductor structure, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0110] It can be seen that the packaging structure provided in the embodiment of the present application places a target semiconductor structure in the gap between heterogeneous chips, and multiple target semiconductor structures are arranged in an array to fill the gap between heterogeneous chips, thereby enhancing the overall rigidity of the packaging structure, thereby reducing the stress generated by different materials in the packaging structure due to differences in thermal expansion coefficients, and thereby effectively improving the warping phenomenon of the packaging structure.

[0111] At the same time, the metal layer in the target semiconductor structure has a lower resistivity and can provide a low-impedance current path, so that high-frequency noise can be released through this path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0112] An embodiment of the present application also provides a method for manufacturing a packaging structure, which includes: providing an adapter plate and a target semiconductor structure, wherein a plurality of heterogeneous chips are integrated on the adapter plate, and there are gaps between the heterogeneous chips; the target semiconductor structure includes a substrate; a groove located in the substrate; a layer stacking structure conformally covering the substrate, and the sidewalls and bottom of the groove, the layer stacking structure including n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; wherein n is a positive integer; welding the target semiconductor structure to the gap between the heterogeneous chips; wherein there are multiple target semiconductor structures, and the multiple target semiconductor structures are arranged in an array, and the size of the target semiconductor structure after the array arrangement is matched with the size of the gap between the heterogeneous chips based on a preset rule.

[0113] In an optional implementation, the preset rule at least includes: the distance between the target semiconductor structure and the heterogeneous chip (such as Figure 1 L 1 and L 2 ) is 70 μm to 100 μm.

[0114] Maintaining a certain distance between the target semiconductor structure and the heterogeneous chip helps reduce crosstalk and interference during signal transmission, ensuring signal integrity and accuracy. At the same time, appropriate spacing helps reduce electromagnetic radiation and electromagnetic interference, and improves the electromagnetic compatibility of the entire system.

[0115] It can be seen that the embodiment of the present application welds the target semiconductor structure to the gap between the heterogeneous chips, and arranges multiple target semiconductor structures in an array to fill the gap between the heterogeneous chips, thereby enhancing the overall rigidity of the packaging structure, thereby reducing the stress generated by the difference in thermal expansion coefficients of different materials in the packaging structure, and effectively improving the warping phenomenon of the packaging structure.

[0116] At the same time, the metal layer in the target semiconductor structure has a lower resistivity and can provide a low-impedance current path, so that high-frequency noise can be released through this path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0117] In an optional implementation, the step of providing an adapter plate and a target semiconductor structure may include: providing an adapter plate; forming a target semiconductor structure. The process of forming the target semiconductor structure may be, for example, as follows:

[0118] refer to Figure 4 , providing a substrate 100.

[0119] The substrate 100 is used to provide a basis for subsequently forming a target semiconductor structure.

[0120] In this embodiment, the material of the substrate 100 may be silicon. In other embodiments, the material of the substrate 100 may be, for example, one or more of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium, or the substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator. In a further example, an interface layer may be formed on the surface of the substrate 100, and the material of the interface layer may be, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc., for isolating and protecting the surface of the substrate 100.

[0121] refer to Figure 5-Figure 7 , a trench 102 is formed on the substrate 100 .

[0122] In an optional implementation, the groove may be formed, for example, by combining photolithography and etching. Accordingly, the groove formation process may be, for example, as follows:

[0123] refer to Figure 5 , a patterned mask layer 101 is formed on the substrate 100 .

[0124] The mask layer 101 is used to expose a portion of the substrate 100 , so as to perform corresponding process on the exposed substrate 100 .

[0125] In this embodiment, the material of the mask layer 101 may be, for example, silicon nitride. Silicon nitride has high hardness and density, which is conducive to improving the mask effect. In addition, silicon nitride is a commonly used dielectric material in semiconductor processes and has high process compatibility. In other embodiments, the material of the mask layer 101 may also be amorphous carbon. In other embodiments, the material of the mask layer 101 may also be selected from SiOC, SiOCH, SiC, SiCN, SiO 2 , SiN, SiON or more.

[0126] refer to Figure 6 , an etching process is used to remove the portion of the substrate exposed by the mask layer 101 to form the trench 102 .

[0127] The etching process is a dry etching process or a wet etching process or a combination of the two. That is, the etching process can be a dry etching process, a wet etching process, or a combination of dry and wet etching processes.

[0128] In an optional implementation, the aspect ratio of the groove is greater than or equal to 8:1, for example, the width of the groove is 12 microns and the depth is 100 microns. The embodiment of the present application adopts a groove with a high aspect ratio, so that the subsequently formed layer stacking structure can achieve a higher capacitance density on the same horizontal area, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0129] refer to Figure 7 , remove the mask layer 101.

[0130] refer to Figure 8 , forming a first insulating layer 103 conformally covering the substrate 100 and the sidewalls and bottom of the trench 102 .

[0131] In an optional implementation, a layer of insulating material may be uniformly covered on the surface of the substrate, and the sidewall and bottom of the trench 102 by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD or atomic layer deposition ALD, etc.) to form a first insulating layer 103. The first insulating layer 103 can prevent the layer stacking structure 200 from making electrical contact with the substrate 100, thereby ensuring the stability of the circuit. The material of the first insulating layer 103 may be, for example, silicon oxide or silicon nitride.

[0132] It should be noted that the material of the above-mentioned first insulating layer is only an optional example. In practical applications, the material of the first insulating layer can be selected from various materials familiar to those skilled in the art according to actual conditions. The embodiment of the present application does not limit the material of the first insulating layer.

[0133] refer to Figure 9-13 , forming a layer stack structure 200 that conformally covers the substrate 100 and the sidewalls and bottom of the trench 102 .

[0134] The layer stacking structure includes n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; the dielectric layer exposes the edge of the metal layer it covers, and the metal layer on the dielectric layer conformally covers the dielectric layer. Where n is a positive integer.

[0135] The following embodiments of the present application are described by taking the layer stacking structure including 3 metal layers and 2 dielectric layers as an example.

[0136] In an optional implementation, the layer stack structure includes 3 metal layers and 2 dielectric layers, and the step of forming the layer stack structure that conformally covers the substrate, and the sidewalls and bottom of the groove is specifically: forming a first metal layer that conformally covers the substrate, and the sidewalls and bottom of the groove; forming a first dielectric layer on the first metal layer, the first dielectric layer exposing the edge of the first metal layer; forming a second metal layer that conformally covers the first dielectric layer; forming a second dielectric layer on the second metal layer, the second dielectric layer exposing the edge of the second metal layer; forming a third metal layer that conformally covers the second dielectric layer. Accordingly, the formation process of the layer stack structure 200 can be, for example, as follows:

[0137] refer to Fig. 9 , forming a first metal layer 201 conformally covering the substrate 100 and the sidewalls and bottom of the trench 102 .

[0138] In an optional implementation, the first metal layer 201 may be formed by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD or atomic layer deposition ALD, etc.). The material of the first metal layer 201 may be, for example, a highly conductive metal such as gold, silver or copper, to ensure that the first metal layer 201 can provide a low-impedance current path, so that high-frequency noise can be released through the path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0139] It can be understood that the first metal layer 201 is formed after the step of forming the first insulating layer 103 conformally covering the substrate 100 and the sidewalls and bottom of the trench 102 , and therefore, the first metal layer 201 covers the first insulating layer 103 .

[0140] refer to Fig.10 , a first dielectric layer 202 is formed on the first metal layer 201 , and the first dielectric layer 202 exposes an edge of the first metal layer 201 .

[0141] In an optional implementation, the first dielectric layer 202 may be formed by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD or atomic layer deposition ALD, etc.). The first dielectric layer 202 is used to prevent a short circuit between the first metal layer 201 and the second metal layer 203, and allows current to flow in a predetermined path. The material of the first dielectric layer 202 may be, for example, a low dielectric constant material. The low dielectric constant material is a material with a dielectric constant lower than 4.

[0142] refer to Fig.11 , forming a second metal layer 203 conformally covering the first dielectric layer 202.

[0143] In an optional implementation, the second metal layer 203 may be formed by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD or atomic layer deposition ALD, etc.). The material of the second metal layer 203 may be, for example, a highly conductive metal such as gold, silver or copper, to ensure that the second metal layer 203 can provide a low-impedance current path, so that high-frequency noise can be released through the path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0144] refer to Fig.12 , a second dielectric layer 204 is formed on the second metal layer 203 , and the second dielectric layer 204 exposes an edge of the second metal layer 203 .

[0145] In an optional implementation, the second dielectric layer 204 can be formed by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD or atomic layer deposition ALD, etc.). The second dielectric layer 204 is used to prevent a short circuit between the second metal layer 203 and the third metal layer 205, and allows current to flow in a predetermined path. The material of the second dielectric layer can be, for example, a low dielectric constant material. The low dielectric constant material is a material with a dielectric constant lower than 4.

[0146] refer to Fig.13 , forming a third metal layer 205 conformally covering the second dielectric layer 204.

[0147] In an optional implementation, the third metal layer 205 may be formed by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD or atomic layer deposition ALD, etc.). The material of the third metal layer 205 may be, for example, a highly conductive metal such as gold, silver or copper, to ensure that the third metal layer 205 can provide a low-impedance current path, so that high-frequency noise can be released through the path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0148] refer to Fig.14 , a second insulating layer 104 is formed on the layer stack structure 200 .

[0149] The second insulating layer 104 covers a portion of the top metal layer in the layer stack structure 200 to expose edges of each metal layer in the layer stack structure 200 .

[0150] In an optional implementation, the second insulating layer 104 may be formed by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD, or atomic layer deposition ALD, etc.). The second insulating layer 104 may prevent the layer stack structure 200 from making electrical contact with the conductive layer 105, thereby ensuring the stability of the circuit. The material of the second insulating layer 104 may be, for example, silicon oxide or silicon nitride.

[0151] It should be noted that the material of the second insulating layer is only an optional example. In practical applications, the material of the second insulating layer can be selected from various materials known to those skilled in the art according to actual conditions.

[0152] The material of the second insulating layer is not limited in the embodiment of the present application.

[0153] refer to Fig.15 , a conductive layer 105 is formed on the layer stack structure 200 .

[0154] The conductive layer 105 completely fills the groove 102 and covers a portion of the top metal layer in the layer stack structure 200 to expose the edges of each metal layer in the layer stack structure.

[0155] In an optional implementation, the conductive layer 105 may be formed by a deposition process (such as chemical vapor deposition CVD, physical vapor deposition PVD or atomic layer deposition ALD, etc.) The conductive layer 105 may be, for example, a metal layer, and its material may be, for example, a highly conductive metal such as gold, silver or copper.

[0156] refer to Fig.16 A welding structure 106 is formed at the edge of each metal layer in the layer stack structure 200 and at the center of the conductive layer 105 .

[0157] The welding structure 106 is used to weld the target semiconductor structure to the adapter plate. The welding structure 106 may be, for example, a wafer micro-bump.

[0158] In an embodiment of the present application, a pad is provided on the adapter plate for welding with the welding structure 106 of the target semiconductor structure. In an optional implementation, a power supply can be led out at the pad and connected to the target semiconductor structure. Among them, the relevant power domain (such as HBM power supply, SOC power supply, etc.) can be selected and led out according to the needs. In an embodiment of the present application, a power domain that is physically close to the target semiconductor structure on the adapter plate is selected and led out, so that high-frequency noise can be quickly released through the current path in the target semiconductor structure, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0159] In an optional implementation, the target semiconductor structure can be evenly distributed on the wafer, and then the array of the target semiconductor structure can be adjusted and cut into corresponding sizes according to the requirements of different gaps, and welded to the gaps between the heterogeneous chips on the adapter board. In the embodiment of the present application, the width of the target semiconductor structure ranges from 40 microns to 60 microns.

[0160] Since the grooves on the substrate are high aspect ratio grooves, a thicker substrate is required to provide a foundation. At the same time, the target semiconductor structure is located in the gap between the heterogeneous chips to enhance the overall rigidity of the packaging structure, thereby reducing the stress caused by the difference in thermal expansion coefficients of different materials in the packaging structure, thereby effectively improving the warping phenomenon of the packaging structure. Therefore, in the embodiment of the present application, the thickness of the substrate is set to be greater than the thickness of the adapter plate, and the thickness of the target semiconductor structure is equal to the thickness of the heterogeneous chip.

[0161] It can be seen that the embodiment of the present application welds the target semiconductor structure to the gap between the heterogeneous chips, and arranges multiple target semiconductor structures in an array to fill the gap between the heterogeneous chips, thereby enhancing the overall rigidity of the packaging structure, thereby reducing the stress generated by the difference in thermal expansion coefficients of different materials in the packaging structure, and effectively improving the warping phenomenon of the packaging structure.

[0162] At the same time, the metal layer in the target semiconductor structure has a lower resistivity and can provide a low-impedance current path, so that high-frequency noise can be released through this path, thereby effectively reducing the dynamic impedance of the power supply network and improving the high-frequency performance and stability of the circuit.

[0163] An embodiment of the present application also provides an integrated circuit structure, which includes the packaging structure as described above.

[0164] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0165] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: An adapter board, on which a plurality of heterogeneous chips are integrated, and there are gaps between the heterogeneous chips; at least one target semiconductor structure, the target semiconductor structure being located in a gap between the heterogeneous chips, and the target semiconductor structure comprising a substrate; a trench located in the substrate; A layer stack structure conformally covering the substrate, and the sidewalls and bottom of the trench, the layer stack structure comprising n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; wherein n is a positive integer; There are multiple target semiconductor structures, and the multiple target semiconductor structures are arranged in an array, and the size of the target semiconductor structures after the array arrangement and the size of the gap between the heterogeneous chips are matched and set based on preset rules.

2. The packaging structure according to claim 1, characterized in that: The dielectric layer exposes an edge of the metal layer covered by the dielectric layer, and the metal layer on the dielectric layer conformally covers the dielectric layer.

3. The packaging structure according to claim 2, characterized in that: The target semiconductor structure further includes: a conductive layer located on the layer stack structure, the conductive layer completely filling the groove and covering a portion of the metal layer at the top layer in the layer stack structure to expose edges of each metal layer in the layer stack structure; A welding structure is located at the edge of each metal layer in the layer stack structure and at the center of the conductive layer, and the welding structure is used to weld the target semiconductor structure to the transfer board.

4. The packaging structure according to claim 2, characterized in that: The layer stack structure includes three metal layers and two dielectric layers, and the layer stack structure conformally covering the substrate and the sidewalls and bottom of the trench includes: a first metal layer conformally covering the substrate and the sidewalls and bottom of the trench; a first dielectric layer located on the first metal layer, wherein the first dielectric layer exposes an edge of the first metal layer; a second metal layer conformally covering the first dielectric layer; a second dielectric layer located on the second metal layer, wherein the second dielectric layer exposes an edge of the second metal layer; A third metal layer conformally covers the second dielectric layer.

5. The packaging structure according to claim 3, characterized in that: The target semiconductor structure further includes: a first insulating layer conformally covering the substrate, and the sidewalls and bottom of the trench; wherein the layer stack structure is located on the first insulating layer; A second insulating layer is located on the layer stack structure, and the second insulating layer covers a partial area of ​​the top metal layer in the layer stack structure to expose the edges of each metal layer in the layer stack structure; wherein the conductive structure is located on the second insulating layer.

6. The packaging structure according to claim 1, characterized in that: The preset rule at least includes: the distance between the target semiconductor structure and the heterogeneous chip is 70 microns to 100 microns.

7. The packaging structure according to claim 1, characterized in that: The aspect ratio of the groove is greater than or equal to 8:

1.

8. The packaging structure according to claim 1, characterized in that: The target semiconductor structure has a width ranging from 40 micrometers to 60 micrometers.

9. The packaging structure according to claim 1, characterized in that: The thickness of the substrate is greater than the thickness of the adapter plate; the thickness of the target semiconductor structure is equal to the thickness of the heterogeneous chip.

10. The packaging structure according to claim 1, characterized in that: The material of the dielectric layer is a low dielectric constant material.

11. A method for manufacturing a packaging structure, characterized in that: include: Providing an adapter plate and a target semiconductor structure, wherein a plurality of heterogeneous chips are integrated on the adapter plate, and gaps exist between the heterogeneous chips; The target semiconductor structure includes a substrate; a trench located in the substrate; A layer stack structure conformally covering the substrate, and the sidewalls and bottom of the trench, the layer stack structure comprising n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; wherein n is a positive integer; welding the target semiconductor structure to the gap between the heterogeneous chips; There are multiple target semiconductor structures, and the multiple target semiconductor structures are arranged in an array, and the size of the target semiconductor structures after the array arrangement and the size of the gap between the heterogeneous chips are matched and set based on preset rules.

12. The method for manufacturing a packaging structure according to claim 11, characterized in that: The step of providing an adapter plate and a target semiconductor structure comprises: Provide adapter plate; A target semiconductor structure is formed.

13. The method for manufacturing a packaging structure according to claim 12, characterized in that: The step of forming the target semiconductor structure comprises: providing a substrate; forming a groove on the substrate; Forming a layer stack structure conformally covering the substrate, and the sidewalls and bottom of the trench, the layer stack structure comprising n+1 metal layers and n dielectric layers, the metal layers and the dielectric layers are alternately stacked, and the dielectric layers are located between adjacent metal layers; wherein n is a positive integer; The dielectric layer exposes the edge of the metal layer covered by it, and the metal layer on the dielectric layer conformally covers the dielectric layer.

14. The method for manufacturing a packaging structure according to claim 13, characterized in that: The step of forming the target semiconductor structure further includes: forming a conductive layer on the layer stack structure, wherein the conductive layer completely fills the groove and covers a portion of the metal layer at the top layer in the layer stack structure to expose edges of each metal layer in the layer stack structure; A welding structure is formed at the edge of each metal layer in the layer stack structure and at the center of the conductive layer, and the welding structure is used to weld the target semiconductor structure to the transfer board.

15. The method for manufacturing a packaging structure according to claim 13, characterized in that: The layer stack structure includes three metal layers and two dielectric layers, and the step of forming the layer stack structure conformally covering the substrate and the sidewalls and bottom of the trench is specifically: forming a first metal layer conformally covering the substrate, and the sidewalls and bottom of the trench; forming a first dielectric layer on the first metal layer, wherein the first dielectric layer exposes an edge of the first metal layer; forming a second metal layer conformally covering the first dielectric layer; forming a second dielectric layer on the second metal layer, wherein the second dielectric layer exposes an edge of the second metal layer; A third metal layer is formed conformally covering the second dielectric layer.

16. The method for manufacturing a packaging structure according to claim 14, characterized in that: After the step of forming a trench on the substrate and before the step of forming a layer stack structure conformally covering the substrate and the sidewalls and bottom of the trench, the method further includes: A first insulating layer is formed conformally covering the substrate and the sidewalls and bottom of the trench.

17. The method for manufacturing a packaging structure according to claim 14, characterized in that: After the step of forming a layer stack structure conformally covering the substrate and the sidewalls and bottom of the trench, and before the step of forming a conductive layer on the layer stack structure, the method further includes: A second insulating layer is formed on the layer stack structure, wherein the second insulating layer covers a partial area of ​​the top metal layer in the layer stack structure to expose edges of each metal layer in the layer stack structure.

18. The method for manufacturing a packaging structure according to claim 11, characterized in that: The preset rule at least includes: the distance between the target semiconductor structure and the heterogeneous chip is 70 microns to 100 microns.

19. The method for manufacturing a packaging structure according to claim 11, characterized in that: The aspect ratio of the groove is greater than or equal to 8:

1.

20. The method for manufacturing a packaging structure according to claim 11, characterized in that: The target semiconductor structure has a width ranging from 40 micrometers to 60 micrometers.

21. The method for manufacturing a packaging structure according to claim 13, characterized in that: The step of forming a groove on the substrate comprises: forming a patterned mask layer on the substrate; An etching process is adopted to remove the portion of the substrate exposed by the mask layer to form the trench.

22. The method for manufacturing a packaging structure according to claim 21, characterized in that: The etching process is a dry etching process or a wet etching process or a combination of both.

23. The method for manufacturing a packaging structure according to claim 11, characterized in that: The thickness of the substrate is greater than the thickness of the adapter plate; the thickness of the target semiconductor structure is equal to the thickness of the heterogeneous chip.

24. The method for manufacturing a packaging structure according to claim 11, characterized in that: The material of the dielectric layer is a low dielectric constant material.

25. An integrated circuit structure, characterized in that: The integrated circuit structure comprises the packaging structure according to any one of claims 1-10.

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