Improved base open transistor

Abstract

A base open circuit transistor includes: an emitter region of a first doping polarity; a collector region of the first doping polarity; a base region of a second polarity different from the first doping polarity; and an additional region of the first doping polarity, wherein the base region is resistance-connected to the additional region via a resistor.

Description

Technical Field

[0001] The present disclosure relates to open base transistors, such as open base bipolar junction transistor (BJT) transistors. The open base transistors of the present disclosure may be used in electrostatic discharge (ESD) applications. Background Art

[0002] A BJT is a transistor that can be used in electronic circuits to amplify or switch electrical signals. BJTs exist as PNP and NPN types based on the doping type of the three main terminal regions. An NPN transistor includes two semiconductor junctions that share a P-doped region, while a PNP transistor includes two semiconductor junctions that share an N-doped region.

[0003] In normal transistor operation, the base current is used to control the collector current, thereby allowing the transistor to amplify or switch signals. In typical operation, the base-emitter junction is forward biased, which means that the P-doped side of the junction is at a more positive potential than the N-doped side, and the base-collector junction is reverse biased. When a forward bias is applied to the base-emitter junction, the balance between the thermally generated carriers and the repulsive electric field in the emitter depletion region is destroyed. This allows thermally excited carriers (electrons in NPN, holes in PNP) to be injected from the emitter into the base region. These carriers generate a diffusion current from the high concentration region near the emitter toward the low concentration region near the collector through the base. The collector-base junction is reverse biased, and therefore the carrier injection from the collector to the base can be ignored, but the carriers injected from the emitter into the base and diffused to reach the collector-base depletion region are swept into the collector by the electric field in the depletion region.

[0004] An open base transistor, also known as a floating base transistor, is a BJT configuration where the base terminal is unconnected or open. In other words, there is no external electrical connection to the base terminal of the transistor. The open base configuration is not generally used for amplification or switching purposes. Instead, it can be used to measure leakage current or other characteristics of a transistor when the base is unconnected. In this configuration, the transistor has no current flowing into or out of its base terminal. Therefore, the transistor is not in its active amplification mode. The BJT is essentially off and does not perform any signal amplification or switching functions. In this state, the collector current will be very close to zero and the transistor will not conduct.

[0005] A BJT in a multi-finger arrangement involves multiple parallel transistor structures integrated onto the same semiconductor substrate. Each "finger" is a transistor unit, and the fingers are connected in parallel to collectively handle higher currents or power levels. This configuration allows for increased current carrying capability and improved performance. A multi-finger arrangement may include alternating emitter and collector strips, where the emitter and collector regions of the transistor are arranged in alternating strips or segments along the semiconductor substrate. This arrangement may be used in power transistors to ensure efficient current flow and dissipation. Multi-finger arrangements are often used in power amplifiers and other high-power applications that require increased current carrying capability and better thermal management. Alternating emitter and collector strips help to evenly distribute electrical and thermal stresses across the structure of the transistor, which is critical to maintaining its performance and reliability under high-power conditions.

[0006] The BJTs in a multi-finger arrangement may be implemented as open-base transistors. Summary of the invention

[0007] The following describes an overview of various aspects of some examples disclosed herein. It should be understood that these aspects are presented only to provide the reader with a brief overview of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may include multiple aspects and / or combinations of various aspects that may not be described.

[0008] According to aspects of the present disclosure, a base open transistor is presented. The base open transistor may include an emitter region of a first doping polarity. The base open transistor may further include a collector region of the first doping polarity. The base open transistor may further include a base region of a second polarity different from the first doping polarity. The base open transistor may further include an additional region of the first doping polarity. The base region may be resistively connected to the additional region via a resistor. The base region may form a diode junction with the emitter region, the collector region, and the additional region. The emitter region and the collector region may each be connected to a corresponding external contact.

[0009] In an embodiment, the additional region may be arranged within the base region.

[0010] In an embodiment, the additional region may be placed adjacent to the base region and form a diode junction with the base region.At least a portion of the additional region may not be in contact with the base region.

[0011] In an embodiment, the emitter region and the collector region may be arranged at a surface side of the open base transistor.

[0012] In an embodiment, the emitter region and the collector region may be arranged at different sides of the open base transistor.

[0013] In an embodiment, the open base transistor may further include an additional buried region of the first doping polarity. The additional buried region may form a diode junction with the base region. The additional buried region may be connected to the additional region. The additional buried region may be arranged in a layer below the base region. The additional buried region may be at least partially arranged below at least one of the emitter region and the collector region.

[0014] In an embodiment, the body region may have a first polarity type. The body region may form a diode junction with the base region. The body region may be connected to the additional region.

[0015] In an embodiment, the doping level of the additional buried region or body region may be at least 10 times the doping level of the base region.

[0016] In an embodiment, the open base transistor may further include a base contact region of a second polarity. The base contact region may be arranged in or at the base region. The base contact region may be arranged at the surface side of the open base transistor. The resistor may be connected to the base region via the base contact region.

[0017] In an embodiment, the open base transistor may be symmetrical. The emitter region and the collector region may be reversible in operation.

[0018] In an embodiment, the emitter region and the collector region may be arranged into a plurality of strips.

[0019] In an embodiment, the open base transistor may further include an additional diffusion region arranged below and adjacent to the emitter region. The additional additional diffusion region may be arranged directly below the collector region. The additional additional diffusion region may have a doping level higher than the base doping level.

[0020] In an embodiment, the transistor may have a value in the range of 100 Ohm to 100 kOhm.

[0021] According to an aspect of the present disclosure, a semiconductor device is presented. The semiconductor device may include an open-base transistor having one or more of the features described above.

[0022] According to aspects of the present disclosure, an electrostatic discharge (ESD) protection device is presented. The ESD protection device may include an open-base transistor having one or more of the features described above. The ESD protection device may further include a resistor arranged between a base region and an additional region of the open-base transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings, in which corresponding reference numerals indicate corresponding parts, and in which:

[0024] Figures 1A to 7 An example implementation of an open base transistor is shown.

[0025] The drawings are intended for illustrative purposes only and not as limiting the scope of protection as claimed. DETAILED DESCRIPTION

[0026] It is readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of various embodiments, as represented in the accompanying drawings, is not intended to limit the scope of the present disclosure, but merely represents various embodiments. Although various aspects of the embodiments are presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0027] The described embodiments are to be considered in all respects as illustrative only and not restrictive. Therefore, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes within the meaning and scope of the equivalents of the claims are included within the scope of the claims.

[0028] Throughout the specification, references to features, advantages, or similar language do not imply that all of the features and advantages that can be achieved using the present disclosure should be any single example of the present disclosure or in any single example of the present disclosure. Instead, language referring to features and advantages should be understood to mean that a specific feature, advantage, or characteristic described in conjunction with an embodiment is included in at least one embodiment of the present disclosure. Therefore, throughout the specification, discussions of features and advantages and similar language may refer to the same example but do not necessarily refer to the same example.

[0029] In addition, the features, advantages and characteristics of the present disclosure may be combined in one or more embodiments in any suitable manner. In view of the description herein, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments of the present disclosure may be recognized in certain embodiments. Throughout the specification, reference to "one embodiment", "embodiment" or similar language means that the specific features, structures or characteristics described in conjunction with the indicated embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" and "in an embodiment" throughout the specification may but do not necessarily refer to the same embodiment.

[0030] Open base transistors are often used in ESD protection devices. Due to transistor feedback, the clamping voltage is much smaller than a simple diode in reverse mode, making open base transistors more suitable for applications such as ESD protection devices. In addition, open base transistors offer the possibility of creating a completely electrically symmetrical device.

[0031] Known open-base transistor solutions may suffer from at least two problems. First, the leakage current of an open-base transistor is much higher than that of a similar transistor with a base connected to the emitter. Second, a lateral open-base transistor concentrates the current at the edge of the collector diffusion; the central part of the collector contributes less than the outer part of the collector region. The latter problem can only be partially solved by applying a multi-finger arrangement with alternating emitter and collector stripes.

[0032] The present disclosure overcomes these problems by including an additional collector / emitter region in an open-base transistor. The additional collector / emitter region may be placed within or next to the floating base. Furthermore, the additional collector / emitter region is connected to the base via a resistor, preferably an external resistor.

[0033] The additional collector / emitter region has the same doping polarity as the emitter and collector of the transistor. That is, in an NPN transistor the additional collector / emitter region is an additional N region, whereas in a PNP transistor the additional collector / emitter region is an additional P region.

[0034] The open base transistor of the present disclosure may be asymmetric or symmetric. A change in bias polarity may cause the emitter and collector to swap their roles. That is, in an NPN transistor, each set of N diffusions may serve as an emitter of one polarity and a collector of another polarity, while in a PNP transistor, each set of P diffusions may serve as an emitter of one polarity and a collector of another polarity. Therefore, the additional region introduced by the present disclosure may be referred to as an additional collector / emitter region, thereby indicating two different roles depending on the bias polarity. In the case of an open base NPN transistor, the additional collector / emitter region may be referred to as an additional N region. In the case of an open base PNP transistor, the additional collector / emitter region may be referred to as an additional P region.

[0035] In the following exemplary embodiments of the present disclosure, an open-base NPN transistor is shown. It should be understood that these exemplary embodiments are also applicable to an open-base PNP transistor by exchanging the N region and the P region.

[0036] For most embodiments, only cross-sections are shown without top views. The length of the structure in the dimensions not shown may be large, and furthermore, the cross-sections may only show a similar Figure 5A A portion of a multi-finger arrangement.

[0037] Figure 1A A first exemplary embodiment of an open-base transistor 100A is shown. Figure 1A , a cross-sectional side view of an open base transistor 100A is shown. The open base transistor 100A is a vertical and asymmetric open base NPN transistor including an N emitter region 102A accessible via an emitter contact pad 1 , an N collector region 104A accessible via a collector contact pad 2 , and a P base region 106A.

[0038] An additional N region 110A is arranged in the P base region 106A, which is resistively connected to the P base region 106A via a resistor 114A. A P base contact region 112A may be arranged in the P base region 106A for connecting the P base region 106A to the resistor 114A.

[0039] In open base transistor 100A, additional N region 110A may be located at the surface side (ie, front side) of the same crystal as N emitter region 102A, with N collector region 104A located at the back side of the crystal. Additional N region 110A may be referred to as additional N emitter region 110A.

[0040] Figure 1B A variation of the first exemplary embodiment of an open-base transistor 100B is shown. Figure 1B , a cross-sectional side view of an open base transistor 100B is shown. Similar to the open base transistor 100A, the open base transistor 100B is a vertical and asymmetrical open base NPN transistor. Where the open base transistor 100A includes one N emitter region 102A, the open base transistor 100B includes a plurality of N emitter regions 102B, each of which is accessible via an emitter contact pad 1. Although in Figure 1B Three regions are shown in , but multiple regions are possible. Similar to the open base transistor 100A, the open base transistor 100B comprises an N collector region 104B and a P base region 106B accessible via the collector contact pad 2 .

[0041] Additional N regions 110B are arranged in the P base region 106B, which may be connected together and resistively connected to the P base region 106B via one or more resistors 114B. A P base contact region 112B may be arranged in the P base region 106B for connecting the P base region 106B to the resistor 114B.

[0042] Each N emitter region in N emitter region 102A is surrounded by additional N region 110B. One or more or all of P base contact regions in P base contact region 112B may be connected to the same resistor 114B. One or more or all of additional N regions in additional N region 110B may be connected to the same resistor 114B.

[0043] Similar to the open base transistor 100A, in the open base transistor 100B, the additional N region 110B may be located at the surface side of the same crystal as the N emitter region 102B, wherein the N collector region 104B is located at the back side of the crystal. The additional N region 110B may be referred to as an additional N emitter region 110B.

[0044] Figure 2 A second example implementation of an open base transistor 200 is shown. Figure 2 , a cross-sectional side view of an open base transistor 200 is shown. The open base transistor 200 is a laterally symmetric open base NPN transistor comprising an N emitter region 202 accessible via an emitter contact pad 1 , an N collector region 204 accessible via a collector contact pad 2 , and a P base region 206 .

[0045] The two additional N regions 210 surround the P base contact region 212. The two additional N regions can be connected (using a short circuit). The P base region 206 is resistively connected to the additional N regions 210 via a resistor 214. The P base contact region 212 can be arranged in the P base region 206 for connecting the P base region 206 to the resistor 214. The P base contact region 214 and the surrounding additional N regions 210 are arranged between the N emitter region 202 and the N collector region 204.

[0046] In the open base transistor 200 , the N emitter region 202 , the N collector region 204 , the additional N region 210 , and the P base contact region 212 may be located at the same surface side of the crystal.

[0047] Figure 3 A third example implementation of an open base transistor 300 is shown. Figure 3 , a top view of an open base transistor 300 is shown on the left (indicated as "A"), and a cross-sectional side view of the open base transistor is shown on the right (indicated as "B"). The dashed arrow indicates the location of the cross section B in the top view A. The open base transistor 300 is a lateral open base NPN transistor, including an N emitter region 302 accessible via an emitter contact pad 1, an N collector region 304 accessible via a collector contact pad 2, and a P base region 306.

[0048] A connected additional N region 310 is arranged in the P base region 306, the connected additional N region being resistively connected to the P base region 306 via one or more resistors 314. A P base contact region 312 may be arranged in the P base region 306 for connecting the P base region 306 to the resistor 314. The additional N regions and the P base contact regions 312 are alternately arranged between the N emitter region 302 and the N collector region 304 and in parallel with the N emitter region and the N collector region.

[0049] In the open base transistor 300 , the N emitter region 302 , the N collector region 304 , the additional N region 310 , and the P base contact region 312 may be located at the same surface side of the crystal.

[0050] Figure 4 A fourth example implementation of an open-base transistor 400 is shown. Figure 4 , a cross-sectional side view of an open base transistor 400 is shown. The open base transistor 400 is a laterally symmetrical open base NPN transistor, comprising an N emitter region 402 accessible via an emitter contact pad 1, an N collector region 404 accessible via a collector contact pad 2, and a P base region 406. The N emitter regions 402 and the N collector regions 404 are alternately arranged in the P base region 406.

[0051] An additional N region 410 is arranged outside the P base region 406, the additional N region being resistively connected to the P base region 406 via a resistor 414. A P base contact region 412 may be arranged in the P base region 406 for connecting the P base region 406 to the resistor 414.

[0052] The body N region 416 is arranged below the P base region 406 so that the N emitter region 402 and the N collector region 404 are arranged on one side of the P base region 406, and the body N region 416 is arranged on the other side of the P base region 406. The additional N region 410 may be arranged in the body N region 416. The additional N region 410 and the body N region 416 may form an additional N region. The body N region 416 may be an N-doped body. The body N region 416 may be highly doped, in which case it may be similar to Figure 5B An additional buried N region 516 is provided.

[0053] In the open base transistor 400 , the N emitter region 402 , the N collector region 404 , the additional N region 410 , and the P base contact region 412 are located at the same surface side of the crystal.

[0054] Figure 5A and Figure 5B A fifth example implementation of an open-base transistor 500 is shown. Figure 5A shows a top view of an open base transistor 500, and Figure 5BA cross-sectional side view of an open base transistor 500 is shown. The open base transistor 500 is a laterally symmetric open base NPN transistor comprising an N emitter region 502 accessible via an emitter contact pad 1, an N collector region 504 accessible via a collector contact pad 2, and a P base region 506, which may also be referred to as a P well 506. The N emitter regions 502 and the N collector regions 504 are arranged alternately in the P base region 506. Thus, an array of alternating highly doped N diffusions is placed in a shared P well, for example as an array of parallel strips.

[0055] The additional N region 510 is arranged outside the P base region 506, which is resistively connected to the P base region 506 via the resistor 514. A P base contact region 512 may be arranged in the P base region 506 for connecting the P base region 506 to the resistor 514.

[0056] The additional buried N region 516 is arranged directly below the P base region 506, so that the N emitter region 502 and the N collector region 504 are arranged on one side of the P base region 506, and the additional buried N region 516 is arranged on the other side of the P base region 506. The additional buried N region 516 can be moderately to highly doped. The additional N region 510 can be arranged in the additional buried N region 516. The additional N region 510 and the additional buried N region 516 can form an additional N region. Under the buried N region 516, a body region or a P doped region can be arranged.

[0057] In the open base transistor 500, the N emitter region 502, the N collector region 504, the additional N region 510 and the P base contact region 512 are located at the same surface side of the crystal.

[0058] More generally, the N diffusions 502, 504 can be connected to two external nodes 1, 2, with odd-numbered diffusions (e.g., N emitter region 502) connected to a first node (e.g., emitter contact pad 1) and even-numbered diffusions (e.g., N collector region 504) connected to a second node (e.g., collector contact pad 2).

[0059] Two sets of N diffusions can form an open base transistor with a floating base, an NPN transistor. Figure 3 5, the system is symmetrical in that a change in the bias polarity of the emitter and collector can swap their roles. Each set of N diffusions, such as 302 / 304, 402 / 404, or 502 / 504, can act as an emitter of one polarity and a collector of another polarity.

[0060] Figure 4 5 in that the additional emitter / collector is placed below the base diffusion. The two figures are different because Figure 4In FIG. 4 , the additional emitter / collector is formed from the bulk of the silicon crystal, whereas in FIG. 5 , the additional emitter / collector is introduced during the production process with typical steps like lithography and implantation.

[0061] Fig. 6A A sixth example implementation of an open-base transistor 600A is shown. Fig. 6A , a cross-sectional side view of an open base transistor 600A is shown. The open base transistor 600A is a vertical and asymmetric open base NPN transistor including an N emitter region 602A accessible via an emitter contact pad 1, an N collector region 604A accessible via a collector contact pad 2, and a P base region 606A.

[0062] An additional N region 610A is arranged in the P base region 606A, the additional N region being resistively connected to the P base region 606A via a resistor 614A. A P base contact region 612A may be arranged in the P base region 606A for connecting the P base region 606A to the resistor 614A.

[0063] The additional buried N region 616A is arranged in the P base region 606A and extends below the N emitter region 602 A. The additional buried N region 616A is connected to the additional N region 610A.

[0064] In open base transistor 600A, additional N region 610A may be located at the surface side (ie, front side) of the same crystal as N emitter region 602A, with N collector region 604A located at the back side of the crystal. Additional N region 610A may be referred to as additional N emitter region 610A.

[0065] Figure 6B A variation of the sixth exemplary embodiment of an open-base transistor 600B is shown. Figure 6B , a cross-sectional side view of an open base transistor 600B is shown. Fig. 6A , the open base transistor 600B is a vertical and asymmetric open base NPN transistor, including an N emitter region 602B accessible via emitter contact pad 1 , an N collector region 604B accessible via collector contact pad 2 , and a P base region 606B.

[0066] On both sides of the N emitter region 602B, additional N regions 610B are arranged in the P base region 606B, which are resistively connected to the P base region 606B via resistors 614B. Adjacent to each additional N region 610B, a P base contact region 612B may be arranged in the P base region 606B for connecting the P base region 606B to the resistor 614B.

[0067] The additional buried N regions 616B are arranged in the P base region 606B and extend below the N emitter region 602B. Each additional buried N region 616B is connected to a corresponding additional N region 610B.

[0068] Similar to open base transistor 600A, in open base transistor 600B, additional N region 610B may be located at the surface side (ie, front side) of the same crystal as N emitter region 602B, with N collector region 604B located at the back side of the crystal.

[0069] Figure 7 A cross-sectional side view of a portion of an example symmetric open base transistor 700 is shown. The open base transistor 700 includes wide emitter / collector fingers (i.e., N emitter region 702 and N collector region 704) and a P base region 706. An additional buried N region 716, which may alternatively be an N body region, is arranged below the P base region 706.

[0070] The open base transistor 700 may be similar to Figures 1A to 6B The base open transistor 700 includes one or more additional N regions, one or more P base contact regions, and a circuit connecting the additional N regions and the P base contact regions ( Figure 7 ) such as a resistor Figures 1A to 6B as shown in the example.

[0071] Figure 7 An optional additional P diffusion region 707 is shown, which can be arranged directly below at least a portion of each emitter / collector finger 702 / 704 for breakdown tuning. The additional P diffusion region 707 does not extend to the edge of the N-type fingers 702, 704 and enables tuning of the breakdown voltage Ubr_1 at the bottom of the emitter / collector finger 702 / 704, for example, to be less than the breakdown voltage Ubr_2 at the edge of the emitter / collector finger 702 / 704.

[0072] Such as Figures 1A to 7The base open transistor of the present disclosure shown in any of the examples of can advantageously enable reduced leakage current. A common disadvantage of known base open transistors is high leakage levels. The inherent leakage current that blocks the base collector junction is amplified by the current gain of the transistor. Therefore, compared to similar transistors with base connections, base open transistors show higher leakage currents that are ten to one thousand times higher. In some embodiments, additional buried N regions (such as, additional buried N regions 516, 616A, 616B, 716) below the P base region (also referred to as a P well) (such as P base regions 405, 506, 606A, 606B, 706) can reduce the current gain of the transistor, thereby reducing the total leakage current. Additionally or alternatively, an additional N region in the P base region and / or connected to the additional buried N region (such as additional N regions 110A, 110B, 210, 310, 410, 510, 610A, 610B) can reduce the current gain of the transistor, thereby reducing the total leakage current. Most of the emitted electrons may be "trapped" by the additional buried N region and / or the additional N region, and may not reach the collector. The charge added to the additional buried N region and / or the additional N region by the "trapped" electrons can be transferred to the P base region through the additional buried N region and / or the additional N region and a (preferably external) resistor (such as resistors 414, 514, 614A, 614B). The voltage drop across this path may be very small: for example, for a (significant) leakage current of 1 microampere and a resistance value of 1 kOhm, the voltage drop may be only 1 millivolt. Therefore, the junction between the N region (i.e., the N emitter region or the N collector region) and the P well may never be forward biased, and no electrons may be injected back into the P well from the additional buried N region and / or the additional N region. In fact, all trapped electrons may be lost, similar to the case of recombination with holes on the way to the collector. The current gain of the transistor may be reduced, and the amplification of the leakage current may be reduced, and thus the leakage level may be smaller.

[0073] Such as Figures 1A to 7The base open transistor of the present disclosure shown in any of the examples can advantageously enable the clamping voltage to be reduced, and the current capacity per unit area can be increased. If the voltage difference between two external nodes (such as the emitter contact pad 1 and the collector contact pad 2) is higher than the breakdown voltage of the N diffusion to the P base region (also called P well) (such as the P base region 405, 506, 606A, 606B, 706), the NPN transistor can enter its conduction mode. The base collector junction will be broken down and the emitter base junction will be forward biased. When used as ESD protection (e.g., placed between a signal line and ground), this current path may discharge unwanted stress current to ground, thereby limiting the voltage on the signal line. A set of N diffusions (e.g., N emitter regions 102A, 102B, 202, 302, 402, 502, 602A, 602B, 702) can be used as an emitter, thereby injecting electrons into the P well. Another set of N diffusions (e.g., N collector regions 104A, 104B, 204, 304, 404, 504, 604A, 604B, 704) can act as the collector of the transistor. The junction between the collector and the P-well base can be in a breakdown mode, and the breakdown current delivers the base current for the transistor. Some of the emitted electrons can reach the collector side directly, while some can reach the additional buried N region and / or the additional N region. Within the additional buried N region, the electrons can be transported to a position below the collector and emitted into the P-well base below the collector, where the electrons can eventually reach the collector. Therefore, the additional buried N region can "mirror" or "reflect" the electrons upward to the collector.

[0074] The additional buried N region and / or additional N region can achieve the same function for both external polarities. As the polarity changes, the emitter and collector will change roles. For both polarities, the additional buried N region and / or additional N region can "reflect" the injected electrons upward to the actual collector.

[0075] The connection between the additional buried N region and / or the additional N region and the P base region preferably does not hinder the injection of electrons from the additional buried N region and / or the additional N region into the P base region. This is because the value of the connection resistor is preferably selected to be in the range of kOhm. The use of an open-base transistor forces the current through the device to be much greater than 1 ampere, especially when used as an ESD protection circuit. The voltage drop across the resistor can be sufficient to strongly forward bias the junction between the additional buried N layer and / or the additional N region and the P base region. Only a small part of the current collected by the N region can be fed through the resistor, and the main part can be used in the forward mode of the junction. For example: if 1mA flows through a resistor with 1kOhm, the voltage drop will be 1 volt, which is much larger than the forward voltage of the silicon PN junction. Therefore, the largest part of the collected current can be injected as electrons through the forward biased junction.

[0076] Furthermore, advantageously, most of the emitted electrons reach the collector without being recombined in the base region. Without an additional buried N region and / or an additional N region, many of the emitted electrons may diffuse into the body of the semiconductor device where they may recombine with holes. This recombination will reduce the emitter efficiency, which will result in a smaller current gain of the transistor. A smaller current gain results in an undesirable higher clamping voltage.

[0077] Another advantage of the additional buried N region is that it can collect emitted electrons from the entire width of the emitter N diffusion and transport the mirrored electrons to anywhere below the collector N diffusion, in particular to the center of the diffusion. Without the additional buried N region, only a few electrons will reach the center of the collector stripe, and only a few electrons will be emitted from the center of the emitter stripe. This may be more pronounced for wide stripes of N emitter / N collector regions, where the width of the stripe is greater than the distance of the stripe. With the additional buried N region and / or the additional N region, a larger portion of the emitter and collector stripes can be active than without the additional buried N region and / or the additional N region.

[0078] Multi-finger open-base transistors such as open-base transistors 100B, 400, 500 can be lateral semiconductor devices in the sense that the current flows parallel to the surface of the crystal. In such a configuration, the edges of the diffusion strips contribute the most to the total current, and the center of the strips contributes less because the resistance between the centers is greater than the resistance between the edges of the strips. Therefore, lateral multi-finger transistors are usually designed with very narrow strips. Typically, the width of the strip is similar to the distance of the strips and the depth of the diffusion. In the case where the available space is the limiting factor in the design of the semiconductor device, the current capacity is basically limited by the total width of the transistor because the edges of the strips are the main contributors to the current transmission. The total width is then limited by the number of strips that can be placed in the available area. The strips must have a certain distance, which is limited by the processing capabilities of the diffusion process and the electrical properties of the transistor. Therefore, the total current capacity per unit area is limited by the width rule and the distance rule of the N diffusion.

[0079] In a multi-finger based open transistor, if the central portion of the stripe is active, which may be the case when an additional buried N region is placed below the P base region, then advantageously wider stripes become feasible and the total current capacity per unit area may be greater than in known laterally striped transistors where only the edges of the stripe are active. Thus, the arrangement according to the present disclosure provides better performance measured in current density per unit area than known arrangements that do not use an "electronic mirror".

[0080] Additional buried N region (in Figure 5 to Figure 7 In the example of FIG. 5 , additional buried N regions 516, 616A, 616B, 716) and / or additional N regions (in Figures 1A to 6B In the example of FIG. 1 , the additional N regions 110A, 110B, 210, 310, 410, 510, 610A, 610B) and the P base region (in Figures 1A to 7 In the example, the resistors are connected between the additional N regions 106A, 106B, 206, 306, 406, 506, 606A, 606B, 706) (in Figures 1A to 6B In the example of FIG. 1 , the resistors 114A, 114B, 214, 314, 514, 614A, 614B) advantageously enable the additional buried N region and / or the additional N region to operate in two different modes for different current levels. For very small currents, the resistive connection may be similar to a short circuit, and the additional buried N region and / or the additional N region may reduce the current gain and, therefore, the leakage current. For very large currents, the resistive connection may be similar to an open circuit connection and the additional buried N region and / or the additional N region may improve the electron flow by collecting and re-emitting electrons.

[0081] Wherein regions such as N emitter region, N collector region, P base region, additional P diffusion region, additional N region, P base contact region and additional buried region are cited above, these regions may alternatively be referred to as layers, such as N emitter layer etc.

[0082] Resistors such as resistors 114A, 114B, 214, 314, 514, 614A, 614B are preferably internal resistors, i.e., internal on the semiconductor device, preferably away from the base open transistor region. Alternatively, the resistors may be external to the semiconductor device, i.e., external to the semiconductor device including the base open transistor according to the present disclosure, in which case the resistors may be soldered to contact pads connected to the additional N region and the P base contact region.

[0083] The P base regions such as P base regions 106A, 106B, 206, 306, 406, 506, 606A, 606B, 706 and the additional buried N regions and / or additional N regions may be connected via resistors having preferred values ​​in the kOhm range, possibly any value between 100Ohm and 100kOhm.

Claims

1. An open-base transistor (100A, 100B, 200, 300, 400, 500, 600A, 600B, 700), comprising: an emitter region (102A, 102B, 202, 302, 402, 502, 602A, 602B, 702) of a first doping polarity; The collector region (104A, 104B, 204, 304, 404, 504, 604A, 604B, 704) of the first doping polarity; a base region (106A, 106B, 206, 306, 406, 506, 606A, 606B, 706) of a second polarity different from the first doping polarity; and the additional regions (110A, 110B, 210, 310, 410, 510, 610A, 610B) of the first doping polarity, wherein the base region is resistively connected to the additional region via a resistor (114A, 114B, 214, 314, 414, 514, 614A, 614B). wherein the base region forms a diode junction with the emitter region, the collector region and the additional region, And wherein the emitter region and the collector region are each connected to a corresponding external contact. 2 . The open-base transistor according to claim 1 , wherein the additional region is arranged within the base region.

3. An open-base transistor according to any of the preceding claims, wherein the additional region is placed adjacent to the base region and forms a diode junction with the base region, wherein at least a portion of the additional region is not in contact with the base region. 4 . The open base transistor according to claim 1 , wherein the emitter region and the collector region are arranged at a surface side of the open base transistor. 5 . 5 . The open-base transistor according to claim 1 , wherein the emitter region and the collector region are arranged at different sides of the open-base transistor.

6. An open-base transistor according to any one of the preceding claims, further comprising: an additional buried region (516, 616A, 616B, 716) of the first doping polarity, the additional buried region forming a diode junction with the base region, wherein the additional buried region is connected to the additional region, wherein the additional buried region is arranged in a layer below the base region, And wherein the additional buried region is at least partially arranged below at least one of the emitter region and the collector region.

7. An open base transistor according to any one of the preceding claims, wherein the body region has the first polarity type, wherein the body region forms a diode junction with the base region, And wherein the body region is connected to the additional region.

8. The open base transistor of claim 6, wherein the doping level of the additional buried or body region is at least 10 times the doping level of the base region.

9. An open-base transistor according to any one of the preceding claims, further comprising: the base contact region (112A, 112B, 212, 312, 412, 512, 612A, 612B) of the second polarity, wherein the base contact region is arranged in or at the base region, wherein the base contact region is arranged at the surface side of the open base transistor, And wherein the resistor is connected to the base region via the base contact region.

10. An open base transistor according to any one of the preceding claims, wherein the open base transistor is symmetrical, wherein the emitter region and the collector region are reversible in operation. 11 . The open-base transistor of claim 10 , wherein the emitter region and the collector region are arranged in a plurality of strips.

12. An open-base transistor according to any one of the preceding claims, further comprising: an additional diffusion region (707), the additional diffusion region (707) being arranged below the emitter region and adjacent to the emitter region; and a further additional diffusion region (707), the further additional diffusion region (707) being arranged directly below the collector region, The further additional diffusion region has a doping level that is higher than the base doping level.

13. An open base transistor according to any one of the preceding claims, wherein the transistor has a value in the range of 100 Ohm to 100 kOhm.

14. A semiconductor device comprising the open-base transistor according to any one of claims 1 to 13.

15. An electrostatic discharge (ESD) protection device, comprising: An open base transistor according to any one of claims 1 to 13; and A resistor (114A, 114B, 214, 314, 414, 514, 614A, 614B) is arranged between a base region (106A, 106B, 206, 306, 406, 506, 606A, 606B, 706) and an additional region (110A, 110B, 210, 310, 410, 510, 610A, 610B) of the open-base transistor.

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