Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, and relates to the technical field of solar cells. The solar cell includes a silicon-based substrate; the back surface of the silicon-based substrate comprises a first region, a second region and an isolation region located between the first region and the second region; the semiconductor structures are respectively positioned in the first region and the second region; the semiconductor structure in the first region comprises at least one first semiconductor structure and at least one second semiconductor structure positioned on one side, far away from the silicon-based substrate, of the first semiconductor structure; the first semiconductor structure comprises a first tunneling oxide layer and a first polycrystalline silicon layer which are stacked; the second semiconductor structure comprises a second tunneling oxide layer and a second polycrystalline silicon layer which are stacked; the second tunneling oxide layer is of a porous structure provided with a plurality of holes at intervals; and the first electrode and the second electrode are respectively contacted with the semiconductor structures of the first region and the second region. The completeness of the passivation contact structure on the surface of the solar cell can be ensured, so that the performance of the solar cell is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of solar cells, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] In recent years, with the rapid development of photovoltaic technology, the requirements for the conversion efficiency of solar cells have been continuously improved. Among them, back contact (BC) crystalline silicon solar cells, as a high-efficiency photovoltaic cell, have become a hot topic in current research.

[0003] In the structure of BC cells, the passivation level of the back P and N regions plays a key role in the performance of the cell. In the prior art, by forming an ultra-thin tunneling oxide layer and a doped polysilicon layer on the surface of the cell, the passivation performance of the cell surface can be effectively improved, thereby increasing the open circuit voltage and short circuit current of the cell, and improving the overall performance of the solar cell.

[0004] However, when the polysilicon layer in the solar cell is diffused and doped, the ultra-thin tunneling oxide layer is easily destroyed by the dopant and affects the passivation structure. At the same time, when the electrode is sintered in the solar cell, the sintered electrode easily penetrates the ultra-thin tunneling oxide layer, resulting in the destruction of the tunneling oxide layer, which makes the passivation effect of the cell surface drop sharply. Therefore, how to ensure the integrity of the passivation contact structure on the surface of the solar cell has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present invention provides a solar cell and a preparation method thereof, so as to ensure the integrity of a passivation contact structure on the surface of the solar cell, thereby improving the performance of the solar cell.

[0006] A first aspect of the present invention provides a solar cell, the solar cell comprising:

[0007] A silicon-based substrate, comprising a front side and a back side opposite to each other; the back side comprises a first region, a second region, and an isolation region between the first region and the second region;

[0008] Semiconductor structures located in the first region and the second region respectively; the semiconductor structure in the first region is of opposite type to the semiconductor structure in the second region;

[0009] The semiconductor structure of the first region includes at least one first semiconductor structure and at least one second semiconductor structure located on a side of the first semiconductor structure away from the silicon-based substrate; the first semiconductor structure includes a first tunneling oxide layer and a first polysilicon layer arranged in a stacked manner; the second semiconductor structure includes a second tunneling oxide layer and a second polysilicon layer arranged in a stacked manner; the second tunneling oxide layer is a porous structure; the porous structure includes a plurality of holes arranged at intervals;

[0010] a first electrode in contact with the semiconductor structure of the first region;

[0011] The second electrode is in contact with the semiconductor structure in the second region.

[0012] Optionally, a thickness T1 of at least one of the first tunneling oxide layer and the second tunneling oxide layer has a value range of: 1 nm≤T1≤3 nm.

[0013] Optionally, a thickness T2 of at least one of the first polysilicon layer and the second polysilicon layer is in the range of 50 nm ≤ T2 ≤ 400 nm.

[0014] Optionally, the semiconductor structure of the first region further includes at least one third semiconductor structure; the third semiconductor structure includes a third tunneling oxide layer and a third polysilicon layer which are stacked;

[0015] The third semiconductor structure is located on a side of the second semiconductor structure facing away from the silicon-based substrate, and / or the third semiconductor structure is located between two adjacent second semiconductor structures.

[0016] Optionally, the semiconductor structure of the second region includes at least one fourth semiconductor structure; the fourth semiconductor structure includes a fourth tunneling oxide layer and a fourth polysilicon layer that are stacked.

[0017] Optionally, the semiconductor structure in the second region further includes at least one fifth semiconductor structure located on a side of the fourth semiconductor structure away from the silicon-based substrate;

[0018] The fifth semiconductor structure includes a fifth tunneling oxide layer and a fifth polysilicon layer which are stacked; the fifth tunneling oxide layer is the porous structure.

[0019] Optionally, the semiconductor structure of the second region further includes at least one sixth semiconductor structure; the sixth semiconductor structure includes a sixth tunneling oxide layer and a sixth polysilicon layer which are stacked;

[0020] The sixth semiconductor structure is located on a side of the fifth semiconductor structure facing away from the silicon-based substrate, and / or the sixth semiconductor structure is located between two adjacent fifth semiconductor structures.

[0021] Optionally, the size W of the hole is in the range of 0.05 μm ≤ W ≤ 5 μm.

[0022] Optionally, in the porous structure, a distance L between two adjacent holes is in the range of 0.1 μm ≤ L ≤ 100 μm.

[0023] Optionally, the solar cell further comprises:

[0024] The passivation layer and the anti-reflection layer are stacked and cover the semiconductor structure of the first region, the isolation region, the semiconductor structure of the second region and the front side.

[0025] A second aspect of the present invention provides a solar cell, the solar cell comprising:

[0026] A silicon-based substrate, comprising a front side and a back side opposite to each other; the back side comprises a first region, a second region, and an isolation region between the first region and the second region;

[0027] Semiconductor structures located in the first region and the second region respectively; the semiconductor structure in the first region is of opposite type to the semiconductor structure in the second region;

[0028] The semiconductor structure of the first region includes a first polysilicon layer; the semiconductor structure of the first region also includes at least one second tunneling oxide layer disposed in the first polysilicon layer; the second tunneling oxide layer is a porous structure; the porous structure includes a plurality of holes arranged at intervals;

[0029] a first electrode in contact with the semiconductor structure of the first region;

[0030] The second electrode is in contact with the semiconductor structure in the second region.

[0031] Optionally, the semiconductor structure of the second region includes a fourth polysilicon layer;

[0032] The semiconductor structure in the second region further includes at least one fifth tunneling oxide layer disposed in the fourth polysilicon layer; the fifth tunneling oxide layer is the porous structure.

[0033] A third aspect of the present invention provides a method for preparing a solar cell, the method for preparing a solar cell comprising:

[0034] Providing a silicon-based substrate; the silicon-based substrate comprises a front side and a back side opposite to each other; the back side comprises a first region, a second region, and an isolation region between the first region and the second region;

[0035] Semiconductor structures are formed in the first region and the second region respectively; the semiconductor structure in the first region is of opposite type to the semiconductor structure in the second region; the semiconductor structure in the first region includes at least one first semiconductor structure and at least one second semiconductor structure located on a side of the first semiconductor structure away from the silicon-based substrate; the first semiconductor structure includes a first tunneling oxide layer and a first polysilicon layer arranged in a stacked manner; the second semiconductor structure includes a second tunneling oxide layer and a second polysilicon layer arranged in a stacked manner; the second tunneling oxide layer is a porous structure; the porous structure includes a plurality of holes arranged at intervals;

[0036] A first electrode in contact with the semiconductor structure in the first region and a second electrode in contact with the semiconductor structure in the second region are formed.

[0037] The technical solution provided by the present invention is to set a first area, a second area and an isolation area between the first area and the second area on the back side of a silicon-based substrate, so as to isolate the first area and the second area from each other by using the isolation area to prevent a short circuit between the first area and the second area; at the same time, by setting at least one first semiconductor structure in the semiconductor structure of the first area, and the first semiconductor structure includes a first tunneling oxide layer and a first polysilicon layer arranged in a stacked manner, so that corresponding carriers can be selectively transmitted through the first tunneling oxide layer, the recombination loss of electrons and holes is reduced, which helps to improve the open circuit voltage and short circuit current of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell; in addition, the semiconductor structure of the first area also includes at least one first semiconductor structure and at least one second semiconductor structure located on the side of the first semiconductor structure away from the silicon-based substrate, the second semiconductor structure includes a second tunneling oxide layer and a second polysilicon layer arranged in a stacked manner, and by making the second semiconductor structure The second tunneling oxide layer of the conductor structure is a porous structure, so that the holes of the porous structure can have a smaller potential barrier, reducing the blocking of the second semiconductor structure to the carriers, reducing the resistance of the carriers so that the carriers of the first tunneling oxide layer in the semiconductor structure of the first zone can reach the first electrode, which is beneficial to improving the performance and efficiency of the solar cell; by arranging at least one second semiconductor structure in the first zone, so that the first electrode formed in contact with the semiconductor structure of the first zone is not easy to penetrate into the first tunneling oxide layer in contact with the silicon-based substrate, and because the semiconductor structure of the first zone includes multiple layers of polysilicon layers and multiple layers of tunneling oxide layers, the outer oxide layer of the multiple layers of tunneling oxide layers prevents the dopant from damaging the bottom oxide layer, and can maintain the structure of the passivation contact more completely, thereby improving the passivation performance and open circuit voltage of the battery, ensuring the integrity of the passivation contact structure on the surface of the solar cell, and improving the performance and stability of the solar cell.

[0038] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is a schematic structural diagram of a solar cell provided by an embodiment of the present invention;

[0041] Figure 2 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0042] Figure 3 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0043] Figure 4 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0044] Figure 5 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0045] Figure 6 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0046] Figure 7 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0047] Figure 8 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0048] Fig. 9 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0049] Fig.10 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0050] Fig.11 is a schematic structural diagram of a porous structure provided by an embodiment of the present invention;

[0051] Fig.12 is a schematic structural diagram of another solar cell provided by an embodiment of the present invention;

[0052] Fig.13 is a flow chart of a method for preparing a solar cell provided by an embodiment of the present invention;

[0053] Fig.14 The present invention provides a process flow chart for preparing a solar cell.

[0054] In the figure: 00. silicon-based substrate; 01. front side; 02. back side; 1. first area; 2. second area; 3. isolation area; 11. semiconductor structure in the first area; 21. semiconductor structure in the second area; 111. first semiconductor structure; 112. second semiconductor structure; 113. third semiconductor structure; 101. first tunneling oxide layer; 102. first polysilicon layer; 201. second tunneling oxide layer; 202. second polysilicon layer; 301. third tunneling oxide layer; 302. third polysilicon layer; 211. fourth semiconductor structure; 212. fifth semiconductor structure; 213. sixth semiconductor structure; 401. fourth tunneling oxide layer; 402. fourth polysilicon layer; 501. fifth tunneling oxide layer; 502. fifth polysilicon layer; 601. sixth tunneling oxide layer; 602. sixth polysilicon layer; 4. first electrode; 5. second electrode; 6. passivation layer; 7. anti-reflection layer. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0057] Figure 1 is a schematic diagram of the structure of a solar cell provided by an embodiment of the present invention, such as Figure 1 As shown, the solar cell includes a silicon-based substrate 00, including a front side 01 and a back side 02 opposite to each other; the back side 02 includes a first region 1, a second region 2, and an isolation region 3 located between the first region 1 and the second region 2; semiconductor structures located in the first region 1 and the second region 2 respectively; the semiconductor structure 11 of the first region 1 is of opposite type to the semiconductor structure 21 of the second region 2; the semiconductor structure 11 of the first region 1 includes at least one first semiconductor structure 111 and at least one second semiconductor structure 112 located on the side of the first semiconductor structure 111 away from the silicon-based substrate 00; the first semiconductor structure 111 includes a first tunneling oxide layer 101 and a first polysilicon layer 102 arranged in stacked layers; the second semiconductor structure 112 includes a second tunneling oxide layer 201 and a second polysilicon layer 202 arranged in stacked layers; the second tunneling oxide layer 201 is a porous structure; the porous structure includes a plurality of holes arranged at intervals; a first electrode 4 is in contact with the semiconductor structure 11 of the first region 1; and a second electrode 5 is in contact with the semiconductor structure 21 of the second region 2.

[0058] Among them, the silicon-based substrate 00 can be an N-type silicon-based substrate or a P-type silicon-based substrate, and the doping type and doping concentration of the silicon-based substrate can be designed according to actual needs, and the embodiment of the present invention does not specifically limit this. Specifically, the silicon-based substrate 00 can be double-sided chemically polished by an alkaline polishing tank machine, and the alkaline polishing liquid will corrode the surface of the silicon-based substrate 00 to remove the cutting damage on the surface of the silicon-based substrate 00, and can form a microstructure on the surface of the silicon-based substrate 00. The microstructure is a tower base formed on the surface of the silicon-based substrate. The presence of the tower base enables the silicon-based substrate 00 to have a larger surface area, thereby enabling the silicon-based substrate 00 to have a larger light contact surface, which is beneficial to improving the photoelectric conversion efficiency of the silicon-based substrate 00. In addition, the back side of the silicon-based substrate 00 includes a first region 1 and a second region 2, and semiconductor structures located in the first region 1 and the second region 2, respectively. The semiconductor structure 11 of the first region 1 is of opposite type to the semiconductor structure 21 of the second region 2, that is, when the semiconductor structure 11 of the first region 1 is of P type, the semiconductor structure 21 of the second region 2 is of N type; when the semiconductor structure 11 of the first region 1 is of N type, the semiconductor structure 21 of the second region 2 is of P type. It should be noted that, for the convenience of description, without special limitations, the embodiments of the present invention are all based on the silicon-based substrate 00 being an N-type silicon-based substrate, the semiconductor structure 11 of the first region 1 being of P type, and the semiconductor structure 21 of the second region 2 being of N type, and the technical solution of the embodiments of the present invention is exemplarily described. The back side of the silicon-based substrate 00 also includes an isolation region 3 located between the first region 1 and the second region 2. The isolation region 3 can be formed by a process such as wet etching. The isolation region 3 between the first region 1 and the second region 2 can isolate the P region and the N region from each other to prevent leakage caused by a short circuit between the first region 1 and the second region 2. Wherein, under the premise that the first region 1 and the second region 2 can be isolated from each other, the size of the isolation region 3 should be as small as possible.

[0059] The semiconductor structure 11 of the first region 1 includes at least one first semiconductor structure 111, that is, the semiconductor structure 11 of the first region 1 may include one or more first semiconductor structures 111, and the first semiconductor structure 111 includes a first tunneling oxide layer 101 and a first polysilicon layer 102 arranged in a stacked manner, and the first tunneling oxide layer 101 may cover the first region 1 to achieve selective permeation of carriers. Specifically, the first tunneling oxide layer 101 may be grown in the first region 1 by thermal oxidation, chemical oxidation or chemical vapor deposition. For example, the first tunneling oxide layer 101 may be formed by placing the silicon-based substrate 00 in a high-oxygen solution to oxidize the surface of the silicon-based substrate 00, or by heating the silicon-based substrate 00 while introducing oxygen so that the silicon-based substrate is in a high-temperature and high-oxygen environment to form the first tunneling oxide layer 101. The first tunneling oxide layer 101 may include, for example, SiO 2Etc. The first tunneling oxide layer 101 can play a role in surface passivation and carrier selective transmission, which helps to improve the open circuit voltage and short circuit current of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell. Among them, when the semiconductor structure 11 of the first region 1 is P-type, the first polycrystalline silicon layer 102 can be specifically understood as a polycrystalline silicon layer doped with boron, so that the first polycrystalline silicon layer 102 can form a tunnel junction with the first tunneling oxide layer 101 and the N-type silicon-based substrate 00. The existence of the tunnel junction can improve the electron transmission efficiency of the solar cell.

[0060] The semiconductor structure 11 of the first region 1 includes at least one first semiconductor structure 111, so that the first region 1 can include at least one first polycrystalline silicon layer 102 and at least one first tunneling oxide layer 101 respectively located between the first polycrystalline silicon layer 102 and the silicon-based substrate 00, and located between two adjacent first polycrystalline silicon layers 102, so that when the first polycrystalline silicon layer 102 is doped, the first tunneling oxide layer 101 located between the first polycrystalline silicon layers 102 can prevent the entry of dopants, and can prevent the dopants from damaging the first tunneling oxide layer 101 in contact with the silicon-based substrate 00, thereby ensuring the integrity of the first tunneling oxide layer 101 in contact with the silicon-based substrate 00, thereby ensuring that the first doping structure 11 has a complete passivation contact structure, which is beneficial to improving the passivation performance, open circuit voltage and short circuit current of the solar cell.

[0061] Specifically, when the semiconductor structure of the first region 1 includes a plurality of first semiconductor structures, the first tunneling oxide layer 101 and the first polysilicon layer 102 may be alternately formed in the silicon-based substrate, that is, silane is introduced while oxygen is introduced, and the first polysilicon layer 102 is formed by low pressure chemical vapor deposition (LPCVD) while the first tunneling oxide layer 101 is formed, or the first polysilicon layer 102 may be deposited by plasma enhanced chemical vapor deposition (PECVD) while the first tunneling oxide layer 101 is formed. After the nth first polysilicon layer 102 is formed, BCl 3 or BBr 3 As a boron diffusion source, boron atoms are diffused into at least the first polysilicon layer 102 to at least dope the first polysilicon layer 102 and form the first polysilicon layer 102 with a boron doping type.

[0062] In addition, the semiconductor structure 11 of the first zone 1 also includes at least one second semiconductor structure 112 located on the side of the first semiconductor structure 111 away from the silicon-based substrate 00, that is, the semiconductor structure 11 of the first zone 1 may include one or more second semiconductor structures 112, and the second tunneling oxide layer 201 of the second semiconductor structure 112 is a porous structure, which can be specifically understood as a tunneling oxide layer structure with a plurality of holes arranged at intervals, so that after the carriers that selectively pass through the first semiconductor structure 111 reach the second tunneling oxide layer 201 of the second semiconductor structure 112, they can directly pass through the second tunneling oxide layer 201 of the first semiconductor structure 112 from the hole position, thereby reducing the potential barrier in the second tunneling oxide layer 201 of the second semiconductor structure 112, enabling more carriers to pass through the second semiconductor structure 112, reducing the tunneling resistance of the carriers, thereby helping to optimize the carrier transmission path and improving the performance and efficiency of solar cells.

[0063] It should be noted that, under the premise of ensuring that the second semiconductor structure 112 is located on the side of the first semiconductor structure 111 away from the silicon-based substrate 00, the specific number of the first semiconductor structure 111 and the second semiconductor structure 112 can be set according to actual needs, and the present invention does not make specific restrictions on this. In an optional embodiment, Figure 1 As shown, the semiconductor structure 11 of the first region 1 includes a first semiconductor structure 111 and two second semiconductor structures 112 located on the side of the first semiconductor structure 111 away from the silicon-based substrate 00. In another optional embodiment, as Figure 2 As shown, the semiconductor structure 11 of the first region 1 includes two first semiconductor structures 111 and a second semiconductor structure 112 located on a side of the two first semiconductor structures 111 away from the silicon-based substrate 00 .

[0064] The semiconductor structure 21 of the second region 2 may be a semiconductor structure formed by diffusion doping the surface of the second region of the silicon-based substrate 00 using a doping source, for example, using PH 3 Diffusion is performed from the surface of the second region 2 of the silicon-based substrate 00 , so that the surface of the second region 2 of the silicon-based substrate 00 forms an N-type semiconductor structure.

[0065] In addition, the solar cell further includes a first electrode 4 and a second electrode 5, wherein the materials of the first electrode 4 and the second electrode 5 may include silver, etc., and the silver paste may be printed on the surface of the semiconductor structure 11 of the first region 1 and the semiconductor structure 21 of the second region 2 away from the silicon-based substrate 00 by screen printing, and then the silver paste of the first region 1 and the second region 2 is sintered by laser sintering technology to form the first electrode 4 in contact with the semiconductor structure 11 of the first region 1 and the second electrode 5 in contact with the semiconductor structure 21 of the second region 2, respectively. It can also be understood that the first region 1 includes at least one first semiconductor structure 111, and the second region 2 includes at least one fourth semiconductor structure 211. Therefore, when the first electrode 4 in contact with the semiconductor structure 11 of the first region 1 and the second electrode 5 in contact with the semiconductor structure 21 of the second region 2 are formed by laser sintering technology, it is ensured that the first electrode 4 is not easy to penetrate the first semiconductor structure 111 in contact with the silicon-based substrate 00, and the second electrode 5 is not easy to penetrate the fourth semiconductor structure 211 in contact with the silicon-based substrate 00, thereby ensuring the integrity of the passivation contact structure on the surface of the solar cell and improving the performance and stability of the solar cell.

[0066] It should be noted that the above is only an exemplary illustration of the number of the first semiconductor structure 111 and the second semiconductor structure 112 in the semiconductor structure 11 of the first region 1. In the embodiment of the present invention, the number of the first semiconductor structure 111 and the second semiconductor structure 112 may be the same or different, and may be specifically designed according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0067] Optional, continue to refer to Figure 1 The solar cell further includes a passivation layer 6 and an anti-reflection layer 7 which are stacked and cover the semiconductor structure 11 of the first region, the isolation region 3, the semiconductor structure 12 of the second region and the front side 01.

[0068] Among them, the passivation layer 6 is used to protect the film layer below it, preventing the silicon-based substrate 00, the second polysilicon layer 201, the fourth polysilicon layer 402, etc. from being directly exposed to the air and being polluted by impurities, water oxygen, etc. in the air. At the same time, the presence of the passivation layer 6 can also improve the surface recombination effect, thereby reducing the loss of photogenerated carriers and improving the efficiency and performance of the solar cell. The passivation layer 6 may include aluminum oxide, etc., and aluminum oxide may be deposited on the semiconductor structure 11 in the first region, the isolation region 3, the semiconductor structure 12 in the second region, and the surface of the front 01 by atomic layer deposition (ALD) or the like to form a passivation layer.

[0069] The anti-reflection layer 7 can reduce the reflectivity of light, so that more light is absorbed by the solar cell, thereby improving the photoelectric conversion efficiency, and improving the efficiency and performance of the solar cell. The anti-reflection layer 7 may include a stacked structure of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and the anti-reflection layer 7 may be formed on the side of the passivation layer 6 away from the silicon-based substrate 00 by plasma enhanced chemical vapor deposition (PECVD). It can be understood that the first electrode 4 contacts the semiconductor structure 11 of the first region through the passivation layer 6 and the anti-reflection layer 7 covering the surface of the semiconductor structure 11 of the first region, and the second electrode 5 contacts the semiconductor structure 21 of the second region through the passivation layer 6 and the anti-reflection layer 7 covering the surface of the semiconductor structure 21 of the second region.

[0070] In this embodiment, a first region, a second region, and an isolation region between the first region and the second region are provided on the back side of a silicon-based substrate, so that the first region and the second region are isolated from each other by the isolation region, thereby preventing a short circuit between the first region and the second region; at the same time, at least one first semiconductor structure is provided in the semiconductor structure of the first region, and the first semiconductor structure includes a first tunneling oxide layer and a first polysilicon layer arranged in a stacked manner, so that corresponding carriers can be selectively transmitted through the first tunneling oxide layer, thereby reducing the recombination loss of electrons and holes, and helping to improve the open circuit voltage and short circuit current of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell; in addition, the semiconductor structure of the first region includes at least one first semiconductor structure and at least one second semiconductor structure located on the side of the first semiconductor structure away from the silicon-based substrate, and the second semiconductor structure includes a second tunneling oxide layer and a second polysilicon layer arranged in a stacked manner, and by making the second semiconductor structure The second tunneling oxide layer is a porous structure, so that the holes of the porous structure can have a smaller potential barrier, reducing the blocking of the second semiconductor structure to the carriers, reducing the resistance of the carriers so that the carriers of the first tunneling oxide layer in the semiconductor structure of the first zone can reach the first electrode, which is beneficial to improving the performance and efficiency of the solar cell; by arranging at least one first semiconductor structure in the first zone, so that the first electrode formed in contact with the semiconductor structure of the first zone is not easy to penetrate into the first semiconductor structure in contact with the silicon-based substrate, and because the semiconductor structure of the first zone includes multiple layers of polycrystalline silicon layers and multiple layers of tunneling oxide layers, the outer oxide layer of the multiple layers of tunneling oxide layers prevents the dopant from damaging the bottom oxide layer, and can maintain the passivation contact structure more completely, thereby improving the passivation performance and open circuit voltage of the battery, ensuring the integrity of the passivation contact structure on the surface of the solar cell, and improving the performance and stability of the solar cell.

[0071] Optional, continue to refer to Figure 2 The thickness T1 of at least one of the first tunneling oxide layer 101 and the second tunneling oxide layer 201 has a value range of 1 nm ≤ T1 ≤ 3 nm.

[0072] Specifically, the thickness T1 of each first tunneling oxide layer 101 and the second tunneling oxide layer 201 in the semiconductor structure 11 of the first zone 1 is between 1 nm and 3 nm. On the one hand, this thickness range ensures the effect of the first tunneling oxide layer 101 and the second tunneling oxide layer 201 selectively transmitting carriers to improve the open circuit voltage and short circuit current of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell; on the other hand, it ensures that the first tunneling oxide layer 101 and the second tunneling oxide layer 201 have sufficient thickness to have sufficient ability to block dopants from entering the tunneling oxide layer in contact with the silicon-based substrate 00, and at the same time prevent the first electrode 4 from penetrating into the first semiconductor structure 111 in contact with the silicon-based substrate 00 during the preparation process, thereby ensuring the integrity of the passivation contact structure on the surface of the solar cell and improving the performance and stability of the solar cell.

[0073] Optional, continue to refer to Figure 2 The thickness T2 of at least one of the first polysilicon layer 102 and the second polysilicon layer 202 has a value range of 50 nm ≤ T2 ≤ 400 nm.

[0074] Specifically, the thickness T2 of each first polysilicon layer 102 and the second polysilicon layer 202 in the semiconductor structure 11 in the first zone 1 is between 50nm and 400nm. This thickness range ensures, on the one hand, that the first polysilicon layer 102 and the second polysilicon layer 202 have the effect of improving the electron transmission efficiency of the solar cell, and on the other hand, ensures that the first polysilicon layer 102 and the second polysilicon layer 202 have sufficient thickness to prevent the first electrode 4 from penetrating into the first semiconductor structure 111 in contact with the silicon-based substrate 00 during the preparation process, thereby ensuring the integrity of the passivation contact structure on the surface of the solar cell and improving the performance and stability of the solar cell.

[0075] Optional, Figure 3 and Figure 4 is a schematic diagram of the structure of two other solar cells provided by the embodiments of the present invention, such as Figure 3 or Figure 4 As shown, the semiconductor structure 11 of the first region also includes at least one third semiconductor structure 113; the third semiconductor structure 113 includes a third tunneling oxide layer 301 and a third polysilicon layer 302 which are stacked; the third semiconductor structure 113 is located on the side of the second semiconductor structure 112 away from the silicon-based substrate 00, and / or the third semiconductor structure 113 is located between two adjacent second semiconductor structures 112.

[0076] It can be understood that the semiconductor structure 11 of the first region includes at least one third semiconductor structure 113, that is, the semiconductor structure 11 of the first region 1 includes one or more third semiconductor structures 113, wherein the third semiconductor structure 113 also includes a stacked third tunneling oxide layer 301 and a third polysilicon layer 302. The thickness of the third tunneling oxide layer 301 is also between 1nm and 3nm, and the thickness of the third polysilicon layer 302 is also between 50nm and 400nm.

[0077] In an exemplary embodiment, referring to Figure 3 The semiconductor structure 11 of the first region 1 includes a first semiconductor structure 111, a second semiconductor structure 112 located on the side of the first semiconductor structure 111 away from the silicon-based substrate 00, and two third semiconductor structures 113 located on the side of the second semiconductor structure 112 away from the silicon-based substrate 00. It can be understood that the second tunneling oxide layer 201 in the second semiconductor structure 112 is a porous structure. By arranging the second semiconductor structure 112 between the first semiconductor structure 111 and the third semiconductor structure 113, the first semiconductor structure 111 can selectively penetrate the second semiconductor structure 111. Overcarriers, and the second semiconductor structure 112 can reduce the carrier tunneling resistance, so that more carriers can pass through the second semiconductor structure 112, thereby maximizing the performance and efficiency of the solar cell. By setting a third semiconductor structure 113 on the side of the second semiconductor structure 112 away from the silicon-based substrate, the third tunneling oxide layer 301 of the third semiconductor structure 113 is a full-surface structure, so that the third tunneling oxide layer 301 can further block the entry of dopants, thereby preventing dopants from destroying the first tunneling oxide layer 101 in the first semiconductor structure 111.

[0078] In another exemplary embodiment, referring to Figure 4 The semiconductor structure 11 in the first region 1 includes a first semiconductor structure 111, two second semiconductor structures 112 located on the side of the first semiconductor structure 111 away from the silicon-based substrate 00, and a third semiconductor structure 113 located between the two second semiconductor structures 112. By arranging the third semiconductor structure 113 between two adjacent second semiconductor structures 112, in the semiconductor structure 11 in the first region 1, the first tunneling oxide layer 101 of the first semiconductor structure 111 can selectively transmit carriers, and the second tunneling oxide layer 201 of the second semiconductor structure 112 can reduce the carrier tunneling resistance. At the same time, the third tunneling oxide layer 301 of the third semiconductor structure 113 further blocks the entry of dopants, thereby preventing the dopants from damaging the first tunneling oxide layer 101 in the first semiconductor structure 111.

[0079] It can also be understood that, under the premise of ensuring that the second semiconductor structure 112 and the third semiconductor structure 113 are both located on the side of the first semiconductor structure 111 away from the silicon-based substrate 00, the specific number and stacking arrangement of the second semiconductor structure 112 and the third semiconductor structure 113 can be set according to actual needs, and the present invention does not make specific limitations on this.

[0080] Based on the above embodiment, optionally, Figure 5 As shown, the semiconductor structure 21 of the second region includes at least one fourth semiconductor structure 211, wherein the fourth semiconductor structure 211 includes a fourth tunneling oxide layer 401 and a fourth polysilicon layer 402 arranged in a stacked manner. Specifically, the fourth tunneling oxide layer 401 can be grown in the second region 2 by thermal oxidation, chemical oxidation or chemical vapor deposition, and the fourth tunneling oxide layer 401 can include SiO2, etc. The fourth tunneling oxide layer 401 can play a role in surface passivation and carrier selective transmission, which helps to improve the open circuit voltage and short circuit current of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell. Among them, when the semiconductor structure 21 of the second region 2 is N-type, the fourth polysilicon layer 402 can be specifically understood as a polysilicon layer doped with phosphorus.

[0081] Specifically, after the fourth tunneling oxide layer 401 is formed on the surface of the second region 2 of the silicon-based substrate 00, silane can be introduced to form a polysilicon layer by low-pressure chemical vapor deposition (LPCVD), or a polysilicon layer can be deposited on the surface of the fourth tunneling oxide layer 401 by plasma enhanced chemical vapor deposition (PECVD); after the polysilicon layer is formed, PH3 can be used as a phosphorus diffusion source to diffuse phosphorus atoms into the polysilicon, thereby doping the polysilicon and forming a phosphorus-doped fourth polysilicon layer 402.

[0082] It should be noted that the number of the fourth semiconductor structures 21 in the semiconductor structure 21 of the second region 2 can be set according to actual needs, and the present invention does not specifically limit this. Figure 5 , the second region 2 includes a fourth semiconductor structure 21. In another optional embodiment, as Figure 6 As shown, the second region 2 includes two fourth semiconductor structures 21 .

[0083] When the number of fourth semiconductor structures 21 is greater than 1, fourth tunneling oxide layers 401 and fourth polysilicon layers 402 can be alternately formed, and after the fourth polysilicon layer 402 is formed, PH3 can be used as a phosphorus diffusion source to dope the fourth polysilicon layer 402, so that phosphorus atoms can at least diffuse into the fourth polysilicon layer 402, at least to achieve doping of the fourth polysilicon layer 402, and form a fourth polysilicon layer 402 with a phosphorus-doped type. At this time, the semiconductor structure 21 of the second zone 2 may include at least one fourth polysilicon layer 402 and at least one fourth tunneling oxide layer 401 respectively located between the fourth polysilicon layer 402 and the silicon-based substrate 00, and between two adjacent fourth polysilicon layers 402, so that when the fourth polysilicon layer 402 is doped, the fourth tunneling oxide layer 401 located between the fourth polysilicon layers 402 can prevent the entry of dopants, thereby preventing the dopants from damaging the fourth tunneling oxide layer 401 in contact with the silicon-based substrate 00, thereby ensuring the integrity of the fourth tunneling oxide layer 401 in contact with the silicon-based substrate 00, thereby ensuring that the semiconductor structure 21 of the second zone 2 has a complete passivation contact structure, which is beneficial to improving the passivation performance, open circuit voltage and short-circuit current of the solar cell.

[0084] Optional, such as Figure 7 As shown, the semiconductor structure 21 in the second region includes at least one fifth semiconductor structure 212 located on the side of the fourth semiconductor structure 211 away from the silicon-based substrate 00; the fifth semiconductor structure 212 includes a fifth tunneling oxide layer 501 and a fifth polysilicon layer 502 arranged in stacked layers; the fifth tunneling oxide layer 501 is a porous structure.

[0085] Specifically, the semiconductor structure 21 of the second region includes at least one fourth semiconductor structure 211 and at least one fifth semiconductor structure 212 located on the side of the fourth semiconductor structure 211 away from the silicon-based substrate 00, that is, the semiconductor structure 21 of the second region may include one or more fourth semiconductor structures 211 and one or more fifth semiconductor structures 212, and the fourth tunneling oxide layer 401 in the fourth semiconductor structure 211 may cover the second region 2 to achieve selective permeation of carriers; the fifth tunneling oxide layer 501 of the fifth semiconductor structure 212 is a porous structure, and the porous structure has The body can be understood as a tunneling oxide layer structure with a plurality of holes arranged at intervals, so that after the carriers selectively passing through the fourth semiconductor structure 211 reach the fifth tunneling oxide layer 501 of the fifth semiconductor structure 212, they can directly pass through the fifth tunneling oxide layer 501 of the fifth semiconductor structure 212 from the hole position, thereby reducing the potential barrier in the fifth tunneling oxide layer 501 of the fifth semiconductor structure 212, enabling more carriers to pass through the fifth semiconductor structure 212, reducing the tunneling resistance of the carriers, thereby helping to optimize the transmission path of the carriers and improving the performance and efficiency of the solar cell. Among them, the thickness of the fourth tunneling oxide layer 401 and the fifth tunneling oxide layer 501 can also range from 1nm to 3nm, and the thickness of the fourth polysilicon layer 402 and the fifth polysilicon layer 502 can also range from 50nm to 400nm.

[0086] It should be noted that, under the premise of ensuring that the fifth semiconductor structure 212 is located on the side of the fourth semiconductor structure 211 away from the silicon-based substrate 00, the specific number of the fourth semiconductor structure 211 and the fifth semiconductor structure 212 can be set according to actual needs, and the present invention does not make specific limitations on this. Figure 7 , the semiconductor structure 21 in the second region 2 includes a fourth semiconductor structure 211 and two fifth semiconductor structures 212 located on the side of the fourth semiconductor structure 211 away from the silicon-based substrate 00. In another optional embodiment, as Figure 8 As shown, the semiconductor structure 21 in the second region includes two fourth semiconductor structures 211 and a fifth semiconductor structure 212 located on a side of the two fourth semiconductor structures 211 away from the silicon-based substrate 00 .

[0087] Optional, Fig. 9 and Fig.10 is a schematic diagram of the structure of two other solar cells provided by the embodiments of the present invention, such as Fig. 9 or Fig.10As shown, the semiconductor structure 21 of the second region also includes at least one sixth semiconductor structure 213; the sixth semiconductor structure 213 includes a sixth tunneling oxide layer 601 and a sixth polysilicon layer 602 that are stacked; the sixth semiconductor structure 213 is located on the side of the fifth semiconductor structure 212 that is away from the silicon-based substrate 00, and / or the sixth semiconductor structure 213 is located between two adjacent second doped structures 212.

[0088] It is understandable that the semiconductor structure 21 in the second region includes at least one sixth semiconductor structure 213, that is, the semiconductor structure 21 in the second region includes one or more sixth semiconductor structures 213, wherein the sixth semiconductor structure 213 also includes a sixth tunneling oxide layer 601 and a sixth polysilicon layer 602 that are stacked.

[0089] In an exemplary embodiment, referring to Fig. 9 The semiconductor structure 21 of the second region 2 includes a fourth semiconductor structure 211, a fifth semiconductor structure 212 located on the side of the fourth semiconductor structure 211 away from the silicon-based substrate 00, and two sixth semiconductor structures 213 located on the side of the fifth semiconductor structure 212 away from the silicon-based substrate 00. It can be understood that the fifth tunneling oxide layer 501 in the fifth semiconductor structure 212 is a porous structure. By arranging the fifth semiconductor structure 212 between the fourth semiconductor structure 211 and the sixth semiconductor structure 213, the fourth semiconductor structure 211 can selectively penetrate the oxide layer 501. Overcarriers, and the fifth semiconductor structure 212 can reduce the carrier tunneling resistance, so that more carriers can pass through the fifth semiconductor structure 212, and maximize the performance and efficiency of the solar cell. On the premise of arranging the sixth semiconductor structure 213 on the side of the fifth semiconductor structure 212 away from the silicon-based substrate, the sixth tunneling oxide layer 601 of the sixth semiconductor structure 213 is a full-surface structure, so that the sixth tunneling oxide layer 601 can further block the entry of dopants, thereby preventing dopants from damaging the fourth tunneling oxide layer 401 in the fourth semiconductor structure 211. The thickness of the sixth tunneling oxide layer 601 can also be between 1nm and 3nm, and the thickness of the sixth polysilicon layer 602 can also be between 50nm and 400nm.

[0090] In another exemplary embodiment, referring to Fig.10The semiconductor structure 21 of the second region 2 includes a fourth semiconductor structure 211, two fifth semiconductor structures 212 located on the side of the fourth semiconductor structure 211 away from the silicon-based substrate 00, and a sixth semiconductor structure 213 located between the two fifth semiconductor structures 212. By arranging the sixth semiconductor structure 213 between two adjacent fifth semiconductor structures 212, in the semiconductor structure 21 of the second region 2, the fourth tunneling oxide layer 401 of the fourth semiconductor structure 211 can selectively transmit carriers, and the fifth tunneling oxide layer 501 of the fifth semiconductor structure 212 can reduce the carrier tunneling resistance. At the same time, the sixth tunneling oxide layer 601 of the sixth semiconductor structure 213 can further block the entry of dopants, thereby preventing the dopants from damaging the fourth tunneling oxide layer 401 in the fourth semiconductor structure 211.

[0091] It can also be understood that, under the premise of ensuring that the fifth semiconductor structure 212 and the sixth semiconductor structure 213 are both located on the side of the fourth semiconductor structure 211 away from the silicon-based substrate 00, the specific number and stacking arrangement of the fifth semiconductor structure 212 and the sixth semiconductor structure 213 can be set according to actual needs, and the present invention does not make specific restrictions on this. At the same time, the specific number and stacking arrangement of each doping structure in the semiconductor structure 11 of the first zone 1 and the specific number and stacking arrangement of each doping structure in the semiconductor structure 21 of the second zone 2 can be set independently of each other, that is, the specific number and stacking arrangement of each doping structure in the semiconductor structure 11 of the first zone 1 and the specific number and stacking arrangement of each doping structure in the semiconductor structure 21 of the second zone 2 can have a variety of combinations, which will not be repeated here.

[0092] Optional, Fig.11 is a schematic diagram of a porous structure provided by an embodiment of the present invention, such as Fig.11 As shown, the range of the hole size W is: 0.05μm≤W≤5μm.

[0093] Specifically, the second tunneling oxide layer 201 of the second semiconductor structure 112 in the semiconductor structure 11 of the first region 1 is a porous structure, and when the semiconductor structure 21 of the second region 2 includes a fifth semiconductor structure 212, the fifth tunneling oxide layer 501 of the fifth semiconductor structure 212 is also a porous structure. Since the porous structure includes a plurality of holes arranged at intervals, the position of the hole is not provided with a tunneling oxide layer, so that there is a smaller potential barrier at the position, ensuring that more carriers pass through the tunneling oxide layer on the porous structure side.

[0094] It is understandable that when the size of the holes in the porous structure is too small, the proportion of the holes is small, and there will be a certain potential barrier at the non-hole position, which limits the transmission of carriers; when the size of the holes in the porous structure is too large, the second tunneling oxide layer 201 and the fifth tunneling oxide layer 501 cannot have sufficient ability to block dopants, resulting in the destruction of the passivation contact structure on the surface of the solar cell. Therefore, by setting the size of the holes in the porous structure between 0.05μm and 5μm, the porous structure has holes of appropriate size, thereby ensuring the integrity of the passivation contact structure on the surface of the solar cell, improving the performance and stability of the solar cell, and ensuring that the second tunneling oxide layer 201 and the fifth tunneling oxide layer 501 can optimize the transmission path of the carriers, so that more carriers can pass through the second tunneling oxide layer 201 and the fifth tunneling oxide layer 501, thereby maximizing the performance and efficiency of the solar cell.

[0095] Optional, continue to refer to Fig.11 In the porous structure, the distance L between two adjacent holes ranges from 0.1 μm to 100 μm.

[0096] It can be understood that when the distance between two adjacent holes in the porous structure is too small, the holes in the porous structure will be connected, making the second tunneling oxide layer 201 and the fifth tunneling oxide layer 501 unable to block the dopant, allowing the dopant to enter the first tunneling oxide layer 101 and the fourth tunneling oxide layer 401 in contact with the silicon-based substrate 00, resulting in the destruction of the passivation contact structure on the surface of the solar cell; when the distance between two adjacent holes in the porous structure is too large, the proportion of the holes is small, and the potential barrier formed by the second tunneling oxide layer 201 and the fifth tunneling oxide layer 501 is large, which limits the transmission of carriers. Therefore, by setting the spacing between the multiple holes spaced apart in the porous structure to be between 0.1 μm and 100 μm, a suitable spacing design is made between two adjacent holes to ensure the stability of the second tunneling oxide layer 201 and the fifth tunneling oxide layer 501 structure, have sufficient blocking ability for dopants, ensure the integrity of the passivation contact structure on the surface of the solar cell, and improve the performance and stability of the solar cell. On the premise of this, it is ensured that the second tunneling oxide layer 201 and the fifth tunneling oxide layer 501 can optimize the transmission path of carriers, so that more carriers can pass through the second tunneling oxide layer 201 and the fifth tunneling oxide layer 501, thereby maximizing the performance and efficiency of the solar cell.

[0097] Based on the same inventive concept, an embodiment of the present invention further provides a solar cell, such as Fig.12As shown, the solar cell includes a silicon-based substrate 00, including a front side 01 and a back side 02 opposite to each other; the back side 02 includes a first region 1, a second region 2, and an isolation region 3 located between the first region 1 and the second region 2; semiconductor structures located in the first region 1 and the second region 2 respectively; the semiconductor structure 11 of the first region 1 is of opposite type to the semiconductor structure 21 of the second region 2; the semiconductor structure 11 of the first region 1 includes a first tunneling oxide layer 101 and a first polysilicon layer 102 arranged in a stacked manner; the semiconductor structure 11 of the first region 1 also includes at least one second tunneling oxide layer 201 arranged in the first polysilicon layer 102; the second tunneling oxide layer 201 is a porous structure; the porous structure includes a plurality of holes arranged at intervals; a first electrode 4 is in contact with the semiconductor structure 11 of the first region 1; and a second electrode 5 is in contact with the semiconductor structure 21 of the second region 2.

[0098] Among them, the first polysilicon layer 102 includes at least one second tunneling oxide layer 201, that is, the first polysilicon layer 102 may include one or more layers of the second tunneling oxide layer 201, and the second tunneling oxide layer 201 is a porous structure. The porous structure can be specifically understood as a tunneling oxide layer structure with a plurality of holes arranged at intervals, so that after the carriers that selectively penetrate the first tunneling oxide layer 201 reach the second tunneling oxide layer 201 in the first polysilicon layer 102, they can directly pass through the second tunneling oxide layer 201 of the first polysilicon layer 102 from the hole position, thereby reducing the potential barrier in the second tunneling oxide layer 201 of the first polysilicon layer 102, enabling more carriers to pass through the first polysilicon layer 102, reducing the tunneling resistance of the carriers, thereby helping to optimize the carrier transmission path and improving the performance and efficiency of solar cells.

[0099] Optional, continue to refer to Fig.12 The semiconductor structure 21 of the second region 2 includes a fourth tunneling oxide layer 401 and a fourth polysilicon layer 402 which are stacked; the semiconductor structure 21 of the second region 2 also includes at least one fifth tunneling oxide layer 501 which is arranged in the fourth polysilicon layer 402; the fifth tunneling oxide layer 501 is a porous structure.

[0100] Among them, the fourth polysilicon layer 402 includes at least one fifth tunneling oxide layer 501, that is, the fourth polysilicon layer 402 may include one or more layers of the fifth tunneling oxide layer 501, and the fifth tunneling oxide layer 501 is a porous structure. The porous structure can be specifically understood as a tunneling oxide layer structure with a plurality of holes arranged at intervals, so that the carriers that selectively pass through the fourth tunneling oxide layer 401 can directly pass through the fifth tunneling oxide layer 501 of the fourth polysilicon layer 402 from the hole position after reaching the fifth tunneling oxide layer 501 in the fourth polysilicon layer 402, thereby reducing the potential barrier in the fifth tunneling oxide layer 501 of the fourth polysilicon layer 402, enabling more carriers to pass through the fourth polysilicon layer 402, reducing the tunneling resistance of the carriers, thereby helping to optimize the transmission path of the carriers and improving the performance and efficiency of the solar cell.

[0101] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a solar cell. Fig.13 is a flow chart of a method for preparing a solar cell provided by an embodiment of the present invention, Fig.14 is a process flow chart of a solar cell manufacturing method provided by an embodiment of the present invention, and is combined with reference to Fig.13 and Fig.14 As shown, the method for preparing the solar cell includes:

[0102] S101. Provide a silicon-based substrate.

[0103] The silicon-based substrate 00 includes a front side 01 and a back side 02 opposite to each other; the back side 02 includes a first region 1 , a second region 2 , and an isolation region 3 located between the first region 1 and the second region 2 .

[0104] It is understandable that the silicon-based substrate 00 can be an N-type silicon-based substrate or a P-type silicon-based substrate. Specifically, the silicon-based substrate 00 can be chemically polished on both sides by an alkali polishing tank machine. The alkaline polishing liquid will corrode the surface of the silicon-based substrate 00 to remove the cutting damage on the surface of the silicon-based substrate 00, and can form a microstructure on the surface of the silicon-based substrate 00. The microstructure is a tower base formed on the surface of the silicon-based substrate. The presence of the tower base enables the silicon-based substrate 00 to have a larger surface area, thereby enabling the silicon-based substrate 00 to have a larger light contact surface, which is conducive to improving the photoelectric conversion efficiency of the silicon-based substrate 00. In addition, the back side of the silicon-based substrate 00 includes a first area 1 and a second area 2. The back side of the silicon-based substrate 00 also includes an isolation area 3 located between the first area 1 and the second area 2. The isolation area 3 can be formed by a process such as wet etching. The isolation area 3 between the first area 1 and the second area 2 can isolate the P area and the N area from each other to prevent short circuit between the first area 1 and the second area 2 and leakage.

[0105] S102 , forming semiconductor structures in the first region and the second region respectively.

[0106] Among them, the semiconductor structure 11 of the first zone 1 is of opposite type to the semiconductor structure 21 of the second zone 2, that is, when the semiconductor structure 11 of the first zone 1 is of P type, the semiconductor structure 21 of the second zone 2 is of N type; when the semiconductor structure 11 of the first zone 1 is of N type, the semiconductor structure 21 of the second zone 2 is of P type; the semiconductor structure 11 of the first zone 1 includes at least one first semiconductor structure 111 and at least one second semiconductor structure 112 located on the side of the first semiconductor structure 111 away from the silicon-based substrate 00; the first semiconductor structure 111 includes a first polysilicon layer 102; the second semiconductor structure 112 includes a second tunneling oxide layer 201 and a second polysilicon layer 202 arranged in a stacked manner; the second tunneling oxide layer 201 is a porous structure; the porous structure includes a plurality of holes arranged at intervals.

[0107] Optionally, the semiconductor structure 21 of the second region 2 includes at least one fourth semiconductor structure 211 ; the fourth semiconductor structure 211 includes a fourth polysilicon layer 402 .

[0108] On the basis of the above embodiment, optionally, the first semiconductor structure 111 may further include a first tunneling oxide layer 101 located between the first polysilicon layer 102 and the silicon-based substrate 00 .

[0109] On the basis of the above embodiment, optionally, the fourth semiconductor structure 211 may further include a fourth tunneling oxide layer 401 located between the fourth polysilicon layer 402 and the silicon-based substrate 00 .

[0110] It can be understood that when forming the semiconductor structure 11 of the first region 1 and the semiconductor structure 21 of the second region 2, the semiconductor structure 11 of the first region 1 can be formed first and then the semiconductor structure 21 of the second region 2, or the semiconductor structure 21 of the second region 2 can be formed first and then the semiconductor structure 11 of the first region 1. The present invention does not specifically limit the order of forming the semiconductor structure 11 of the first region 1 and the semiconductor structure 21 of the second region 2. For the convenience of description, without special limitations, the embodiments of the present invention take the example of first forming the semiconductor structure 11 of the first region 1 and then forming the semiconductor structure 21 of the second region 2 to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0111] Specifically, the semiconductor structure 11 in the first region 1 may include: a first tunneling oxide layer 101 and a first polysilicon layer 102 may be alternately formed, and after forming the first polysilicon layer 102, a first type of dopant may be used to dope the first polysilicon layer 102, so that the first polysilicon layer 102 is a polysilicon layer having a first doping type. The first tunneling oxide layer 101 is grown in the first region 1 by thermal oxidation, chemical oxidation, or chemical vapor deposition. For example, the silicon-based substrate 00 may be placed in a high-oxygen solution to oxidize the surface of the silicon-based substrate 00, thereby forming the first tunneling oxide layer 101. Alternatively, the silicon-based substrate 00 may be heated while oxygen is introduced so that the silicon-based substrate is in a high-temperature, high-oxygen environment to form the first tunneling oxide layer 101. The first tunneling oxide layer 101 may include, for example, SiO 2 When forming the first tunneling oxide layer 101, silane may be introduced to form the first polysilicon layer 102 by low pressure chemical vapor deposition (LPCVD) or the like, or the first polysilicon layer 102 may be deposited on the surface of the first tunneling oxide layer 101 by plasma enhanced chemical vapor deposition (PECVD), thereby realizing a structure in which the first tunneling oxide layer 101 and the first polysilicon layer 102 are alternately formed. When the semiconductor structure 11 of the first region 1 is of P type, the first polysilicon layer 102 having the first doping type may be specifically understood as a polysilicon layer doped with boron. After forming the first polysilicon layer 102, BCl 3 or BBr 3 As a boron diffusion source, boron atoms are diffused into the first polysilicon 102 to achieve doping of the first polysilicon 102, thereby forming a first polysilicon layer 102 with a boron doping type. For example, the range of the doping concentration on the surface of the first polysilicon layer 102 can be 1×10 19 cm -3 -2×10 20 cm -3 .

[0112] In addition, while the boron is diffused into the polysilicon layer, a diffusion byproduct is formed on the surface of the polysilicon layer, namely, borosilicate glass. The borosilicate glass can be used as a mask structure of the first region 1 to protect the first polysilicon layer 102 and the first tunneling oxide layer 101 in the first region 1 in subsequent process steps.

[0113] It can also be understood that due to process limitations, while the semiconductor structure 11 of the first zone 1 is formed, the semiconductor structure 11 of the first zone 1 will also be formed on other surfaces of the silicon-based substrate 00. In order to ensure the performance of the prepared solar cell, it is necessary to remove the semiconductor structure 11 of the first zone 1 at other locations on the surface of the silicon-based substrate 00 except for the first zone 1.

[0114] In an optional embodiment, laser can be used to perform laser film opening on the second area 2 and the isolation area 3 on the back of the silicon-based substrate 00, and the borosilicate glass and part of the second polysilicon layer 202 in the second area 2 and the isolation area 3 are removed according to the patterns of the second area 2 and the isolation area 3 to expose the semiconductor structure 11 of the first area 1 remaining in the second area 2 and the isolation area 3. Exemplarily, the laser for laser film opening on the second area 2 and the isolation area 3 of the silicon-based substrate 00 can include a picosecond or femtosecond laser with a wavelength of 532nm or 355nm, and the repetition frequency of the laser can be 100KHz to 1000KHz, wherein the power of the laser is adjustable, the optical path is matched with a diffractive optical element (DOE), and the laser device has the ability to scan complex patterns. At the same time, due to the narrow pulse width of the picosecond laser, the damage produced is small, which is conducive to removing the borosilicate glass and part of the second polysilicon layer 202 in the second area 2 and the isolation area 3 in a nearly lossless state. After removing the borosilicate glass and part of the second polysilicon layer 202 in the second region 2 and the isolation region 3, the borosilicate glass on the front side 01 can be removed by single-sided wet etching. For example, the borosilicate glass on the front side 01 can be removed by single-sided chain equipment using hydrofluoric acid. After removing the borosilicate glass in the second region 2, the isolation region 3 and the front side 01, the semiconductor structure 11 of the first region 1 around the second region 2, the isolation region 3 and the front side 01 is removed by an alkali polishing tank machine. It can be understood that when the silicon-based substrate 00 is alkali-polished, borosilicate glass exists on the surface of the first region 1, so that the semiconductor structure 11 in the first region 1 can be protected by the borosilicate glass without being etched. Among them, after using laser to remove borosilicate glass and part of the first polysilicon layer 102, the reaction time of the semiconductor structure 11 in the first zone 1 in the next step of alkali corrosion can be reduced. At the same time, the laser energy is absorbed by the borosilicate glass and part of the second polysilicon layer 202, reducing the risk of laser energy being transmitted downward and avoiding the thermal impact of the laser energy on the second polysilicon layer 202 and the underlying second tunneling oxide layer 201.

[0115] After removing the semiconductor structure 11 of the first region 1 at other positions on the surface of the silicon-based substrate 00 except the first region 1, the semiconductor structure 21 of the second region can be formed. The fourth tunneling oxide layer 401 and the fourth polysilicon layer 402 can be formed alternately. The fourth tunneling oxide layer 401 can be grown in the second region 2 by thermal oxidation, chemical oxidation or chemical vapor deposition. The fourth tunneling oxide layer 401 can include, for example, SiO 2Etc. When forming the fourth tunneling oxide layer 401, silane is introduced to form the fourth polysilicon layer 402 by low pressure chemical vapor deposition (LPCVD), or the fourth polysilicon layer 402 can be deposited on the surface of the fourth tunneling oxide layer 401 by plasma enhanced chemical vapor deposition (PECVD). The fourth tunneling oxide layer 401 can be formed in a manner similar to the first tunneling oxide layer 101, and the fourth polysilicon layer 402 can be formed in a manner similar to the first polysilicon layer 102. For details, reference can be made to the above description of the formation of the first tunneling oxide layer 101 and the first polysilicon layer 102.

[0116] When the semiconductor structure 21 of the second region 2 is of N type, the fourth polysilicon layer 402 can be specifically understood as a polysilicon layer doped with phosphorus. 3 As a phosphorus diffusion source, phosphorus atoms are diffused into the fourth polysilicon 402 to achieve doping of the fourth polysilicon 402, forming a fourth polysilicon layer 402 with a phosphorus doping type. For example, the surface doping concentration of the fourth polysilicon layer 402 may range from 1×10 19 cm -3 -2×10 20 cm -3 .

[0117] In addition, while the boron is diffused into the polysilicon layer, a diffusion byproduct is formed on the surface of the fourth polysilicon layer, namely, phosphosilicate glass. The phosphosilicate glass can be used as a mask structure of the second region 2 to protect the fourth polysilicon layer 402 and the fourth tunneling oxide layer 401 in the second region 2 in subsequent process steps.

[0118] It can also be understood that due to process limitations, while forming the semiconductor structure 21 of the second zone 2, the semiconductor structure 21 of the second zone 2 will also be formed on other surfaces of the silicon-based substrate 00. In order to ensure the performance of the prepared solar cell, it is necessary to remove the semiconductor structure 21 of the second zone 2 at other locations on the surface of the silicon-based substrate 00 except for the second zone 2.

[0119] In an optional embodiment, a laser may be used to perform laser film opening on the first area 1 and the isolation area 3 on the back side of the silicon-based substrate 00, and the phosphorus silicon glass and part of the fourth polysilicon layer 402 in the first area 1 and the isolation area 3 are removed according to the patterns of the first area 1 and the isolation area 3 to expose the semiconductor structure 21 of the second area 2 remaining in the first area 1 and the isolation area 3. Exemplarily, the laser for laser film opening on the first area 1 and the isolation area 3 on the back side of the silicon-based substrate 00 may include a picosecond or femtosecond laser with a wavelength of 532nm or 355nm, and the repetition frequency of the laser may be 100KHz to 1000KHz, wherein the power of the laser is adjustable, the optical path is matched with a diffractive optical element (DOE), and the laser device has the ability to scan complex patterns. At the same time, due to the narrow pulse width of the picosecond laser, the damage produced is small, which is conducive to removing the phosphorus silicon glass in the first area 1 and the isolation area 3 in a nearly lossless state. In addition, removing the phosphosilicate glass and part of the fourth polysilicon layer 402 in the first region 1 and the isolation region 3 by laser film opening can reduce the reaction time when the semiconductor structure 21 in the second region 2 on the surface of the first region 1 and the isolation region 3 is subsequently removed by alkaline corrosion. At the same time, the laser energy is absorbed by the borosilicate glass and part of the fourth polysilicon layer 402, reducing the risk of laser energy being transmitted downward and avoiding the thermal impact of the laser energy on the fourth polysilicon layer 402 and the underlying fourth tunneling oxide layer 401.

[0120] After removing the phosphosilicate glass in the first area 1 and the isolation area 3, the phosphosilicate glass on the front side 01 can be removed by single-sided wet etching. For example, the phosphosilicate glass on the front side 01 can be removed by single-sided chain equipment using hydrofluoric acid to save resources and improve production efficiency. After removing the phosphosilicate glass in the first area 1, the isolation area 3 and the front side 01, the semiconductor structure 21 of the second area 2 around the first area 1, the isolation area 3 and the front side 01 is removed by an alkali polishing tank machine. It can be understood that when the silicon-based substrate 00 is alkali-polished, there is phosphosilicate glass on the surface of the second area 2, so that the semiconductor structure 21 in the second area 2 can be protected by the phosphosilicate glass without being etched.

[0121] It can also be understood that after removing the semiconductor structure 21 of the second area 2 on the surface of the silicon-based substrate 00 except the second area 2, the silicon-based substrate 00 of the isolation area 3 and the front side 01 can be exposed, and by further polishing the silicon-based substrate 00 with an alkaline solution, the isolation area 3 and the front side 01 of the silicon-based substrate 00 can be corroded, thereby forming a tower base again in the isolation area 3 and the front side 01 of the silicon-based substrate 00, ensuring that the surface of the silicon-based substrate 00 has a larger light receiving area; at the same time, after polishing the surface of the silicon-based substrate 00, the impurities on the surface of the silicon-based substrate 00 can be removed, thereby ensuring the cleanliness of the surface of the silicon-based substrate 00 and improving the yield of the film layer formed in the subsequent process.

[0122] It can also be understood that in the process of manufacturing solar cells, borosilicate glass is used to protect the semiconductor structure 11 of the first area 1, and phosphosilicate glass is used to protect the semiconductor structure 21 of the second area 2. Before completing the process of manufacturing solar cells, it is necessary to remove the borosilicate glass in the first area 1 and the phosphosilicate glass in the second area 2 to prevent the presence of borosilicate glass and phosphosilicate glass from affecting the conversion efficiency of the solar cell, while providing a good foundation for subsequent processes. Among them, the method of removing borosilicate glass and phosphosilicate glass may include but is not limited to laser removal or wet removal. For example, hydrofluoric acid may be used to etch borosilicate glass and phosphosilicate glass to remove the borosilicate glass in the first area 1 and the phosphosilicate glass in the second area 2.

[0123] In an optional embodiment, after removing the borosilicate glass of the first region 1 and the phosphosilicate glass of the second region 2, aluminum oxide can be deposited on the first doping structure 11, the isolation region 3, the second doping structure 12 and the surface of the front side 01 by atomic layer deposition (ALD) to form a passivation layer, and an anti-reflection layer 7 can be formed on the side of the passivation layer 6 away from the silicon-based substrate 00 by plasma enhanced chemical vapor deposition (PECVD). The anti-reflection layer 7 may include a stacked structure of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0124] S103 , forming a first electrode in contact with the semiconductor structure in the first region, and a second electrode in contact with the semiconductor structure in the second region.

[0125] Specifically, the first electrode 4 and the second electrode 5 may include silver electrodes, etc., and the silver paste may be printed on the surface of the first area 1 and the second area 2 on the side away from the silicon-based substrate 00 by screen printing, and then the silver paste of the first area 1 and the second area 2 may be sintered by laser sintering technology to form the first electrode 4 in contact with the semiconductor structure 11 of the first area and the second electrode 5 in contact with the semiconductor structure 21 of the second area, respectively, so as to form a passivation contact structure. It can also be understood that the first area 1 includes at least one first semiconductor structure 111, and the second area 2 includes at least one fourth semiconductor structure 211. Therefore, when the first electrode 4 in contact with the semiconductor structure 11 of the first area 1 and the second electrode 5 in contact with the semiconductor structure 21 of the second area 2 are formed by laser sintering technology, it is ensured that the first electrode 4 is not easy to penetrate the first semiconductor structure 111 in contact with the silicon-based substrate 00, and the second electrode 5 is not easy to penetrate the fourth semiconductor structure 211 in contact with the silicon-based substrate 00, thereby ensuring the integrity of the passivation contact structure on the surface of the solar cell, and improving the performance and stability of the solar cell.

[0126] Optionally, while forming the first electrode 4 and the second electrode 5, a main grid electrode of the back side 02 is also formed, and the first electrode 4 and the second electrode 5 can be electrically connected to an external device or other solar cell through the main grid electrode. The main grid electrode can be formed in a similar manner to the first electrode 4 and the second electrode 5, that is, the main grid electrode, the first electrode 4 and the second electrode 5 can be manufactured under the same process, and the specific implementation method can be designed according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0127] In addition, after the preparation of solar cells is completed, the electrical properties of the solar cells need to be tested, such as the open circuit voltage, maximum output power, conversion efficiency, etc. of the solar cells, so as to sort and store the solar cells.

[0128] The above-mentioned method for preparing a solar cell can prepare a solar cell provided by any embodiment of the present invention, and has the corresponding functions and beneficial effects of a solar cell. For technical details not described in detail in this embodiment, please refer to the solar cell provided by any embodiment of the present invention.

[0129] Since the above-described method for preparing solar cells can prepare the solar cells in the embodiment of the present invention, based on the solar cells described in the embodiment of the present invention, the skilled person in the art can understand the specific implementation of the method for preparing solar cells in the embodiment of the present invention and its various variations, so how the method for preparing solar cells can achieve the preparation of the solar cells in the embodiment of the present invention is not described in detail here. As long as the skilled person in the art implements the method for preparing the solar cells in the embodiment of the present invention, it falls within the scope of protection of this application.

[0130] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0131] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon-based substrate, comprising a front side and a back side opposite to each other; the back side comprises a first region, a second region, and an isolation region between the first region and the second region; Semiconductor structures located in the first region and the second region respectively; the semiconductor structure in the first region is of opposite type to the semiconductor structure in the second region; The semiconductor structure of the first region includes at least one first semiconductor structure and at least one second semiconductor structure located on a side of the first semiconductor structure away from the silicon-based substrate; the first semiconductor structure includes a first tunneling oxide layer and a first polysilicon layer arranged in a stacked manner; the second semiconductor structure includes a second tunneling oxide layer and a second polysilicon layer arranged in a stacked manner; the second tunneling oxide layer is a porous structure; the porous structure includes a plurality of holes arranged at intervals; a first electrode in contact with the semiconductor structure of the first region; The second electrode is in contact with the semiconductor structure in the second region.

2. The solar cell according to claim 1, characterized in that The thickness T1 of at least one of the first tunneling oxide layer and the second tunneling oxide layer has a value range of: 1 nm≤T1≤3 nm.

3. The solar cell according to claim 1, characterized in that The thickness T2 of at least one of the first polysilicon layer and the second polysilicon layer has a value range of 50 nm ≤ T2 ≤ 400 nm.

4. The solar cell according to claim 1, characterized in that The semiconductor structure of the first region further includes at least one third semiconductor structure; the third semiconductor structure includes a third tunneling oxide layer and a third polysilicon layer stacked; The third semiconductor structure is located on a side of the second semiconductor structure facing away from the silicon-based substrate, and / or the third semiconductor structure is located between two adjacent second semiconductor structures.

5. The solar cell according to claim 1, characterized in that: The semiconductor structure of the second region includes at least one fourth semiconductor structure; the fourth semiconductor structure includes a fourth tunneling oxide layer and a fourth polysilicon layer which are stacked.

6. The solar cell according to claim 5, characterized in that: The semiconductor structure in the second region further includes at least one fifth semiconductor structure located on a side of the fourth semiconductor structure away from the silicon-based substrate; The fifth semiconductor structure includes a fifth tunneling oxide layer and a fifth polysilicon layer which are stacked; the fifth tunneling oxide layer is the porous structure.

7. The solar cell according to claim 6, characterized in that: The semiconductor structure of the second region further includes at least one sixth semiconductor structure; the sixth semiconductor structure includes a sixth tunneling oxide layer and a sixth polysilicon layer stacked; The sixth semiconductor structure is located on a side of the fifth semiconductor structure facing away from the silicon-based substrate, and / or the sixth semiconductor structure is located between two adjacent fifth semiconductor structures.

8. The solar cell according to claim 1, characterized in that The size W of the hole has a value range of 0.05 μm ≤ W ≤ 5 μm.

9. The solar cell according to claim 1, characterized in that: In the porous structure, the distance L between two adjacent holes is in the range of 0.1 μm ≤ L ≤ 100 μm.

10. The solar cell according to claim 1, characterized in that: Also includes: The passivation layer and the anti-reflection layer are stacked and cover the semiconductor structure of the first region, the isolation region, the semiconductor structure of the second region and the front side.

11. A solar cell, characterized in that: include: A silicon-based substrate, comprising a front side and a back side opposite to each other; the back side comprises a first region, a second region, and an isolation region between the first region and the second region; Semiconductor structures located in the first region and the second region respectively; the semiconductor structure in the first region is of opposite type to the semiconductor structure in the second region; The semiconductor structure of the first region includes a first polysilicon layer; the semiconductor structure of the first region also includes at least one second tunneling oxide layer disposed in the first polysilicon layer; the second tunneling oxide layer is a porous structure; the porous structure includes a plurality of holes arranged at intervals; a first electrode in contact with the semiconductor structure of the first region; The second electrode is in contact with the semiconductor structure in the second region.

12. The solar cell according to claim 11, characterized in that: The semiconductor structure of the second region includes a fourth polysilicon layer; The semiconductor structure in the second region further includes at least one fifth tunneling oxide layer disposed in the fourth polysilicon layer; the fifth tunneling oxide layer is the porous structure.

13. A method for preparing a solar cell, characterized in that: include: Providing a silicon-based substrate; the silicon-based substrate comprises a front side and a back side opposite to each other; the back side comprises a first region, a second region, and an isolation region between the first region and the second region; Semiconductor structures are formed in the first region and the second region respectively; the semiconductor structure in the first region is of opposite type to the semiconductor structure in the second region; the semiconductor structure in the first region includes at least one first semiconductor structure and at least one second semiconductor structure located on a side of the first semiconductor structure away from the silicon-based substrate; the first semiconductor structure includes a first tunneling oxide layer and a first polysilicon layer arranged in a stacked manner; the second semiconductor structure includes a second tunneling oxide layer and a second polysilicon layer arranged in a stacked manner; the second tunneling oxide layer is a porous structure; the porous structure includes a plurality of holes arranged at intervals; A first electrode in contact with the semiconductor structure in the first region and a second electrode in contact with the semiconductor structure in the second region are formed.

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