Display panel

Abstract

The display panel of the present invention may include: a base layer; a pixel defining film disposed on the base layer and having a light emitting opening; a partition wall disposed on the pixel defining film and having a partition wall opening portion overlapping the light emitting opening portion and a groove overlapping the pixel defining film; and a light-emitting element including an anode, a light-emitting pattern, and a cathode in contact with the partition wall, the light-emitting element being disposed in the light-emitting opening and the partition wall opening.

Description

Technical Field

[0001] The present invention relates to a display panel, and more particularly, to a display panel with improved display quality. Background Art

[0002] Display devices such as televisions, monitors, smartphones, and tablets that provide images to users include display panels that display images. As display panels, various display panels are being developed, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0003] An organic light emitting display panel may include an anode, a cathode and a light emitting pattern. The light emitting pattern may be separated for each light emitting area, and the cathode provides a common voltage for each light emitting area. Summary of the invention

[0004] In a display panel that forms a light-emitting element without using a metal mask, an object of the present invention is to provide a display panel with improved display quality and a method for manufacturing the same.

[0005] It can be that the display panel according to an embodiment of the present invention includes: a base layer; a pixel defining film, which is arranged on the base layer and has a light-emitting opening portion; a partition wall, which is arranged on the pixel defining film and has a partition wall opening portion overlapping with the light-emitting opening portion and a groove overlapping with the pixel defining film; and a light-emitting element, including an anode, a light-emitting pattern and a cathode in contact with the partition wall, and is arranged in the light-emitting opening portion and the partition wall opening portion.

[0006] The groove may be recessed from the upper surface of the partition wall in the thickness direction of the base layer.

[0007] The partition wall may include: a first portion disposed on the pixel defining film; a second portion extending from the first portion along a thickness direction of the base layer; and a third portion extending from the second portion toward a center of the partition wall opening.

[0008] It may be that the third portion protruding from the second portion includes an end portion.

[0009] The partition wall opening may include a first region defined by the third portion of the partition wall and a second region defined by the second portion of the partition wall, and a width of the first region in one direction is smaller than a width of the second region in the one direction.

[0010] A height from a lower surface of the first portion of the partition wall adjacent to the second portion to a lower surface of the third portion may be 0.5 μm to 1 μm.

[0011] Alternatively, the display panel further includes a lower encapsulation inorganic pattern covering the light emitting element, wherein the lower encapsulation inorganic pattern fills the partition wall opening.

[0012] Alternatively, the display panel further includes: an encapsulation organic film disposed on the lower encapsulation inorganic pattern, wherein the encapsulation organic film fills the groove.

[0013] The partition wall may include at least one of molybdenum (Mo), tungsten (W), and a molybdenum-tungsten (Mo—W) alloy.

[0014] The partition wall may include a first partition wall layer disposed on the pixel defining film and a second partition wall layer disposed on the first partition wall layer.

[0015] The first partition wall layer may include at least one of molybdenum (Mo), tungsten (W), and a molybdenum-tungsten (Mo—W) alloy.

[0016] The second partition wall layer may include at least one of titanium (Ti) and aluminum (Al).

[0017] The partition wall may have a thickness of 0.2 μm to 0.5 μm.

[0018] It may be that a display panel manufacturing method according to an embodiment of the present invention includes: a step of providing a preliminary display panel including a base layer, an anode arranged on the base layer, and a pixel defining film covering the anode; a step of forming an auxiliary layer overlapping with the anode on the preliminary display panel; a step of forming a preliminary partition wall on the pixel defining film and the auxiliary layer; a step of etching the preliminary partition wall and the auxiliary layer to form a partition wall opening in the partition wall; a step of etching the pixel defining film to form a light-emitting opening overlapping with the partition wall opening; and a step of forming a light-emitting element in the light-emitting opening and the partition wall opening.

[0019] The step of etching the preliminary partition wall and the auxiliary layer to form the partition wall opening in the partition wall may include: a step of etching the preliminary partition wall to form a first region of the partition wall opening; and a step of etching the auxiliary layer to form a second region of the partition wall opening.

[0020] The partition wall may include a groove overlapping the pixel defining film, and the groove may be recessed from an upper surface of the partition wall in a thickness direction of the base layer.

[0021] Alternatively, the display panel manufacturing method further includes: forming a lower encapsulation inorganic pattern covering the light emitting element, wherein the lower encapsulation inorganic pattern fills the partition wall opening.

[0022] Alternatively, the display panel manufacturing method further includes: forming an encapsulation organic film on the lower encapsulation inorganic pattern, wherein the encapsulation organic film fills the groove.

[0023] The step of forming the preliminary partition wall on the pixel defining film and the auxiliary layer may include: a step of evaporating at least one of molybdenum (Mo), tungsten (W) and molybdenum-tungsten alloy (Mo—W).

[0024] The step of forming the preliminary partition wall on the pixel defining film and the auxiliary layer includes: the step of evaporating a first preliminary partition wall layer on the pixel defining film and the auxiliary layer; and the step of evaporating a second preliminary partition wall layer on the first preliminary partition wall layer.

[0025] As described above, since the partition wall has a shape defining a groove, the partition wall can have a large height even when it includes molybdenum (Mo), tungsten (W) or a molybdenum-tungsten (Mo-W) alloy material. That is, the display panel of the present invention can include a partition wall having a large height while having a large adhesion to the cathode and the lower package inorganic pattern and a small contact resistance with the cathode. As a result, pixel defects (dark spots, pixel shrinkage, etc.) of the display panel can be reduced or removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a is a perspective view of a display device according to an embodiment of the present invention.

[0027] Figure 1b is an exploded perspective view of a display device according to an embodiment of the present invention.

[0028] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention.

[0029] Figure 3is a plan view of a display panel according to an embodiment of the present invention.

[0030] Figure 4 FIG. 1 is a plan view showing an enlarged portion of a display area of ​​a display panel according to an embodiment of the present invention.

[0031] Figure 5 is along Figure 3 A cross-sectional view of the display panel taken along line II′.

[0032] Figure 6 is along Figure 4 A cross-sectional view taken along line II-II′.

[0033] Figures 7a to 7l is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0034] Figure 8 is along Figure 3 A cross-sectional view taken along line II′.

[0035] Fig. 9 is along Figure 3 A cross-sectional view taken along line II′.

[0036] (Explanation of Reference Numerals)

[0037] DP: Display Panel PDL: Pixel Definition Layer

[0038] PW: Partition wall OP-P: Partition wall opening

[0039] GV: Tank AE: Anode

[0040] EP: luminous pattern CE: cathode

[0041] ED: Light-emitting element LIL: Lower package inorganic pattern

[0042] OL: Encapsulated organic film DETAILED DESCRIPTION

[0043] In this specification, when a certain constituent element (or region, layer, part, etc.) is mentioned as being "on" another constituent element, "connected to" or "combined to" another constituent element, it means that it can be directly configured / connected / combined on the other constituent element, or a third constituent element can be configured between them.

[0044] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. "And / or" includes all combinations that can be defined by the relevant components.

[0045] The terms "first", "second" and the like may be used to describe a variety of constituent elements, but the above constituent elements are not limited by the above terms. The above terms are only used for the purpose of distinguishing one constituent element from another constituent element. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. As long as it is not clearly indicated as different in the context, a singular expression includes a plural expression.

[0046] In addition, terms such as “below”, “lower side”, “above”, and “upper side” are used to explain the relationship between components shown in the drawings. The above terms are relative concepts and are explained based on the directions shown in the drawings.

[0047] The terms "including" or "having" should be understood as being used to specify the existence of the features, numbers, steps, tasks, constituent elements, parts or their combinations recorded in the specification, and do not preclude the existence or additional possibilities of one or more other features or numbers, steps, tasks, constituent elements, parts or their combinations.

[0048] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by persons skilled in the art to which the present invention belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having the same meanings as those in the context of the relevant technology, and should not be interpreted as overly idealized or overly formalized meanings unless explicitly defined herein.

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0050] Figure 1a is a perspective view of a display device DD according to an embodiment of the present invention, Figure 1b is an exploded perspective view of a display device DD according to an embodiment of the present invention.

[0051] In one embodiment, the display device DD may be a large electronic device such as a television, a monitor, or an outdoor billboard. In addition, the display device DD may be a small or medium-sized electronic device such as a personal computer, a notebook computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet, and a camera. However, it is exemplary and may also be used as other display devices as long as it does not exceed the concept of the present invention. Figure 1a as well as Figure 1b exemplarily shows that the display device DD is a smart phone.

[0052] Reference Figure 1a as well as Figure 1bThe display device DD can display an image IM toward a third direction DR3 in a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The image IM may include not only a dynamic image but also a still image. Figure 1a , a clock window and an icon are shown as an example of the image IM. The display surface FS displaying the image IM may correspond to the front surface of the display device DD.

[0053] In this embodiment, the front (or top) and rear (or bottom) of each component are defined based on the direction of displaying the image IM. It can be that the front and rear are opposite to each other in the third direction DR3, and the normal direction of each of the front and rear is parallel to the third direction DR3. On the other hand, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and can be converted to other directions. In this specification, "on a plane" can mean when observed in the third direction DR3.

[0054] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be combined with each other to form the appearance of the display device DD.

[0055] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0056] The frame area BZA may be an area with a relatively low light transmittance compared to the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and surround the transmission area TA. However, it is shown as an example, and the frame area BZA of the window WP may be omitted. The window WP may include at least any one of the functional layers of the anti-fingerprint layer, the hard coating layer, and the anti-reflection layer, and is not limited to any one embodiment.

[0057] The display module DM may be disposed below the window WP. The display module DM may be a structure that substantially generates an image IM. The image IM generated by the display module DM is displayed on the display surface IS of the display module DM, and the user can recognize it from the outside through the transmission area TA.

[0058] The display surface IS of the display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated according to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA is an area covered by the frame area BZA and may not be recognizable from the outside.

[0059] The housing HAU may be combined with the window WP. The housing HAU may be combined with the window WP to provide a predetermined internal space. The display module DM may be accommodated in the internal space.

[0060] The housing HAU may include a relatively high rigidity material. For example, the housing HAU may include glass, plastic, or metal, or include a plurality of frames and / or plates formed of a combination thereof. The housing HAU may stably protect the display device DD contained in the internal space from external impact.

[0061] Figure 2 is a cross-sectional view of a display module DM according to an embodiment of the present invention.

[0062] Reference Figure 2 , the display module DM may include a display panel DP and an input sensor INS. Although not shown separately, the display device DD according to an embodiment of the present invention (see Figure 1a ) may also include a protective component arranged under the display panel DP or an anti-reflection component and / or a window component arranged on the input sensor INS.

[0063] The display panel DP may be a light-emitting display panel. However, this is exemplary and is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0064] The display panel DP may include a base layer BL, a circuit element layer DP-CL configured on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be directly configured on the thin film encapsulation layer TFE. In this specification, "A configuration is directly configured on B configuration" means that no adhesive layer is configured between the A configuration and the B configuration.

[0065] The base layer BL may include at least one plastic film. As a flexible substrate, the base layer BL may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1bThe display area DA and the non-display area NDA described in the accompanying drawings may be similarly defined in the base layer BL.

[0066] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel driving circuits, and the like.

[0067] The display element layer DP-OLED may include partition walls and a light emitting element. The light emitting element may include an anode, an intermediate layer, and a cathode.

[0068] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be configured to improve optical efficiency, and some of which may be configured to protect the organic light emitting diode.

[0069] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single-layer or multi-layer conductive layer. In addition, the input sensor INS may include a single-layer or multi-layer insulating layer. The input sensor INS may sense the external input in a capacitive manner. However, it is exemplary and not limited thereto. For example, in one embodiment, the input sensor INS may also sense the external input in an electromagnetic induction manner or a pressure sensing manner. On the other hand, in another embodiment of the present invention, the input sensor INS may be omitted.

[0070] Figure 3 is a plan view of a display panel DP according to an embodiment of the present invention.

[0071] Reference Figure 3 In the display panel DP, a display area DA and a non-display area NDA around the display area DA may be defined. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a drive circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be divided by whether the pixels PX are configured or not. The pixels PX may be configured in the display area DA. The drive circuit GDC and the pad portion PLD may be configured in the non-display area NDA.

[0072] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0073] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding pixel in the pixels PX, and each of the data lines DL may be connected to a corresponding pixel in the pixels PX. The power lines PL may be electrically connected to the pixels PX. The control signal lines CSL may be connected to the drive circuit GDC to provide a control signal to the drive circuit GDC.

[0074] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate line GL. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0075] The pad portion PLD may be a portion for connecting a flexible circuit substrate. The pad portion PLD may include a pixel pad D-PD, and the pixel pad D-PD may be a pad for connecting the flexible circuit substrate to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line in the signal line SGL. The pixel pad D-PD may be connected to a corresponding pixel PX through the signal line SGL. In addition, any one of the pixel pads D-PD may be connected to the drive circuit GDC.

[0076] In addition, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit substrate to the input sensor INS (see Figure 2 However, the input pad may be configured on the input sensor INS (refer to Figure 2 ), and connected to the pixel pad D-PD and a separate circuit substrate. Alternatively, the input sensor INS can be omitted (refer to Figure 2 ), and may not further include an input pad.

[0077] Figure 4 is an enlarged view of a display panel DP according to an embodiment of the present invention (refer to Figure 2 ) is a plan view of a portion of the display area DA. Figure 4 The display module DM (refer to Figure 1b ) display surface IS (refer to Figure 1b ) is a plane of the display module DM observed from above, and shows the arrangement of the light-emitting areas PXA-R, PXA-G, and PXA-B.

[0078] Reference Figure 4, the display area DA may include first to third light emitting areas PXA-R, PXA-G, PXA-B and peripheral areas NPXA surrounding the first to third light emitting areas PXA-R, PXA-G, PXA-B. The first to third light emitting areas PXA-R, PXA-G, PXA-B may correspond to areas where light provided by the light emitting element is emitted, respectively. The first to third light emitting areas PXA-R, PXA-G, PXA-B may be arranged according to the direction toward the display module DM (refer to Figure 2 ) is divided by the color of the light emitted from the outside.

[0079] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may respectively provide first to third color lights having different colors from each other. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the examples of the first to third color lights are not necessarily limited to the examples.

[0080] Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be defined as a region of the anode exposed through a light emitting opening described later. The peripheral region NPXA may set a boundary of the first to third light emitting regions PXA-R, PXA-G, and PXA-B and prevent color mixing between the first to third light emitting regions PXA-R, PXA-G, and PXA-B.

[0081] Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be provided in a plurality and have a predetermined arrangement form and are repeatedly arranged in the display area DA. For example, the first and third light emitting regions PXA-R and PXA-B may be arranged alternately along the first direction DR1 to form a 'first group'. The second light emitting region PXA-G may be arranged along the first direction DR1 to form a 'second group'. Each of the 'first group' and the 'second group' may be provided in a plurality, and the 'first group' and the 'second group' may be arranged alternately with each other along the second direction DR2.

[0082] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first and second directions DR1 and DR2.

[0083] on the other hand, Figure 4 The arrangement of the first to third light emitting regions PXA-R, PXA-G, and PXA-B is shown as an example, but is not limited thereto and can be arranged in various forms. Figure 4 As shown, the first to third light emitting regions PXA-R, PXA-G, PXA-B may have PENTILE (PENTILETM Alternatively, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may also have a stripe arrangement or a diamond arrangement. ) arrangement format.

[0084] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have various shapes on a plane, such as a polygon, a circle, or an ellipse. Figure 4 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a rhombus shape) on a plane and the second light emitting region PXA-G having an octagonal shape are exemplarily shown.

[0085] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the same shape as each other on a plane, or at least a portion thereof may have different shapes from each other. Figure 4 The first and third light emitting regions PXA-R and PXA-B having the same shape as each other on a plane and the second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-R and PXA-B are exemplarily shown.

[0086] At least a portion of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have different areas on a plane. In one embodiment, the area of ​​the first light emitting region PXA-R emitting red light may be larger than the area of ​​the second light emitting region PXA-G emitting green light and smaller than the area of ​​the third light emitting region PXA-B emitting blue light. However, the size relationship between the areas of the first to third light emitting regions PXA-R, PXA-G, and PXA-B according to the light emitting color is not limited thereto, and may be determined according to the display module DM (refer to Figure 2 ) design diversification. In addition, not limited to this, the first to third light-emitting regions PXA-R, PXA-G, PXA-B may also have the same area as each other on a plane.

[0087] On the other hand, the display module DM of the present invention (refer to Figure 2 The shapes, areas, and arrangements of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B can be determined according to the color of the light emitted or the display module DM (see Figure 2 ) are designed in different sizes and compositions, not limited to Figure 4 The embodiment shown.

[0088] Figure 5 is along Figure 3A cross-sectional view of the display panel DP taken along line II′. Figure 5 When, refer to Figure 2 The description will be given below, and the description of the same figure numerals will be omitted. Figure 5 The display area DA is shown in an enlarged manner (see Figure 4 ) within a light emitting area PXA, Figure 5 The light emitting area PXA can be Figure 4 Corresponding to any one of the first to third light emitting areas PXA-R, PXA-G, PXA-B.

[0089] Reference Figure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0090] The display panel DP may include a plurality of insulating layers and semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed by coating, evaporation, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and photolithography processes. In this manner, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0091] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first to fifth insulating layers 10, 20, 30, 40, 50, an electrode EE, and a plurality of connection electrodes CNE1, CNE2.

[0092] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0093] A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, it is not limited thereto, and the semiconductor pattern may also include amorphous silicon or metal oxide. Figure 5 Only a part of the semiconductor pattern is shown as an example, and in the plurality of light emitting regions PXA-R, PXA-G, PXA-B (refer to Figure 4) can also be configured with a semiconductor pattern. The semiconductor pattern can be arranged according to a specific rule across multiple light-emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern can have different electrical properties depending on whether it is doped or not. The semiconductor pattern may include a first region with a large doping concentration and a second region with a small doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a first region doped with a P-type dopant.

[0094] The conductivity of the first region is greater than that of the second region, and it substantially functions as an electrode or a signal line. The second region may substantially be equivalent to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be the active region of a transistor, another portion may be the source or drain of the transistor, and another portion may be a conductive region.

[0095] The source S, the active electrode A, and the drain D of the transistor TR1 may be formed from a semiconductor pattern. Figure 5 A portion of a signal transmission region SCL formed from a semiconductor pattern is shown in . Although not separately shown, the signal transmission region SCL may be connected to the drain D of the transistor TR1 on a plane.

[0096] The first to fifth insulating layers 10, 20, 30, 40, 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, 50 may be inorganic layers or organic layers.

[0097] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active electrode A, the drain electrode D, and the signal transmission region SCL of the transistor TR1 disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the electrode EE.

[0098] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 penetrating the first to third insulating layers 10, 20, and 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0099] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0100] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining layer PDL, and a partition wall PW.

[0101] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode). The light emitting element ED may be disposed in a light emitting opening OP-E and a partition wall opening OP-P described later.

[0102] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 by passing through the fifth insulating layer 50 to define the connection contact hole CNT-3. Therefore, the anode AE ​​may be electrically connected to the signal transmission region SCL through the first and second connection electrodes CNE1 and CNE2, and electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer or multi-layer structure. The anode AE ​​may include multiple layers including ITO and Ag. For example, the anode AE ​​may include a layer including ITO (or, a lower ITO layer), a layer including Ag (or, an Ag layer) disposed on the lower ITO layer, and a layer including ITO disposed on the Ag layer.

[0103] The sacrificial pattern SP may be disposed between the anode AE ​​and the pixel defining film PDL. The sacrificial pattern SP may define (or may have) a sacrificial opening OP-S exposing a portion of the upper surface of the anode AE. The sacrificial opening OP-S may overlap with the light emitting opening OP-E described later.

[0104] The pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light emitting opening portion OP-E may be defined (or may be present) in the pixel defining film PDL. The light emitting opening portion OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening portion OP-E.

[0105] In addition, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to this embodiment, the upper surface of the anode AE ​​may be separated from the pixel defining film PDL in a cross section via the sacrificial pattern SP, thereby protecting the anode AE ​​from damage during the formation process of the light emitting opening OP-E.

[0106] On a plane, the area of ​​the light-emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. That is, the inner side surface of the pixel defining film PDL defining the light-emitting opening OP-E may be closer to the center of the anode AE ​​than the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, not limited to this, the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S may also be substantially aligned with the inner side surface of the pixel defining film PDL defining the light-emitting opening OP-E. At this time, the light-emitting area PXA may also be regarded as the area of ​​the anode AE ​​exposed from the corresponding sacrificial opening OP-S.

[0107] The pixel definition layer PDL may include an inorganic insulating material. For example, it may include silicon nitride (SiN x or silicon nitride). The pixel defining layer PDL may be disposed between the anode AE ​​and the partition wall PW, and the blocking anode AE ​​and the partition wall PW are electrically connected to each other.

[0108] The light-emitting pattern EP may be arranged on the anode AE. The light-emitting pattern EP may include a light-emitting layer including a light-emitting substance. The light-emitting pattern EP may also include a hole injection layer (HIL) and a hole transport layer (HTL) arranged between the anode AE ​​and the light-emitting layer, and may also include an electron transport layer (ETL) and an electron injection layer (EIL) arranged on the light-emitting layer. The light-emitting pattern EP may also be referred to as an 'organic layer' or an 'intermediate layer'.

[0109] The light-emitting pattern EP may be patterned by defining the end of the partition wall PW. The details are described later in the description of the display panel manufacturing method. The light-emitting pattern EP may be arranged inside the sacrificial opening portion OP-S and the light-emitting opening portion OP-E. However, it is shown as an example, and the light-emitting pattern EP may be arranged inside at least one of the sacrificial opening portion OP-S, the light-emitting opening portion OP-E and the partition wall opening portion OP-P. The light-emitting pattern EP may cover a portion of the upper surface of the pixel defining film PDL.

[0110] The cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be patterned by being defined at the end of the partition wall PW. At least a portion of the cathode CE may be disposed at the partition wall opening OP-P. Figure 5 2 and 3 exemplarily show that the cathode CE is arranged in the light emitting opening OP-E and the partition wall opening OP-P, but the present invention is not limited thereto. For example, the cathode CE may be arranged only in the partition wall opening OP-P.

[0111] The cathode CE may extend along the inner side of the partition wall PW, and an end of the cathode CE may contact the partition wall PW. Figure 5 FIG. 4 exemplarily shows that the cathode CE contacts the inner side surface of the partition wall PW and the inner side surface of the pixel defining film PDL, but the present invention is not limited thereto. For example, the cathode CE may be formed to contact only the inner side surface of the partition wall PW.

[0112] The cathode CE may be conductive. The cathode CE may be formed of various conductive materials such as metal, transparent conductive oxide (TCO) or conductive polymer. For example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu) or a compound thereof.

[0113] The partition wall PW may be disposed on the pixel defining film PDL. The partition wall PW may include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (IndiumGallium Oxide), indium gallium zinc oxide (IGZO), or aluminum zinc oxide (Aluminum Zinc Oxide). In one embodiment, the partition wall PW may include at least one of molybdenum (Mo), tungsten (W), and a molybdenum-tungsten (Mo-W) alloy.

[0114] The partition wall PW including the conductive material may receive a driving voltage, and thus the cathode CE may be electrically connected to the partition wall PW to receive the driving voltage.

[0115] The partition wall PW may have an undercut shape in cross section. The partition wall PW may include a first portion P1, a second portion P2, and a third portion P3. The first portion P1 of the partition wall PW may be disposed on the pixel defining film PDL. The second portion P2 of the partition wall PW may extend from the first portion P1 along the thickness direction of the base layer BL (e.g., the third direction DR3). The third portion P3 of the partition wall PW may extend from the second portion P2 toward the center of the partition wall opening OP-P. The partition wall PW may include an end. For example, the third portion P3 of the partition wall PW may protrude toward the partition wall opening OP-P to form an end. That is, the third portion P3 protruding from the second portion P2 may be defined as an end (may include an end). That is, the inner side surface of the third portion P3 may be closer to the center of the anode AE ​​than the inner side surface of the second portion P2.

[0116] The partition wall PW may have (may define) a partition wall opening OP-P and a groove GV. The partition wall opening OP-P may overlap with the light emitting opening OP-E and may expose at least a portion of the anode AE. The groove GV may be a shape that is concave from the upper surface U_PW of the partition wall PW in the thickness direction of the base layer BL (for example, the opposite direction of the third direction DR3), and the groove GV may overlap with the pixel defining film PDL on a plane.

[0117] The partition wall opening OP-P may include a first area A1 defined by the third portion P3 of the partition wall PW and a second area A2 defined by the second portion P2 of the partition wall PW. The width of the first area A1 in one direction (e.g., the first direction DR1 or the second direction DR2) may be smaller than the width of the second area A2 in one direction (e.g., the first direction DR1 or the second direction DR2).

[0118] A height DD1 from the bottom B_P1 of the first portion P1 adjacent to the second portion P2 of the partition wall PW to the bottom B_P3 of the third portion P3 may be 0.5 μm to 1 μm. In one embodiment, a height DD1 from the bottom B_P1 of the first portion P1 of the partition wall PW to the bottom B_P3 of the third portion P3 may be 0.6 μm. In addition, a thickness T1 of the partition wall PW may be 0.2 μm to 0.5 μm.

[0119] exist Figure 5 FIG. 4 exemplarily shows that the inner side of the partition wall PW is perpendicular to the upper surface of the pixel defining film PDL, but the present invention is not limited thereto. For example, the partition wall PW may also have a tapered shape or a reverse tapered shape.

[0120] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0121] The lower package inorganic pattern LIL may correspond to (or overlap) the light emitting opening OP-E. The lower package inorganic pattern LIL may be configured on the light emitting element ED to cover the light emitting element ED. A portion of the lower package inorganic pattern LIL may be formed in the partition wall opening OP-P, and another portion of the lower package inorganic pattern LIL may be formed on the partition wall PW. For example, a portion of the lower package inorganic pattern LIL may fill the partition wall opening OP-P, and another portion of the lower package inorganic pattern LIL may be formed on the partition wall PW, separated from the partition wall PW.

[0122] The encapsulation organic film OL may be disposed on the lower encapsulation inorganic pattern LIL. The encapsulation organic film OL may cover the lower encapsulation inorganic pattern LIL and provide a flat upper surface. The encapsulation organic film OL may fill the groove GV of the partition wall PW. The upper encapsulation inorganic film UIL may be disposed on the encapsulation organic film OL.

[0123] The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL may protect the display element layer DP-OLED from foreign matter such as dust particles.

[0124] Molybdenum (Mo), tungsten (W) or molybdenum-tungsten (Mo-W) alloy has the characteristics of high adhesion and low contact resistance. However, molybdenum (Mo), tungsten (W) or molybdenum-tungsten (Mo-W) alloy needs to be made into a small thickness according to the large stress characteristics. However, according to the present invention, since the partition wall PW has a shape defining a groove GV, even in the case of a molybdenum (Mo), tungsten (W) or molybdenum-tungsten (Mo-W) alloy material, the partition wall PW can also have a large height DD1 (the height from the bottom B_P1 of the first part P1 to the bottom B_P3 of the third part P3). That is, the display panel DP of the present invention can include a partition wall PW having a large height DD1 while having a large adhesion to the cathode CE and the lower encapsulation inorganic pattern LIL and a small contact resistance with the cathode CE. As a result, pixel defects (dark spots, pixel shrinkage, etc.) of the display panel can be reduced or removed.

[0125] Figure 6 is along Figure 4 A cross-sectional view taken along line II-II′. Figure 6 A first light emitting region PXA-R, a second light emitting region PXA-G, and a third light emitting region PXA-B are shown in an enlarged manner. Figure 5 The description of a light emitting region PXA can be applied to Figure 6 Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B. Figure 6 When Figure 5 The same / similar configurations as those described in the description are denoted by the same / similar reference numerals, and repeated descriptions are omitted.

[0126] Reference Figure 6 The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2, ED3, sacrificial patterns SP1, SP2, SP3, a pixel defining film PDL, and a partition wall PW.

[0127] The light emitting elements ED1, ED2, ED3 may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 that emit different colors, respectively. The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be provided in plural.

[0128] The first light emitting element ED1 may include a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1. The second light emitting element ED2 may include a second anode AE2, a second light emitting pattern EP2, and a second cathode CE2. The third light emitting element ED3 may include a third anode AE3, a third light emitting pattern EP3, and a third cathode CE3. The first to third anodes AE1, AE2, and AE3 may be provided in a plurality of patterns. In one embodiment, the first light emitting pattern EP1 may provide red light, the second light emitting pattern EP2 may provide green light, and the third light emitting pattern EP3 may provide blue light.

[0129] The pixel defining film PDL may define first to third light emitting openings OP1-E, OP2-E, and OP3-E. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3.

[0130] In one embodiment of the present invention, the first light emitting region PXA-R may be defined as a region of the upper surface of the first anode AE1 exposed by the first light emitting opening OP1-E. The second light emitting region PXA-G may be defined as a region of the upper surface of the second anode AE2 exposed by the second light emitting opening OP2-E. The third light emitting region PXA-B may be defined as a region of the upper surface of the third anode AE3 exposed by the third light emitting opening OP3-E.

[0131] In one embodiment of the present invention, the sacrificial patterns SP1, SP2, SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1, SP2, SP3 may be disposed on the first to third anodes AE1, AE2, AE3, respectively. The first to third sacrificial openings OP1-S, OP2-S, OP3-S respectively overlapping the first to third light emitting openings OP1-E, OP2-E, OP3-E may be defined in the first to third sacrificial patterns SP1, SP2, SP3.

[0132] The first to third partition wall openings OP1-P, OP2-P, OP3-P and the groove GV may be defined in the partition wall PW. The first to third partition wall openings OP1-P, OP2-P, OP3-P may overlap with the first to third light-emitting openings OP1-E, OP2-E, OP3-E, respectively, and the groove GV may overlap with the pixel defining film PDL. The groove GV may be formed between the first to third partition wall openings OP1-P, OP2-P, OP3-P on a plane. For example, a portion of the groove GV may be formed on a plane between the first partition wall opening OP1-P and the second partition wall opening OP2-P, a portion of the groove GV may be formed on a plane between the second partition wall opening OP2-P and the third partition wall opening OP3-P, and a portion of the groove GV may be formed on a plane between the third partition wall opening OP3-P and the first partition wall opening OP1-P.

[0133] In one embodiment of the present invention, the first to third light emitting patterns EP1, EP2, EP3 and the first to third cathodes CE1, CE2, CE3 can be physically separated by the partition wall PW forming the end and formed in each light emitting opening OP1-E, OP2-E, OP3-E and the partition wall opening OP1-P, OP2-P, OP3-P. That is, the light emitting elements ED1, ED2, ED3 can be arranged in the partition wall opening OP1-P, OP2-P, OP3-P and the light emitting opening OP1-E, OP2-E, OP3-E. For example, the first light emitting element ED1 can be arranged in the first partition wall opening OP1-P and the first light emitting opening OP1-E, the second light emitting element ED2 can be arranged in the second partition wall opening OP2-P and the second light emitting opening OP2-E, and the third light emitting element ED3 can be arranged in the third partition wall opening OP3-P and the third light emitting opening OP3-E.

[0134] According to the present invention, a plurality of first light emission patterns EP1 can be patterned and evaporated in pixel units by end portions defined in the partition wall PW. That is, the first light emission patterns EP1 are collectively formed using an open mask, but can be easily divided in pixel units by the partition wall PW.

[0135] On the contrary, when a fine metal mask (FMM) is used to pattern the first light emitting pattern EP1, in order to support the fine metal mask, a supporting spacer protruding from the conductive partition wall needs to be provided. In addition, since the fine metal mask separates the partition wall and the height of the spacer from the substrate surface for patterning, the realization of high resolution may be limited. In addition, since the fine metal mask is in contact with the spacer, after the patterning process of the first light emitting pattern EP1, foreign matter may remain in the spacer, or the spacer may be damaged due to traces of the fine metal mask. As a result, a poor display panel may be formed.

[0136] According to this embodiment, the physical separation between the light emitting elements ED1, ED2, and ED3 can be easily achieved by including the partition wall PW. Thus, it is possible to prevent current leakage or driving errors between adjacent light emitting regions PXA-R, PXA-G, and PXA-B, and drive each light emitting element ED1, ED2, and ED3 independently.

[0137] In particular, it is possible to achieve the above by providing a display area DA (see Figure 1b ) is formed in contact with the inner part of the plurality of first light emitting patterns EP1 to reduce the defect rate and provide a display panel DP with improved process reliability. Even if a separate supporting spacer protruding from the partition wall PW is not provided, since it can also be patterned, the area of ​​the light emitting regions PXA-R, PXA-G, and PXA-B can be miniaturized, and thus a display panel DP that can easily achieve high resolution can be provided.

[0138] In addition, when manufacturing a large-area display panel DP, by omitting the large-area mask production, the process cost can be reduced, and the adverse effects that may occur in the large-area mask can be avoided, so that a display panel DP with improved process reliability can be provided. The description of the plurality of first light emitting patterns EP1 can also be applied to the plurality of second and third light emitting patterns EP2 and EP3.

[0139] The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0140] The lower encapsulation inorganic pattern LIL may include a first lower encapsulation inorganic pattern LIL1 covering the first light emitting element ED1, a second lower encapsulation inorganic pattern LIL2 covering the second light emitting element ED2, and a third lower encapsulation inorganic pattern LIL3 covering the third light emitting element ED3. The first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may overlap with the first to third light emitting opening portions OP1-E, OP2-E, OP3-E, respectively. The first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may be provided in the form of patterns spaced apart from each other.

[0141] A portion of the first lower encapsulation inorganic pattern LIL1 may fill the first partition wall opening OP1-P, and another portion of the first lower encapsulation inorganic pattern LIL1 may be formed on the partition wall PW, separated from the partition wall PW. A portion of the second lower encapsulation inorganic pattern LIL2 may fill the second partition wall opening OP2-P, and another portion of the second lower encapsulation inorganic pattern LIL2 may be formed on the partition wall PW, separated from the partition wall PW. A portion of the third lower encapsulation inorganic pattern LIL3 may fill the third partition wall opening OP3-P, and another portion of the third lower encapsulation inorganic pattern LIL3 may be formed on the partition wall PW, separated from the partition wall PW.

[0142] The encapsulation organic film OL may be disposed on the first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3. The encapsulation organic film OL may cover the first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3 and provide a flat upper surface. The encapsulation organic film OL may fill the groove GV of the partition wall PW.

[0143] Figures 7a to 7l FIG. 1 is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 7a to 7l 1 to Figure 6 The same or similar components will be described using the same or similar reference numerals, and duplicate description will be omitted.

[0144] According to an embodiment of the present invention, a display panel manufacturing method may include: a step of providing a preliminary display panel including a base layer, an anode arranged on the base layer, and a pixel defining film covering the anode; a step of forming an auxiliary layer overlapping with the anode on the preliminary display panel; a step of forming a preliminary partition wall on the pixel defining film and the auxiliary layer; a step of etching the preliminary partition wall and the auxiliary layer to form a partition wall opening in the partition wall; a step of etching the pixel defining film to form a light-emitting opening overlapping with the partition wall opening; and a step of forming a light-emitting element in the light-emitting opening and the partition wall opening.

[0145] Below, through Figures 7a to 7l , describing a method for forming two light emitting elements ED1, ED2 and lower encapsulation inorganic patterns LIL1, LIL2 covering the light emitting elements ED1, ED2, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL. Figures 7a to 7l The display panel DP formed can be Figure 6 Corresponding to a portion of the display panel DP.

[0146] Reference Figure 7a The display panel manufacturing method of the present invention may include: providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in this embodiment may include a base layer BL, a circuit element layer DP-CL, first and second anodes AE1, AE2, first and second preliminary sacrificial patterns SP1-I, SP2-I, a pixel defining layer PDL and a preliminary auxiliary layer SL-I.

[0147] The circuit element layer DP-CL can be formed by forming an insulating layer, a semiconductor layer and a conductive layer by coating, evaporation, etc., and selectively patterning the insulating layer, the semiconductor layer and the conductive layer by photolithography technology and etching process to form a common circuit element manufacturing process such as a semiconductor pattern, a conductive pattern and a signal line.

[0148] The first anode AE1 and the first preliminary sacrificial pattern SP1-I may be formed by the same patterning process, and the second anode AE2 and the second preliminary sacrificial pattern SP2-I may be formed by the same patterning process. The pixel defining film PDL may be disposed on the base layer BL. The pixel defining film PDL may completely cover the first and second anodes AE1, AE2 and the first and second preliminary sacrificial patterns SP1-I, SP2-I.

[0149] The preliminary auxiliary layer SL-I may be formed by evaporating on the pixel definition layer PDL. The preliminary auxiliary layer SL-I may be formed together with the preliminary partition wall PW-I (see Figure 7c For example, the preliminary auxiliary layer SL-I may be silicon (Si), silicon nitride (SiN x ) and polyimide (PI), etc. The material of the preliminary auxiliary layer SL-I is exemplary and is not limited to the example. The height of the evaporated preliminary auxiliary layer SL-I may determine the partition wall PW to be formed later (refer to Figure 7e ) height DD1 (refer to Figure 5 ).

[0150] The display panel manufacturing method of the present invention may include: forming a first photoresist layer PR1 on the preliminary auxiliary layer SL-I. The first photoresist layer PR1 may be formed by patterning the preliminary photoresist layer using a photomask after forming the preliminary photoresist layer on the preliminary auxiliary layer SL-I. Through the patterning process, an optical opening portion OP-PR may be formed in the first photoresist layer PR1. The optical opening portion OP-PR may not overlap with the first and second anodes AE1 and AE2 on the plane.

[0151] Afterwards, refer to Figure 7b The display panel manufacturing method of the present invention may include: forming an auxiliary layer SL overlapping the first and second anodes AE1 and AE2. The step of forming the auxiliary layer SL may use the first photoresist layer PR1 as a mask to dry etch the preliminary auxiliary layer SL-I (refer to Figure 7a ). A portion of the preliminary auxiliary layer SL-I that does not overlap with the first photoresist layer PR1 may be removed by etching, and a portion that overlaps with the first photoresist layer PR1 may become the auxiliary layer SL.

[0152] Afterwards, refer to Figure 7c The display panel manufacturing method of the present invention may include: removing the first photoresist layer PR1 (refer to Figure 7b ) Thereafter, a step of forming a preliminary partition wall PW-I on the pixel defining film PDL and the auxiliary layer SL.

[0153] The preliminary partition wall PW-I may be disposed on the pixel defining film PDL and the auxiliary layer SL. The preliminary partition wall PW-I may be formed by an evaporation process of a conductive material. The preliminary partition wall PW-I may include a metal, a transparent conductive oxide (Transparent Conductive Oxide, TCO) or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy. The transparent conductive oxide may include indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) or aluminum zinc oxide (Aluminum Zinc Oxide). In one embodiment of the present invention, the step of forming the preliminary partition wall PW-I may include: a step of evaporating at least one of molybdenum (Mo), tungsten (W), and a molybdenum-tungsten (Mo—W) alloy.

[0154] However, it is exemplary, and the preliminary partition wall PW-I formation process and the material of the preliminary partition wall PW-I are not limited to the example. For example, the step of forming the preliminary partition wall PW-I on the pixel defining film PDL and the auxiliary layer SL may include: the step of evaporating a first preliminary partition wall layer on the pixel defining film PDL and the auxiliary layer SL; and the step of forming a second preliminary partition wall layer on the first preliminary partition wall layer. In one embodiment, the first preliminary partition wall layer may include at least one of molybdenum (Mo), tungsten (W) and molybdenum-tungsten (Mo-W) alloy, and the second preliminary partition wall layer may include at least one of titanium (Ti) and aluminum (Al). The display panel manufactured by the process may be Figure 8 or Fig. 9 corresponding to the display panel (DPa or DPb).

[0155] Thereafter, the display panel manufacturing method of the present invention may include: a step of forming a second photoresist layer PR2 on the preliminary partition wall PW-I. The second photoresist layer PR2 may be formed by patterning the preliminary photoresist layer using a photomask after forming the preliminary photoresist layer on the preliminary partition wall PW-I. Through the patterning process, a first light opening portion OP-PR1 and a second light opening portion OP-PR2 may be formed in the second photoresist layer PR2. The first light opening portion OP-PR1 may overlap with the first anode AE1, and the second light opening portion OP-PR2 may overlap with the second anode AE2.

[0156] Afterwards, refer to Figure 7d as well as Figure 7e The display panel manufacturing method of the present invention may include: etching the preliminary partition wall PW-I (refer to Figure 7c ) and the auxiliary layer SL to form a partition wall opening OP-P in the partition wall PW (refer to Figure 5 ). The step of etching the preliminary partition wall PW-I and the auxiliary layer SL to form the partition wall opening OP-P in the partition wall PW may include: a step of etching the preliminary partition wall PW-I to form a first area A1 of the partition wall opening OP-P; and a step of etching the auxiliary layer SL to form a second area A2 of the partition wall opening OP-P. Figure 7d The steps of forming the first area A1 are described by Figure 7e The step of forming the second area A2 is described.

[0157] First, if Figure 7d As shown, the preliminary partition wall PW-I is etched to form a partition wall opening OP-P (see Figure 5), the second photoresist layer PR2 may be used as a mask to dry etch the preliminary partition wall PW-I. The portion of the preliminary partition wall PW-I that does not overlap with the second photoresist layer PR2 may be etched and removed, and the first region A1 may be formed in the portion that is removed by being etched. For example, the first region A1 corresponding to the first anode AE1 may be formed in the portion that is removed by overlapping with the first optical opening portion OP-PR1, and the first region A1 corresponding to the second anode AE2 may be formed in the portion that is removed by overlapping with the second optical opening portion OP-PR2. The partition wall PW may be formed from the preliminary partition wall PW-I that defines the first region A1.

[0158] Afterwards, if Figure 7e As shown, the etching auxiliary layer SL (refer to Figure 7d ) to form the second region A2 of the partition wall opening OP-P, after removing the second photoresist layer PR2 (refer to Figure 7d ), the auxiliary layer SL may be dry etched (dry etching) and the auxiliary layer SL may be removed. A second area A2 may be formed in the portion removed by etching. The width of the first area A1 in one direction may be smaller than the width of the second area A2 in one direction. The first area A1 and the second area A2 may define partition wall openings OP1-P and OP2-P. For example, the first area A1 and the second area A2 overlapping the first anode AE1 may define the first partition wall opening OP1-P, and the first area A1 and the second area A2 overlapping the second anode AE2 may define the second partition wall opening OP2-P.

[0159] The etching process for forming the second region A2 may be implemented in an environment where the etching selectivity ratio between the auxiliary layer SL and the partition wall PW is large. Specifically, since the etching rate of the auxiliary layer SL relative to the etching solution is greater than the etching rate of the partition wall PW, the auxiliary layer SL may be mainly etched.

[0160] Thus, the partition wall PW may have an undercut shape in cross section and may include an end portion. Figure 5 ) The protruding third portion P3 (refer to Figure 5 ) may be defined as an end portion (may include an end portion). That is, the inner side surface of the third portion P3 may be closer to the center of the anode (AE1 or AE2) than the inner side surface of the second portion P2.

[0161] In the portion where the second photoresist layer PR2 is removed, the partition wall PW may include a groove GV The groove GV may be recessed from the upper surface of the partition wall PW in the thickness direction of the base layer BL (eg, the opposite direction to the third direction DR3 ).

[0162] Afterwards, refer to Figure 7f The display panel manufacturing method of the present invention may include a step of etching a pixel definition film PDL to form light emitting openings OP1-E and OP2-E overlapping with partition wall openings OP1-P and OP2-P.

[0163] The step of etching the pixel defining film PDL may use the partition wall PW as a mask to dry etch the pixel defining film PDL. The portion of the pixel defining film PDL that does not overlap with the partition wall PW may be etched and removed. As a result, light-emitting openings OP1-E and OP2-E overlapping with the partition wall openings OP1-P and OP2-P may be formed in the pixel defining film PDL. The light-emitting openings OP1-E and OP2-E may include a first light-emitting opening OP1-E overlapping with the first partition wall opening OP1-P and a second light-emitting opening OP2-E overlapping with the second partition wall opening OP2-P. The etched pixel defining film PDL may overlap with the groove GV.

[0164] Thereafter, the display panel manufacturing method of the present invention may include: etching the first and second preliminary sacrificial patterns SP1-I and SP2-I (refer to Figure 7e ) to form sacrificial patterns SP1 and SP2 having sacrificial openings OP1-S and OP2-S overlapping with light-emitting openings OP1-E and OP2-E.

[0165] The step of etching the first and second preliminary sacrificial patterns SP1-I and SP2-I may use the partition wall PW as a mask to wet etch the first and second preliminary sacrificial patterns SP1-I and SP2-I. Portions of the first and second preliminary sacrificial patterns SP1-I and SP2-I that do not overlap with the partition wall PW may be etched and removed. As a result, sacrificial patterns SP1 and SP2 may be formed from the first and second preliminary sacrificial patterns SP1-I and SP2-I.

[0166] The sacrificial patterns SP1 and SP2 may include a first sacrificial pattern SP1 and a second sacrificial pattern SP2. A first sacrificial opening OP1-S overlapping the first light emitting opening OP1-E may be formed in the first sacrificial pattern SP1, and a second sacrificial opening OP2-S overlapping the second light emitting opening OP2-E may be formed in the second sacrificial pattern SP2.

[0167] The etching process of the sacrificial patterns SP1 and SP2 can be implemented in an environment where the etching selectivity ratio between the sacrificial patterns SP1 and SP2 and the anodes AE1 and AE2 is large, thereby preventing the anodes AE1 and AE2 from being etched together. That is, the sacrificial patterns SP1 and SP2 having a higher etching rate than the anodes AE1 and AE2 can be arranged between the pixel defining film PDL and the anodes AE1 and AE2, thereby preventing the anodes AE1 and AE2 from being etched together and damaged during the etching process.

[0168] Afterwards, refer to Figure 7g The display panel manufacturing method of the present invention may include: forming a light emitting element ED1 in the light emitting opening OP1-E and the partition wall opening OP1-P. The step of forming the first light emitting element ED1 may include: forming a first light emitting pattern EP1; and forming a first cathode CE1.

[0169] The step of forming the first light-emitting pattern EP1 may include an evaporation process of the light-emitting layer. For example, the step of forming the first light-emitting pattern EP1 may include: a step of thermally evaporating the light-emitting layer. The light-emitting layer may be separated by being formed at the end of the partition wall PW and evaporated inside the first and second partition wall openings OP1-P, OP2-P and on the partition wall PW. The light-emitting layer formed in the first partition wall opening OP1-P may form the first light-emitting pattern EP1, and the light-emitting layer formed inside the second partition wall opening OP2-P and on the partition wall PW may form the first dummy layer D1. That is, the first light-emitting pattern EP1 may be formed on the first anode AE1 to overlap with the first partition wall opening OP1-P, and the first light-emitting pattern EP1 may be formed to cover the first anode AE1 and the pixel defining film PDL.

[0170] The first dummy layer D1 formed together in the step of forming the first light emitting pattern EP1 may include an organic substance. For example, the first dummy layer D1 may include the same substance as the first light emitting pattern EP1. The first dummy layer D1 may be formed simultaneously with the first light emitting pattern EP1 through one process and may be separated from the first light emitting pattern EP1 by the undercut shape of the partition wall PW.

[0171] The step of forming the first cathode CE1 may include an evaporation process of the cathode layer. For example, the step of forming the first cathode CE1 may include: a step of sputtering the cathode layer. The cathode layer may be evaporated inside the first and second partition wall openings OP1-P, OP2-P and on the partition wall PW by separation of the ends formed in the partition wall PW. The cathode layer formed in the first partition wall opening OP1-P may form the first cathode CE1, and the cathode layer formed inside the second partition wall opening OP2-P and on the partition wall PW may form the second dummy layer D2. That is, the first cathode CE1 may be formed on the first light emitting pattern EP1 to overlap with the first partition wall opening OP1-P, and the first cathode CE1 may be formed to cover the first light emitting pattern EP1. In addition, the first cathode CE1 may be in contact with the inner side surface of the partition wall PW and extend along the inner side surface of the partition wall PW.

[0172] The second dummy layer D2 formed together with the step of forming the first cathode CE1 may include a conductive material. For example, the second dummy layer D2 may include the same material as the first cathode CE1. The second dummy layer D2 may be formed simultaneously with the first cathode CE1 through one process and separated from the first cathode CE1 by the undercut shape of the partition wall PW.

[0173] The first anode AE1, the first light emitting pattern EP1, and the first cathode CE1 may be sequentially stacked along the third direction DR3. The first anode AE1, the first light emitting pattern EP1, and the first cathode CE1 may form a first light emitting element ED1.

[0174] Afterwards, refer to Figure 7h as well as Figure 7i The display panel manufacturing method of the present invention may include: forming a lower encapsulation inorganic pattern LIL1 covering the light emitting element ED1. The step of forming the lower encapsulation inorganic pattern LIL1 may include: evaporating a first lower encapsulation inorganic layer LIL1-I; and removing a portion of the first lower encapsulation inorganic layer LIL1-I that does not overlap with the first light emitting element ED1. Figure 7h The steps of evaporating the first lower encapsulation inorganic layer LIL1-I are described by Figure 7i The step of removing a portion of the first lower encapsulation inorganic layer LIL1-I that does not overlap with the first light emitting element ED1 is described.

[0175] First, refer to Figure 7h , forming a first lower package inorganic pattern LIL1 (refer to Figure 7i) may include: a step of evaporating the first lower encapsulation inorganic layer LIL1-I. In one embodiment, the first lower encapsulation inorganic layer LIL1-I may be formed by a chemical vapor deposition (CVD, Chemical Vapor Deposition) process. The first lower encapsulation inorganic layer LIL1-I may be formed to cover the first cathode CE1 and the partition wall PW. A portion of the first lower encapsulation inorganic layer LIL1-I may fill the first partition wall opening OP1-P and the groove GV.

[0176] Thereafter, the display panel manufacturing method of the present invention may include: a step of forming a third photoresist layer PR3. In the step of forming the third photoresist layer PR3, the third photoresist layer PR3 may be formed by patterning the preliminary photoresist layer using a photomask after forming the preliminary photoresist layer. Through the patterning process, the third photoresist layer PR3 may be formed in a pattern corresponding to the first light-emitting element ED1.

[0177] Afterwards, refer to Figure 7i The step of forming the first lower encapsulation inorganic pattern LIL1 may include: removing the first lower encapsulation inorganic layer LIL1-I (refer to Figure 7h ) part of the steps.

[0178] In the step of removing a portion of the first lower package inorganic layer LIL1-I that does not overlap with the first light-emitting element ED1, the third photoresist layer PR3 may be used as a mask to dry etch the first lower package inorganic layer LIL1-I. The portion of the first lower package inorganic layer LIL1-I that does not overlap with the third photoresist layer PR3 may be removed, and the portion of the first lower package inorganic layer LIL1-I that is not etched and remains may form a first lower package inorganic pattern LIL1. The first lower package inorganic pattern LIL1 formed by etching may fill the first partition wall opening OP1-P and may not overlap with the groove GV.

[0179] Afterwards, refer to Figure 7j The display panel manufacturing method of the present invention may include: removing the dummy layers D1 and D2. The second dummy layer D2 in the dummy layers D1 and D2 may be removed by wet etching, and the first dummy layer D1 in the dummy layers D1 and D2 may be removed by a stripper. Figure 7i ) can be removed.

[0180] Afterwards, refer to Figure 7kThe display panel manufacturing method of the present invention may include: forming a second light emitting element ED2 and a second lower encapsulation inorganic pattern LIL2. The process of forming the second light emitting element ED2 and the second lower encapsulation inorganic pattern LIL2 may be the same as that of Figure 7g to Figure 7j The described processes of forming the first light emitting element ED1 and the first lower encapsulation inorganic pattern LIL1 are substantially the same.

[0181] For the sake of convenience, the display panel manufacturing method of the present invention may include: forming a third light emitting element ED3 (refer to Figure 6 ) and the third lower package inorganic pattern LIL3 (refer to Figure 6 The process of forming the third light emitting element ED3 and the third lower package inorganic pattern LIL3 can be the same as that of Figure 7g to Figure 7j The described processes of forming the first light emitting element ED1 and the first lower encapsulation inorganic pattern LIL1 are substantially the same.

[0182] Afterwards, refer to Figure 7l The display panel manufacturing method of the present invention may include: forming an encapsulation organic film OL on the first and second lower encapsulation inorganic patterns LIL1 and LIL2; and forming an upper encapsulation inorganic film UIL on the encapsulation organic film OL to complete the display panel DP.

[0183] The encapsulation organic film OL may be formed by coating an organic substance by inkjet method, but is not limited thereto. The encapsulation organic film OL provides a planarized upper surface. The encapsulation organic film OL may fill the groove GV of the partition wall PW.

[0184] Thereafter, the upper encapsulation inorganic film UIL may be formed by evaporating an inorganic substance, through which a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE may be formed.

[0185] Figure 8 is along Figure 3 A cross-sectional view taken along line II′. Figure 8 The cross-sectional view of Figure 5 In the cross-sectional view corresponding to FIG. Figure 8 When the Figure 7l The same / similar configurations as those described in the description are denoted by the same / similar reference numerals, and repeated descriptions are omitted.

[0186] Reference Figure 8The display panel DPa may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLEDa, and a thin film encapsulation layer TFE. The display element layer DP-OLEDa may include a light emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, and a partition wall PWa.

[0187] The partition wall PWa may be disposed on the pixel defining film PDL. The partition wall PWa may include a plurality of layers stacked in sequence. For example, the partition wall PWa may include a first partition wall layer L1 and a second partition wall layer L2. It may be that the first partition wall layer L1 is disposed on the pixel defining film PDL, and the second partition wall layer L2 is disposed on the first partition wall layer L1. The partition wall PWa includes the first and second partition wall layers L1 and L2 for example, and is not limited to the example. For example, the partition wall PWa may include more than three partition wall layers.

[0188] like Figure 8 As shown, the thickness of the first partition wall layer L1 may be the same as the thickness of the second partition wall layer L2, but is not limited thereto. For example, the thickness of the second partition wall layer L2 may be greater than the thickness of the first partition wall layer L1.

[0189] The partition wall PWa may include a conductive material. In one embodiment, the first partition wall layer L1 of the partition wall PWa may include at least one of molybdenum (Mo), tungsten (W), and a molybdenum-tungsten (Mo-W) alloy, and the second partition wall layer L2 of the partition wall PWa may include at least one of titanium (Ti) and aluminum (Al).

[0190] The partition wall PWa may have an undercut shape in cross section. The partition wall PWa may include a first portion P1a, a second portion P2a, and a third portion P3a. The first portion P1a, the second portion P2a, and the third portion P3a of the partition wall PWa may be Figure 5 The first part P1, the second part P2 and the third part P3 are substantially the same. The partition wall PWa may include an end. For example, the third part P3a of the partition wall PWa may protrude toward the partition wall opening OP-P to form an end. That is, the third part P3a protruding from the second part P2a may be defined as an end (may include an end). That is, the inner side surface of the third part P3a may be closer to the center of the anode AE ​​than the inner side surface of the second part P2a.

[0191] The partition wall PWa may have (may define) a partition wall opening OP-P and a groove GV. A height DD1a from the bottom B_P1a of the first portion P1a adjacent to the second portion P2a of the partition wall PWa to the bottom B_P3a of the third portion P3a may be 0.6 μm. In addition, the thickness of the partition wall PWa (the sum of T1a and T2) may be 0.2 μm to 0.5 μm. In one embodiment, the thickness T1a of the first partition wall layer L1a may be 0.2 μm, and the thickness T2 of the second partition wall layer L2 may be 0.25 μm.

[0192] Fig. 9 is along Figure 3 A cross-sectional view taken along line II′. Fig. 9 The cross-sectional view of Figure 5 In the cross-sectional view corresponding to FIG. Fig. 9 When the Figure 8 The same / similar configurations as those described in the description are denoted by the same / similar reference numerals, and repeated descriptions are omitted.

[0193] Reference Fig. 9 The display panel DPb may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLEDb and a thin film encapsulation layer TFE. The display element layer DP-OLEDb may include a light emitting element ED, a sacrificial pattern SP, a pixel defining film PDL and a partition wall PWb.

[0194] The partition wall PWb may be disposed on the pixel defining film PDL. The partition wall PWb may include a plurality of layers stacked in sequence. For example, the partition wall PWb may include a first partition wall layer L1a and a second partition wall layer L2a. Alternatively, the first partition wall layer L1a may be disposed on the pixel defining film PDL, and the second partition wall layer L2a may be disposed on the first partition wall layer L1a. Fig. 9 The partition wall PWb can be Figure 8 The partition wall PWa is substantially the same as Fig. 9 The second portion P2a of the partition wall PWb (refer to Figure 8 ) adjacent to the first part P1a (refer to Figure 8 ) below B_P1 to the third part P3a (refer to Figure 8 )'s lower side B_P3a's height DD1b may be 1 μm.

[0195] Reference Figure 8 as well as Fig. 9, molybdenum (Mo), tungsten (W) or molybdenum-tungsten (Mo-W) alloy has the characteristics of high adhesion and low contact resistance. However, molybdenum (Mo), tungsten (W) or molybdenum-tungsten (Mo-W) alloy needs to be made into a small thickness according to the large stress characteristics. However, according to the present invention, since the partition wall (PWa or PWb) has a shape defining a groove GV, even in the case of including molybdenum (Mo), tungsten (W) or molybdenum-tungsten (Mo-W) alloy material, the partition wall (PWa or PWb) can also have a large height (DD1a or DD1b). That is, the display panel (DPa or DPb) of the present invention can include a partition wall (PWa or PWb) having a large height (DD1a or DD1b) while having a large adhesion to the cathode CE and the lower encapsulation inorganic pattern LIL and a small contact resistance with the cathode CE.

[0196] In addition, as the partition wall (PWa or PWb) includes the second partition wall layer (L2 or L2a) having a small stress, the thickness of the first partition wall layer (L1 or L1a) including molybdenum (Mo), tungsten (W) or a molybdenum-tungsten (Mo-W) alloy can be minimized. As a result, the stress of the partition wall (PWa or PWb) can be reduced to have a larger height (DD1a or DD1b).

[0197] The above description is made with reference to the preferred embodiments of the present invention, but it is understood by those skilled in the art or those with general knowledge in the art that various modifications and changes can be made to the present invention without exceeding the scope of the concept and technical field of the present invention recorded in the attached claims. Therefore, the technical scope of the present invention is not limited by the contents recorded in the detailed description of the specification, but should be limited by the claims.

Claims

1. A display panel, wherein: include: basal layer; A pixel defining film is disposed on the base layer and has a light emitting opening; a partition wall disposed on the pixel defining film and having a partition wall opening portion overlapping the light emitting opening portion and a groove overlapping the pixel defining film; as well as The light emitting element includes an anode, a light emitting pattern, and a cathode in contact with the partition wall, and is disposed in the light emitting opening and the partition wall opening.

2. The display panel according to claim 1, wherein: The groove is recessed from the upper surface of the partition wall toward the thickness direction of the base layer.

3. The display panel according to claim 1, wherein: The partition wall comprises: The first part is configured on the pixel defining film; a second portion extending from the first portion in a thickness direction of the base layer; and The third portion extends from the second portion toward the center of the partition wall opening.

4. The display panel according to claim 3, wherein: The third portion protruding from the second portion includes an end.

5. The display panel according to claim 3, wherein: The partition wall opening includes a first area defined by the third portion of the partition wall and a second area defined by the second portion of the partition wall, A width of the first region in one direction is smaller than a width of the second region in the one direction.

6. The display panel according to claim 3, wherein: A height from a lower surface of the first portion of the partition wall adjacent to the second portion to a lower surface of the third portion is 0.5 μm to 1 μm.

7. The display panel according to claim 1, wherein: The display panel further includes: The lower package inorganic pattern covers the light emitting element, The lower package inorganic pattern fills the partition wall opening.

8. The display panel according to claim 7, wherein: The display panel further includes: The encapsulation organic film is arranged on the lower encapsulation inorganic pattern, The encapsulating organic film fills the groove.

9. The display panel according to claim 1, wherein: The partition wall includes at least one of molybdenum, tungsten, and a molybdenum-tungsten alloy.

10. The display panel according to claim 1, wherein: The partition wall includes a first partition wall layer disposed on the pixel defining film and a second partition wall layer disposed on the first partition wall layer.

11. The display panel according to claim 10, wherein: The first partition wall layer includes at least one of molybdenum, tungsten, and a molybdenum-tungsten alloy.

12. The display panel according to claim 10, wherein: The second partition wall layer includes at least one of titanium and aluminum.

13. The display panel according to claim 1, wherein: The thickness of the partition wall is 0.2 μm to 0.5 μm.

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