Partial die block

Abstract

Portions of the die blocks may facilitate a superblock without having unused die blocks. In this case, maximum utilization of the available physical capacity of the data storage device can be achieved. Therefore, the reserved space (OP) and the effective capacity of the data storage device can be improved, or the bare chip yield can be improved. Improving effective capacity by using previously unused physical blocks will improve performance and durability. The cost of each bare chip and each data storage device can be reduced by improving the yield. A partial die block is a solution.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of, and is hereby incorporated by reference for all purposes, U.S. non-provisional application No. 18 / 357,789, filed on July 24, 2023, entitled “PARTIAL DIEBLOCKS,” in the U.S. Patent and Trademark Office, which claims priority to U.S. Provisional Application No. 63 / 501,435, filed on May 11, 2023. Background Art Technical Field

[0003] Embodiments of the present disclosure are generally directed to utilizing traditionally unused die blocks.

[0004] Related technical description

[0005] In a solid state device (SSD) that includes a super die block (i.e., superblock), a superblock is formed from complete (i.e., full) die blocks. A superblock may contain a plane that has die blocks that are considered bad (i.e., bad blocks) within the plane of the superblock. The number of times a die block can contribute to a superblock is determined by the worst plane. The worst plane is the plane with the highest number of bad blocks.

[0006] Bad die blocks are not evenly distributed across planes. During programming, the die is busy for the same amount of time whether one plane or all planes are programmed. Therefore, the more planes that can be programmed in parallel, the more efficient the utilization of the die. The use of full die blocks improves performance. Full die blocks have physical blocks from each plane. In such cases, the number of die blocks that can be formed is limited by the worst plane. Therefore, there are some good blocks in the better planes (i.e., the planes with at least one bad die block). These good blocks remain unused. If the number of bad die blocks across the planes is not equal, the number of unused die blocks is even worse.

[0007] In the past, a two plane superblock could leave at least one bad die block across the planes. As the number of planes has increased, the inequality of bad die blocks across superblocks has also increased, resulting in performance differences.

[0008] Therefore, there is a need in the art to facilitate improved use of die blocks by partial die blocks. Summary of the invention

[0009] Partial die blocks can facilitate super blocks without having a single die block. In this case, maximum utilization of the available physical capacity of the data storage device can be achieved. Therefore, the over-provisioning (OP) and effective capacity of the data storage device can be increased or the die yield can be increased. Increasing the effective capacity by using previously unused physical blocks will improve performance and durability. Improved yield will reduce the cost of each die and each data storage device. Partial die blocks are the solution.

[0010] In one embodiment, a data storage device includes: a memory device having multiple planes and multiple dies; and a controller coupled to the memory device, wherein the controller is configured to: detect that one or more of the multiple planes have one or more bad blocks; and form one or more first super blocks using blocks from less than all of the multiple planes.

[0011] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: form one or more first super blocks including full die blocks; and form one or more second super blocks including a mixture of full die blocks and partial die blocks.

[0012] In another embodiment, a data storage device includes: an apparatus for storing data; and a controller coupled to the apparatus for storing data, wherein the controller is configured to: set a super block size for a partitioned name space (ZNS) environment of the apparatus for storing data; and form one or more first super blocks including a mixture of full die blocks and partial die blocks, wherein the one or more first super blocks include at least two adjacent full die blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Thus, the above-mentioned features of the present disclosure may be understood in detail by reference to the embodiments, and more particularly the present disclosure briefly summarized above will be described, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0014] Figure 1 is a schematic block diagram illustrating a storage system according to certain embodiments, in which a data storage device can be used as a storage device for a host device.

[0015] Figure 2 An exemplary full die block with unused good die blocks is illustrated in accordance with certain embodiments.

[0016] Figure 3Exemplary combinations of full die blocks and partial die blocks are illustrated according to certain embodiments.

[0017] Figure 4 An exemplary SSD with a regular and flexible planar support is illustrated in accordance with certain embodiments.

[0018] Figure 5 An exemplary Zoned Namespace (ZNS) SSD with a fixed superblock size according to certain embodiments is illustrated.

[0019] Figure 6 is a flow chart illustrating a method for identifying conventional SSDs and ZNS SSDs for utilization of partial die blocks, according to certain embodiments.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0021] Hereinafter, reference is made to the embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the embodiments specifically described. On the contrary, it is conceivable that any combination of the following features and elements is used to implement and practice the present disclosure, regardless of whether it is related to different embodiments. In addition, although the embodiments of the present disclosure can achieve advantages that are superior to other possible solutions and / or superior to the prior art, whether a specific advantage is achieved by a given embodiment does not limit the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative and are not considered as elements or limitations of the appended claims, unless explicitly stated in the claims. Similarly, reference to "the present disclosure" should not be understood as a generalization of any inventive subject matter disclosed herein and should not be considered as elements or limitations of the appended claims, unless explicitly stated in the claims.

[0022] Partial die blocks can facilitate super blocks without having a single die block. In this case, maximum utilization of the available physical capacity of the data storage device can be achieved. Therefore, the over-provisioning (OP) and effective capacity of the data storage device can be increased or the die yield can be increased. Increasing the effective capacity by using previously unused physical blocks will improve performance and durability. Improved yield will reduce the cost of each die and each data storage device. Partial die blocks are the solution.

[0023] Figure 1is a schematic block diagram illustrating a storage system 100 having a data storage device 106 that can be used as a storage device for a host device 104 according to certain embodiments. For example, the host device 104 can utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host dynamic random access memory (DRAM) 138. In some examples, the storage system 100 may include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 that are configured as a redundant array of inexpensive / independent disks (RAID) that are collectively used as mass storage devices for the host device 104.

[0024] Host device 104 may store data to and / or retrieve data from one or more storage devices, such as data storage device 106. Figure 1 As illustrated, host device 104 may communicate with data storage device 106 via interface 114. Host device 104 may include any of a wide range of devices, including a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" tablet computer, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or other device capable of sending data to or receiving data from a data storage device.

[0025] The host DRAM 138 may optionally include a host memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 that is allocated to the data storage device 106 for exclusive use by the controller 108 of the data storage device 106. For example, the controller 108 may store mapping data, buffering commands, logical to physical (L2P) tables, metadata, etc. in the HMB 150. In other words, the controller 108 may use the HMB 150 to store data that would normally be stored in the volatile memory 112, the buffer 116, an internal memory of the controller 108 such as a static random access memory (SRAM), etc. In examples where the data storage device 106 does not include a DRAM (i.e., the optional DRAM 118), the controller 108 may utilize the HMB 150 as the DRAM of the data storage device 106.

[0026] Data storage device 106 includes controller 108, NVM 110, power supply 111, volatile memory 112, interface 114, write buffer 116, and optional DRAM 118. In some examples, data storage device 106 may include additional Figure 1 Components not shown in the figure. For example, the data storage device 106 may include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and the printed circuit board includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical dimensions and connector configuration of the data storage device 106 may be made to conform to one or more standard form factors. Some example standard form factors include, but are not limited to, a 3.5-inch data storage device (e.g., an HDD or SSD), a 2.5-inch data storage device, a 1.8-inch data storage device, a peripheral component interconnect (PCI), a PCI extension (PCI-X), an express PCI (PCIe) (e.g., PCIe x1, PCIe x4, PCIe x8, PCIe x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage device 106 may be directly coupled (e.g., directly soldered or inserted into a connector) to a motherboard of the host device 104.

[0027] The interface 114 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, so that data can be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also enable the data storage device 106 to receive power from the host device 104. For example, as Figure 1 As illustrated, power supply 111 may receive power from host device 104 via interface 114 .

[0028] NVM 110 may include multiple memory devices or memory cells. NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of NVM 110 may receive data and a message from controller 108 indicating that the memory cell stores data. Similarly, the memory cell may receive a message from controller 108 indicating that the memory cell retrieves data. In some examples, each of the memory cells may be referred to as a die. In some examples, NVM 110 may include multiple dies (i.e., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0029] In some examples, each memory cell may include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0030] NVM 110 may include multiple flash memory devices or memory cells. NVM flash memory devices may include NAND or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into multiple dies, wherein each of the multiple dies includes multiple physical blocks or logical blocks that can be further divided into multiple pages. Each block in a plurality of blocks within a particular memory device may include multiple NVM cells. Word lines may be used to electrically connect rows of NVM cells to define pages in a plurality of pages. The corresponding cells in each of the plurality of pages may be electrically connected to the corresponding bit lines. In addition, the NVM flash memory device may be a 2D device or a 3D device and may be a single-level cell (SLC), a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). The controller 108 may write data to and read data from the NVM flash memory device at the page level, and erase data of the NVM flash memory device at the block level.

[0031] The power supply 111 may provide power to one or more components of the data storage device 106. When operating in standard mode, the power supply 111 may use power provided by an external device such as the host device 104 to provide power to one or more components. For example, the power supply 111 may use power from the host device 104 received via the interface 114 to provide power to one or more components. In some examples, the power supply 111 may include one or more power storage components that are configured to provide power to one or more components when operating in a shutdown mode (such as when power from an external device is stopped). In this way, the power supply 111 can be used as an on-board backup power source. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by one or more power storage components may vary as the cost and / or size (e.g., area / volume) of the one or more power storage components changes. In other words, as the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0032] Controller 108 may use volatile memory 112 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 until the cached information is written to NVM 110. Figure 1 As illustrated, volatile memory 112 may consume power received from power source 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Likewise, optional DRAM 118 may be used to store mapping data, buffered commands, logical to physical (L2P) tables, metadata, cached data, etc. in optional DRAM 118. In some examples, data storage device 106 does not include optional DRAM 118, such that data storage device 106 is DRAM-free. In other examples, data storage device 106 includes optional DRAM 118.

[0033] The controller 108 may manage one or more operations of the data storage device 106. For example, the controller 108 may manage reading data from the NVM 110 and / or writing data to the NVM. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 may initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 may determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in an internal memory or write buffer 116 before sending the data to the NVM 110.

[0034] The controller 108 may include an optional second volatile memory 120. The optional second volatile memory 120 may be similar to the volatile memory 112. For example, the optional second volatile memory 120 may be an SRAM. The controller 108 may allocate a portion of the optional second volatile memory to the host device 104 as a controller memory buffer (CMB) 122. The host device 104 may directly access the CMB 122. For example, the host device 104 may utilize the CMB 122 to store one or more submission queues that are typically maintained in the host device 104, rather than maintaining the one or more submission queues in the host device 104. In other words, the host device 104 may generate commands and store the generated commands with or without associated data in the CMB 122, wherein the controller 108 accesses the CMB 122 to retrieve the stored generated commands and / or associated data.

[0035] Figure 2 An exemplary full die block 200 with unused good die blocks according to certain embodiments is illustrated. Full die block 200 includes planes 0 to 3 from which full die blocks A to F can be made. Plane 0 is the worst plane in full die block 200 because plane 0 has the largest number of bad blocks (i.e., six bad blocks). Since plane 0 is the worst plane, plane 0 will determine how many die super blocks (super blocks A to F) can be formed.

[0036] Currently, superblocks are formed from whole die blocks. Die blocks are selected from one or more dies within the device. There may be a smaller number of missing dies, but each die provides erase blocks from each plane. Several good blocks remain unused. The number of whole die blocks is determined by the worst plane. If the number of bad blocks across planes is not equal, the number of unused blocks is worse. In four planes of memory, there may be more unused blocks. Figure 2The example shown shows six full die blocks, of which nine erase blocks remain unused. Therefore, the die can contribute only six super blocks. The die blocks marked as unused are still good blocks, but cannot be used because unused blocks are not recognized as super blocks that can be used in conventional SSDs.

[0037] It should be noted that, for clarity, in the full die block 200, all bad blocks and unused blocks are at the top of each plane. In practice, bad blocks and unused blocks may be physically randomly scattered throughout the plane or logically placed at the beginning. The full die block 200 can support a small number of missing die. Each die provides an erase block from each plane. Even if there are multiple full die blocks, several good blocks will remain unused.

[0038] Figure 3 An exemplary combination 300 of a full die block and a partial die block according to certain embodiments is illustrated. The combination 300 includes planes 0 to 3 that can make blocks A to J. Plane 3 is the best plane in the super block 300 because plane 3 has the least number of bad blocks (2 bad blocks). It should be noted that the number of bad blocks of the combination 300 is the same as that of the full die block 200. The combination 300 does not have unused blocks in any of the four planes. The number of partial die blocks is determined by the number of bad blocks in each plane. A partial die block with 1 missing plane is allowed so that all excess bad blocks can be used.

[0039] exist Figure 3 In the example of , there is a partial die block with erase blocks from three planes in it. A partial block with one missing plane is allowed so that all erase blocks can be used. Figure 3 The example of FIG. 1 shows three full die blocks and seven partial die blocks, where each partial die block has erase blocks from three planes therein. Thus, the die can contribute ten super blocks, rather than Figure 2 The distribution of bad blocks is similar to that shown in Figure 2 , but the number of partial die blocks is determined by the number of bad blocks in each plane that are more than the best plane. The best plane is plane 3 with two bad blocks. The excess bad blocks are four bad blocks for plane 0, one bad block for plane 1, and two bad blocks for plane 2. The total number of excess bad blocks equals seven.

[0040] Figure 4An exemplary SSD with conventional and flexible plane support according to certain embodiments is illustrated. Conventional SSD 410 is evenly distributed across the best possible plane size. For conventional SSD 410, uniform shaping of super blocks with n or n+1 full die blocks is achieved. When the sizes of super blocks are similar, uniform shaping means consistent performance. Uniform shaping makes it possible to use all available full die blocks. Multiple super blocks have six or seven full die blocks. The total number of planes in each super block is twenty-four or twenty-eight. The previous method is to make a super block formed by a similar number (n or n+1) of die blocks, where each die block is the same size (due to the presence of erase blocks in each plane). Once a single erase block fails, the failed block can be replaced by an unused block. However, if the failure occurs in the worst plane, the entire block will be unusable. The previous method causes inequality between the best plane and the worst plane.

[0041] In conventional SSD 410, as described above in the previous method, there are four consistent planes that contribute to the super block of the die block. For example, in conventional SSD 410, the predetermined number of planes that need to be contributed by each die block in the entire super block is four planes. Once a die block fails, the uniform contribution makes the total number of contributions unequal. Once a die block fails to contribute to the total number of planes required for the super block (four planes in this example), the die block will be considered a failure. Even if the die block may have fewer planes than the super block, the die block will still be considered a failure. Examples of plane ranges are only 24 and 28. In the case of using all planes to contribute in conventional SSD 410, because these planes are occupied and contributed, there is a lack of flexibility in the planes to be used. In contrast to SSD 420, all planes are not occupied but contribute to the super block.

[0042] With partial die blocks, a super block can be formed with a mixture of full die blocks and partial die blocks. It should be noted that if a parity die is present, the parity die needs to be a full die block. If a manifest exists for the enterprise product, the manifest should also be written to the full die block to simplify the firmware, and the manifest should be adjacent to the parity die. SSD 420 shows a range of super blocks with all full die blocks or a mixture, and the result is a range of planes of twenty-three to twenty-seven blocks.

[0043] In the flexible SSD 420, three plane contributions are accepted from the die block even if the total plane contribution is four planes. As seen in the flexible SSD 420, three plane support is accepted, which makes the total contribution amount less different. The total number of planes accepted can range from three planes to four planes, depending on what the die block can contribute. The contribution of three planes by the die block can be considered a partial die block. Even if the planes are not the total amount (four planes), the super block will still accept contributions from the three remaining planes. When three planes are accepted, the total contribution amount is more uniform because when the die block does not have four planes to contribute, the super block will still accept contributions from three planes. Compared with previous methods, different plane contributions ultimately make the total plane contributions across the die less unequal. Flexible use of multiple plane sizes for contribution makes more use of planes and improves performance.

[0044] Figure 5 An exemplary ZNS SSD 500 with a fixed Super Block size according to certain embodiments is illustrated. In the ZNS SSD 500 architecture, all Super Blocks have the same size. In addition, the logical size of these zones is fixed so that all logical data can fit into the Super Block. Figure 5 In the ZNS SSD 500, all super blocks in the ZNS SSD 500 have a total of 24 planes. A die block will contribute to a maximum of four planes until the super block reaches a total of 24 plane contributions. As long as the total planes contributed to the super block are 24, the plane contribution of each die block is random. In the ZNS SSD 500, a super block is formed by six full die blocks or three full die blocks and four partial die blocks. For larger super blocks, there can be eight partial die blocks (must be a multiple of four). Up to about three partial die blocks will be unused. At least two fully filled die blocks must be together (contiguous). At least two fully filled die blocks must be together (contiguous or adjacent), but can be placed anywhere within the die (at the beginning or in the middle). Since there are no two adjacent full die blocks for the optional list or optional parity die, the final entry is illegal.

[0045] As seen in ZNS SSD 500, there may be other limitations with some die block missing, which results in using three planes to facilitate or using partial die blocks to reach the required total number of facilitates (24 planes). Other limitations may include, but are not limited to, die blocks and parity in the architecture. The list of tables with what has been written to the superblock can later identify valid data during garbage collection (GC).

[0046] Figure 66 is a flow chart illustrating a method 600 for identifying conventional SSDs and ZNS SSDs for facilitating the use of partial die blocks according to certain embodiments. Partial die blocks may be implemented in conventional SSDs and ZNS SSDs. Determining which SSD needs to use a partial die block will be performed by, for example, Figure 1 The controller 108 or the like may be used to determine the controller.

[0047] The method 600 begins at block 602. At block 602, the controller determines that one or more planes have one or more bad die blocks. At block 604, the controller determines whether the device supports a Super Block with less than all planes in use. If the controller determines that the device cannot support a Super Block with less than all planes in use, the method 600 proceeds to block 606. At block 606, the controller forms each Super Block with blocks from each plane. If the controller determines that the device can support a Super Block with less than all planes in use, the method 600 proceeds to block 608. At block 608, the controller determines whether the SSD is ZNS or conventional.

[0048] If the controller determines that the SSD is ZNS, the method 600 proceeds to block 610. At block 610, the controller determines the size of the Super Block. At block 612, the controller determines the number of Super Blocks that can be made using all planes. At block 616, the controller determines the number of Super Blocks that can be made using less than all planes. At block 618, the controller creates the Super Block. At block 620, the controller determines if any Super Block does not have two adjacent whole die blocks. If the controller determines that the Super Block does not have two adjacent whole die blocks, the method proceeds to block 630.

[0049] If at block 608, the controller determines that the SSD is a conventional SSD, the method 600 proceeds to block 622. At block 622, the controller calculates the number of Super Blocks that may have blocks from each plane. At block 624, the controller forms a full Super Block. At block 626, the controller calculates the number of Super Blocks that may have blocks from less than all planes. At block 628, the controller forms the Super Block. At block 630, the controller removes the illegal Super Block from the list of available Super Blocks. At block 632, the controller begins using the Super Block.

[0050] The use of partial die blocks will replace the existing conventional approach and apply to all data types (host data and tables), thus making it possible to leverage different product types. If the drive is built, there is more available capacity, resulting in better performance.

[0051] In one embodiment, a data storage device includes: a memory device having a plurality of planes and a plurality of dies; and a controller coupled to the memory device, wherein the controller is configured to: detect that one or more of the plurality of planes have one or more bad blocks; and use blocks from less than all of the plurality of planes to form one or more first super blocks. The controller is further configured to use blocks from each of the plurality of planes to make one or more second super blocks. Wherein, less than all of the plurality of planes is equal to one plane less than all of the plurality of planes. The number of the plurality of planes is equal to two or more. The data storage device is a zoned namespace (ZNS) data storage device.

[0052] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: form one or more first super blocks including full die blocks; and form one or more second super blocks including a mixture of full die blocks and partial die blocks. At least one die is a parity die. Parity is set in the full die block. The controller is configured to write inventory data to the full die block. The full die block is adjacent to the block containing parity data. The total number of planes of the one or more first super blocks is an even number. The total number of planes of the one or more second super blocks is an odd number. The total number of planes of the one or more second super blocks is less than the total number of planes of the one or more first super blocks. The total number of planes of the one or more second super blocks is more than the total number of planes of the one or more first super blocks. The mixture of full die blocks and partial die blocks does not contain inventory data.

[0053] In another embodiment, a data storage device includes: a device for storing data; and a controller coupled to the device for storing data, wherein the controller is configured to: set a superblock size for a partitioned namespace (ZNS) environment of the device for storing data; and form one or more first superblocks including a mixture of full die blocks and partial die blocks, wherein the one or more first superblocks include at least two adjacent full die blocks. The controller is also configured to form one or more second superblocks including only full die blocks. The one or more first superblocks include a first number of die, wherein the one or more second superblocks include a second number of die, and wherein the second number of die is more than the first number of die. The number of planes in each of the one or more first superblocks is equal to the number of planes in each of the one or more second superblocks. At least two adjacent full die blocks include parity data and manifest data. The number of partial die blocks is a multiple of four. One or more first superblocks do not have parity data or manifest data. One or more first superblocks have parity data. One or more first superblocks have parity data and manifest data. One or more first superblocks have manifest data.

[0054] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A data storage device, comprising: a memory device having a plurality of planes and a plurality of dies; and a controller coupled to the memory device, wherein the controller is configured to: detecting that one or more planes of the plurality of planes have one or more bad blocks; as well as One or more first super blocks are formed using blocks from less than all of the plurality of planes.

2. The data storage device according to claim 1, wherein: The controller is further configured to make one or more second super blocks using blocks from each of the plurality of planes.

3. The data storage device according to claim 2, wherein: Less than all of the planes in the plurality of planes is equal to one plane less than all of the planes in the plurality of planes. The data storage device according to claim 1 , wherein the number of the plurality of planes is equal to two or more.

5. The data storage device according to claim 1, wherein: The data storage device is a zoned name space (ZNS) data storage device.

6. A data storage device, comprising: Memory devices; and a controller coupled to the memory device, wherein the controller is configured to: forming one or more first super blocks including full die blocks; as well as One or more second super blocks are formed that include a mixture of full die blocks and partial die blocks.

7. The data storage device according to claim 6, wherein: At least one of the die is a parity die.

8. The data storage device according to claim 7, wherein: Parity is set in full die blocks.

9. The data storage device according to claim 6, wherein: The controller is configured to write the inventory data to the full die block.

10. The data storage device according to claim 9, wherein: The full die block is adjacent to the block containing parity data.

11. The data storage device according to claim 6, wherein: The total number of planes used for the one or more first super blocks is an even number.

12. The data storage device according to claim 11, wherein: The total number of planes used for the one or more second super blocks is an odd number.

13. The data storage device according to claim 11, wherein: The total number of planes used for the one or more second super blocks is less than the total number of planes used for the one or more first super blocks.

14. The data storage device according to claim 11, wherein: The total number of planes used for the one or more second super blocks is greater than the total number of planes used for the one or more first super blocks.

15. The data storage device according to claim 6, wherein: The mixture of full die blocks and partial die blocks does not include manifest data.

16. A data storage device, the data storage device comprising: a device for storing data; and a controller coupled to the device for storing data, wherein the controller is configured to: Setting a superblock size for a zoned namespace (ZNS) environment of the device for storing data; and One or more first super blocks are formed including a mixture of full die blocks and partial die blocks, wherein the one or more first super blocks include at least two adjacent full die blocks.

17. The data storage device according to claim 16, wherein: The controller is also configured to form one or more second super blocks including only full die blocks.

18. The data storage device according to claim 17, wherein: The one or more first super blocks include a first number of dies, wherein the one or more second super blocks include a second number of dies, and wherein the second number of dies is greater than the first number of dies.

19. The data storage device according to claim 17, wherein: The number of planes in each of the one or more first super blocks is equal to the number of planes in each of the one or more second super blocks.

20. The data storage device of claim 16, wherein: The at least two adjacent full die blocks include parity data and manifest data.

21. The data storage device according to claim 16, wherein: The number of some die blocks is a multiple of four.

22. The data storage device according to claim 16, wherein: The one or more first super blocks do not have parity data or manifest data.

23. The data storage device according to claim 16, wherein: The one or more first super blocks have parity data.

24. The data storage device according to claim 16, wherein: The one or more first super blocks have parity data and manifest data.

25. The data storage device of claim 16, wherein: The one or more first super blocks have manifest data.

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