Memory, memory system, and operating method of memory

Abstract

The invention discloses a memory, a memory system and an operation method of the memory, and belongs to the technical field of memorizing.A second switch unit is turned on by turning off a first switch unit, and a first voltage is provided for a first node, so that the first voltage acts on a second end of a driving transistor through the second switch unit and a source line; the second end of the driving transistor is coupled with the control end, so that the voltage of the control end changes along with the voltage of the second end, and the first voltage is greater than the threshold voltage of the driving transistor, so that the driving transistor is switched on, and the driving transistor is triggered to assist the corresponding memory string in performing GIDL erasing.

Description

Memory, memory system, and memory operating method Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a memory, a storage system, and a memory operating method. Background Art

[0002] The memory includes a peripheral circuit and multiple memory blocks coupled to the peripheral circuit. A driving transistor is provided in the peripheral circuit of the memory. During the erase operation of the memory block, an erase voltage is provided to both ends of the memory string in the memory block through the driving transistor, so that the top select gate (TSG) and the bottom select gate (BSG) of the memory string generate gate-induced-drain-leakage (GIDL), thereby performing GIDL erasure on the memory string.

[0003] Summary of the Invention

[0004] Embodiments of the present application provide a memory, a memory system, and a memory operation method, which can control a driving transistor to assist a corresponding memory string in performing GIDL erasure.

[0005] In a first aspect, the present application provides a memory, comprising: a plurality of memory blocks, each of the memory blocks comprising a plurality of memory strings, each of the memory strings being connected to different bit lines and the same source line; and a peripheral circuit, the peripheral circuit comprising a plurality of drive transistors, a first switch unit connected to control terminals of the plurality of drive transistors, and a second switch unit connected to the source line, the first terminal of each drive transistor being connected to a different bit line and the second terminal being connected to the source line, the first switch unit and the second switch unit being both connected to a first node; wherein the peripheral circuit is configured to perform an erase operation on the memory block. To perform the erase operation, the peripheral circuit is configured to:

[0006] Turning off the first switch unit to float the control terminals of the plurality of driving transistors;

[0007] The second switch unit is turned on to provide a first voltage to the first node, where the first voltage is greater than a threshold voltage of the plurality of driving transistors.

[0008] In a possible implementation, the peripheral circuit is further configured as follows:

[0009] Before turning off the first switch unit, the first switch unit is turned on, the second switch unit is turned off, and a second voltage is provided to the first node, where the second voltage is lower than the first voltage.

[0010] In a possible implementation, the peripheral circuit is further configured as follows:

[0011] After the second voltage is provided to the first node, the first switch unit is turned off to discharge the voltage provided to the first node from the second voltage to a third voltage.

[0012] In a possible implementation, the peripheral circuit is further configured as follows:

[0013] Before providing the second voltage to the first node, a fourth voltage is provided to the first node, or a fifth voltage is provided to the first node first and then the fourth voltage is provided to the first node, the fifth voltage is lower than the fourth voltage, and the fourth voltage is lower than the second voltage.

[0014] In a possible implementation, the peripheral circuit is further configured as follows:

[0015] Before providing the first voltage to the first node, a sixth voltage is provided to the bit line, or a seventh voltage is provided to the bit line first and then the sixth voltage is provided to the bit line, the seventh voltage is lower than the sixth voltage, and the sixth voltage is lower than the first voltage.

[0016] In a possible implementation, the peripheral circuit is further configured as follows:

[0017] Before providing the first voltage to the first node, an eighth voltage is provided to the source line, or a ninth voltage is provided to the source line first and then the eighth voltage is provided to the source line, the ninth voltage is lower than the eighth voltage, and the eighth voltage is lower than the first voltage.

[0018] In a possible implementation, at least one of the first switch unit and the second switch unit includes a transistor.

[0019] In a possible implementation, at least one of the first switch unit and the second switch unit includes a transistor and a voltage converter, the voltage converter is coupled to a control terminal of the transistor, and the voltage converter is configured as follows:

[0020] A voltage is provided to the control terminal of the transistor to turn off or turn on the transistor.

[0021] In a second aspect, the present application provides a storage system, which includes a controller and a memory provided by the above-mentioned first aspect or any possible implementation of the first aspect, wherein the controller is coupled to the memory and is configured to control the memory.

[0022] In a possible implementation, the storage system further includes a host; the host is coupled to the controller, and the host is configured to send data to the memory or receive data from the memory through the controller.

[0023] In a third aspect, the present application provides a method for operating a memory, the memory comprising: a plurality of memory blocks, each memory block comprising a plurality of memory strings, each memory string being connected to different bit lines and the same source line, the different bit lines being connected to first terminals of different drive transistors, a first switch unit connected to a control terminal of the drive transistor and a second switch unit connected to the source line being both connected to a first node; the method comprising performing an erase operation on the memory block, the erase operation comprising:

[0024] Turning off the first switch unit to float the control terminal of the driving transistor;

[0025] The second switch unit is turned on to provide a first voltage to the first node, where the first voltage is greater than a threshold voltage of the driving transistor.

[0026] In a possible implementation, the erasing operation further includes:

[0027] Before turning off the first switch unit, the first switch unit is turned on, the second switch unit is turned off, and a second voltage is provided to the first node, where the second voltage is lower than the first voltage.

[0028] In a possible implementation, the erasing operation further includes:

[0029] After the second voltage is provided to the first node, the first switch unit is turned off to discharge the voltage provided to the first node from the second voltage to a third voltage.

[0030] In a possible implementation, the erasing operation further includes:

[0031] Before providing the second voltage to the first node, a fourth voltage is provided to the first node, or a fifth voltage is provided to the first node first and then the fourth voltage is provided to the first node, the fifth voltage is lower than the fourth voltage, and the fourth voltage is lower than the second voltage.

[0032] In a possible implementation, the erasing operation further includes:

[0033] Before providing the first voltage to the first node, a sixth voltage is provided to the bit line, or a seventh voltage is provided to the bit line first and then the sixth voltage is provided to the bit line, the seventh voltage is lower than the sixth voltage, and the sixth voltage is lower than the first voltage.

[0034] In a possible implementation, the erasing operation further includes:

[0035] Before providing the first voltage to the first node, an eighth voltage is provided to the source line, or a ninth voltage is provided to the source line first and then the eighth voltage is provided to the source line, the ninth voltage is lower than the eighth voltage, and the eighth voltage is lower than the first voltage.

[0036] In a possible implementation, at least one of the first switch unit and the second switch unit includes a transistor.

[0037] In a possible implementation, at least one of the first switch unit and the second switch unit includes a transistor and a voltage converter, and the erase operation further includes:

[0038] A voltage is provided to the control terminal of the transistor to turn off or turn on the transistor.

[0039] The technical solution provided by this application includes at least the following beneficial effects:

[0040] By turning off the first switch unit, the control end of the driving crystal is floated, so that the second end of the driving transistor is coupled to the control end. By turning on the second switch unit, a first voltage is provided to the first node, so that the first voltage acts on the second end of the driving transistor through the turned-on second switch unit and the source line, so that the voltage of the control end of the driving transistor changes with the voltage of the second end. Since the first voltage is greater than the threshold voltage of the driving transistor, when the voltage of the control end reaches the threshold voltage, the driving transistor is turned on to trigger the storage string coupled to the bit line connected to the driving transistor to perform GIDL erasure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a schematic diagram of a memory according to an exemplary embodiment;

[0042] FIG2 is a cross-sectional side view of a substring according to an exemplary embodiment;

[0043] FIG3 is a schematic structural diagram of a peripheral circuit according to an exemplary embodiment;

[0044] FIG4 is a schematic diagram of a partial structure of another peripheral circuit according to an exemplary embodiment;

[0045] FIG5 is a schematic diagram of a partial structure of another peripheral circuit according to an exemplary embodiment;

[0046] FIG6 is a circuit diagram showing a driving transistor according to an exemplary embodiment;

[0047] FIG7 is a flow chart showing a method for operating a memory according to an exemplary embodiment;

[0048] FIG8 is a diagram showing voltage waveforms of some devices during an erase operation according to an exemplary embodiment;

[0049] FIG9 is a schematic diagram of a storage system according to an exemplary embodiment;

[0050] FIG10 is a schematic diagram showing a memory card according to an exemplary embodiment;

[0051] FIG11 is a schematic diagram showing a solid state drive according to an exemplary embodiment. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0053] FIG1 is a schematic diagram of a memory according to an exemplary embodiment. As shown in FIG1 , the memory 100 includes a memory array 110 , a plurality of bit lines (BL) 120 , a plurality of word lines (WL) 130 , and a peripheral circuit 140 .

[0054] The memory array 110 includes a plurality of memory strings 111 , which are arranged in an array above a substrate (not shown), and each memory string 111 extends vertically above the substrate.

[0055] Each memory string 111 includes multiple memory cells 112. The multiple memory cells 112 in each memory string 111 are stacked vertically above the substrate of the memory array 110. Each memory cell 112 has the function of storing data. The stored data is determined by the number of electrons stored in the memory cell 112. The number of electrons stored in the memory cell 112 can determine the threshold voltage of the memory cell 112. Therefore, the threshold voltage of the memory cell 112 can indicate the stored data. The memory cell 112 is a floating gate field effect transistor or a charge trap field effect transistor. In some embodiments, the memory cell 112 can have two possible storage states. For example, the memory cell 112 can be a single level cell (SLC) that stores one bit of data. For example, the first storage state "0" of the SLC can correspond to a threshold voltage in a first voltage range, and the first storage state "1" of the SLC can correspond to a threshold voltage in a second voltage range. In other embodiments, the memory cell 112 can store at least two bits of data. For example, the memory cell 112 is a multi-level cell (MLC). The MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values.

[0056] Each memory string 111 further includes an upper select transistor 113 and a lower select transistor 114. The upper select transistors 113 in different memory strings 111 that are at the same or similar heights from the substrate support surface are coupled to the same drain select line (DSL) 150. The lower select transistors 114 in different memory strings 111 that are at the same or similar heights from the substrate support surface are coupled to the same source select line (SSL) 160. The upper select transistors 113 and the lower select transistors 114 are used to activate the selected memory string when erasing, programming, or deleting memory cells. The upper select transistor 113 is also called the top select gate (TSG), and the lower select transistor 114 is also called the bottom select gate (BSG). One end of the memory string 111 is coupled to the bit line 120, and the other end of the memory string 111 is coupled to the source line (SL) 170.

[0057] As shown in FIG1 , memory cells 112 in different memory strings 111 that are at the same or similar heights from the substrate support surface are located in the same layer. Multiple memory cells 112 in the same layer form a memory cell row 11a. That is, the memory array 110 includes multiple memory cell rows, and multiple word lines 130 are coupled to the multiple memory cell rows. All memory strings 111 in the memory array 110 that share the same set of word lines form a memory block 11b. Each memory string 111 in the same memory block 11b is coupled to the same source line 170. That is, the memory 100 includes multiple memory blocks 11b, each memory block 11b includes multiple memory strings 111, and each memory string 111 in the same memory block 11b is connected to different bit lines 120 and the same source line 170.

[0058] As the number of memory cell layers increases, it is necessary to form multiple stacked memory strings 111 through multiple etchings. For example, FIG2 shows a cross-sectional side view of a substring according to an exemplary embodiment. Referring to FIG2 , the memory string 111 can extend vertically through the memory cell stacking layer 220 above the doped semiconductor layer 210. The doped semiconductor layer 210 is coupled to the source line. In some embodiments, the doped semiconductor layer 210 is an N-type doped semiconductor layer, in which case the doped semiconductor layer 210 is an N-well in the substrate, and the substrate is an N-type substrate. In other embodiments, the doped semiconductor layer 210 is a P-type doped semiconductor layer, in which case the doped semiconductor layer 210 is a P-well in the substrate, and the substrate is a P-type substrate.

[0059] The memory cell stack 220 includes alternating gate conductive layers 230 and gate-to-gate dielectric layers 240. The number of pairs of gate conductive layers 230 and gate-to-gate dielectric layers 240 in the memory cell stack 220 can determine the number of memory cells 112 in the memory array 110. The gate conductive layers 230 can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In one possible embodiment, each gate conductive layer 230 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 230 includes a doped polysilicon layer. Each gate conductive layer 230 can include a gate surrounding a memory cell 112 and can extend laterally at the top of the memory cell stack 220 as a DSL 150, at the bottom of the memory cell stack 220 as an SSL 160, or between the DSL and the SSL as a WL 130.

[0060] As shown in FIG2 , memory string 111 further includes a channel structure 250 extending vertically through memory cell stack layer 220. Channel structure 250 includes a channel hole filled with at least one semiconductor material (e.g., a semiconductor channel) and at least one dielectric material (e.g., a memory film). In some embodiments, the semiconductor channel includes silicon (e.g., a memory film). In some embodiments, the memory film is a composite dielectric layer including a tunnel layer, a trap layer, and a barrier layer. Channel structure 250 may have a cylindrical shape (e.g., a pillar). In some embodiments, the semiconductor channel, the trap layer (also referred to as the memory layer), and the barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The trap layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0061] As shown in FIG2 , a doped semiconductor layer 260 is stacked on top of the memory cell stack layer 220 in the memory string 111 . The doped semiconductor layer 260 is also called a bit line contact portion. The doped semiconductor layer 260 is coupled to the bit line and is an N-type doped semiconductor layer.

[0062] Referring back to FIG. 1 , the peripheral circuit 140 is coupled to a plurality of word lines 130 . The peripheral circuit 140 controls the memory cells in the selected memory string by controlling the voltage VWL of the word line 130 coupled to the selected memory string and the voltage VBL of the bit line coupled to the selected memory string to implement the following operating method.

[0063] Peripheral circuit 140 includes various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG3 shows a schematic diagram of the structure of a peripheral circuit according to an exemplary embodiment. As shown in FIG3 , peripheral circuit 140 includes a page buffer / sense amplifier 301, a column decoder / bit line (BL) driver 302, a row decoder / word line (WL) driver 303, a voltage generator 304, a control logic unit 305, a register 306, an interface (I / F) 307, and a data bus 308. In some examples, additional peripheral circuits not shown in FIG3 may also be included. Page buffer / sense amplifier 301 can be configured to read data from memory array 110 and program (write) data to memory array 110 based on control signals from control logic unit 305. In one example, page buffer / sense amplifier 301 can store a page of program data (write data) to be programmed into one physical page of memory array 110. In another example, page buffer / sense amplifier 301 can perform program verification operations to ensure that data has been correctly programmed into memory cells 112 coupled to a selected word line. In yet another example, the page buffer / sense amplifier 301 can also sense a low-power signal from a bit line representing a data bit stored in the memory cell 112 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 302 can be configured to be controlled by the control logic unit 305 and select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 304.

[0064] The row decoder / word line driver 303 can be configured to be controlled by the control logic unit 305 and select / deselect the memory block 11b of the memory array 110 and select / deselect the word line 130 of the memory block 11b. The row decoder / word line driver 303 can also be configured to drive the word line using the word line voltage generated from the voltage generator 304. As described in detail below, the row decoder / word line driver 303 is configured to perform an erase operation on the memory cell 112 coupled to the selected word line(s). The voltage generator 304 can be configured to be controlled by the control logic unit 305 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 110.

[0065] The control logic unit 305 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The register 306 may be coupled to the control logic unit 305 and include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 305. The interface 307 may be coupled to the control logic unit 305 and function as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 305, as well as to buffer status information received from the control logic unit 305 and relay it to the host. The interface 307 may also be coupled to the column decoder / bitline driver 302 via the data bus 308 and function as a data I / O interface and data buffer to buffer data and relay it to or from the memory array 110.

[0066] In one embodiment, as shown in FIG4 , the peripheral circuit 140 further includes a low dropout regulator (LDO) 309 and multiple driver transistors 312. The control terminals of the voltage generator 304, the LDO 309, and the multiple driver transistors 312 are all connected to a signal line 91. The LDO 309 is also connected to the SL 170 via a signal line 92. The first terminal of each driver transistor 312 is connected to a different BL 120, and the second terminal of each driver transistor 312 is connected to the same SL 170. The first terminal is the drain of the driver transistor 312, and the second terminal is the source of the driver transistor 312. Alternatively, the first terminal is the source of the driver transistor 312, and the second terminal is the drain of the driver transistor 312.

[0067] When performing an erase operation on the storage block, the voltage generator 304 provides a voltage Vpeh to the signal line 91, so that the voltage Vpeh acts on the LDO309 and each driving transistor 312. The LDO309 converts the voltage Vpeh into a voltage Vpe less than the voltage Vpeh, and provides the voltage Vpe to the signal line 92, so that the voltage Vpe acts on the second end of the driving transistor 312 through the SL170. The voltage Vpeh at the control end of the driving transistor 312 is greater than the voltage Vpe at the second end, so that the driving transistor 312 is turned on and transmits the erase voltage to the bit line 120 and SL170 coupled to the storage string respectively, so that the TSG and BSG of the storage string generate GIDL.

[0068] However, the LDO 309 is relatively large and increases the area of ​​the peripheral circuit 140. Therefore, in another embodiment, a first switch unit 310 is added between the voltage generator 304 and the driver transistor 312, and a second switch unit 311 is added between the voltage generator 304 and the SL 170 to replace the LDO 309, thereby reducing the area of ​​the peripheral circuit 140.

[0069] As shown in Figure 5, the voltage generator 304, the first switch unit 310, and the second switch unit 311 are all connected to the same node (referred to as the first node 313). For example, the voltage generator 304, the first switch unit 310, and the second switch unit 311 are connected to the same signal line, and any position on the signal line is a first node or the signal line is a first node. The voltage generator 304 provides voltage to the first switch unit 310 and the second switch unit 311 via the first node.

[0070] The control terminals of the plurality of driving transistors 312 are all connected to the first switching unit 310. The control terminals of the driving transistors 312 are the gates of the driving transistors 312. The first terminal of each driving transistor 310 is connected to a different BL120, and the second terminal of each driving transistor 310 is connected to the same SL170. The first terminal is the drain of the driving transistor 310, and the second terminal is the source of the driving transistor 310. Alternatively, the first terminal is the source of the driving transistor 310, and the second terminal is the drain of the driving transistor 310.

[0071] In one embodiment, at least one of the first switch unit 310 and the second switch unit 311 includes a transistor and a voltage converter, wherein the voltage converter is coupled to the control terminal of the transistor, and the voltage converter is configured to turn off or turn on the transistor by controlling the control terminal of the transistor.

[0072] Taking the first switch unit 310 as an example, the transistor and the voltage converter in the first switch unit 310 are referred to as a first transistor and a first voltage converter, respectively. The first terminal (e.g., source or drain) of the first transistor is connected to the first node 313. The voltage provided by the voltage generator 304 to the first node 313 is applied to the first terminal of the first transistor. The second terminal (e.g., drain or source) of the first transistor is connected to the control terminal of each driving transistor 312. The first voltage converter is configured to provide a voltage to the control terminal of the first transistor and switch the voltage between a turn-on voltage and a turn-off voltage of the first transistor, wherein the turn-on voltage is greater than or equal to a threshold voltage of the first transistor, and the turn-off voltage is less than the threshold voltage of the first transistor. If the voltage provided to the control terminal of the first transistor is the turn-on voltage, the first transistor is turned on, and a voltage is provided to the control terminal of each driving transistor 312 via the first transistor. If the voltage provided to the control terminal of the first transistor is the turn-off voltage, the first transistor is turned off, and no voltage is provided to the control terminal of each driving transistor 312, causing the control terminal of each driving transistor 312 to float.

[0073] Taking the second switch unit 311 as an example, the transistor and the voltage converter in the second switch unit 311 are referred to as a second transistor and a second voltage converter, respectively. The first terminal (e.g., source or drain) of the second transistor is connected to the first node 313. The voltage provided by the voltage generator 304 to the first node 313 is applied to the first terminal of the second transistor. The second terminal (e.g., drain or source) of the second transistor is connected to the SL 170. The second voltage converter is configured to provide a voltage to the control terminal of the second transistor and switch the voltage between a turn-on voltage and a turn-off voltage of the second transistor, wherein the turn-on voltage is greater than or equal to the threshold voltage of the second transistor and the turn-off voltage is less than the threshold voltage of the second transistor. If the voltage provided to the control terminal of the second transistor is the turn-on voltage, the second transistor is turned on, and voltage is provided to the SL via the second transistor. If the voltage provided to the control terminal of the second transistor is the turn-off voltage, the second transistor is turned off, and no voltage is provided to the SL.

[0074] In another embodiment, at least one of the first switch unit 310 and the second switch unit 311 includes a transistor, and the at least one does not include a voltage converter. In this case, other modules in the peripheral circuit 140 that are independent of the first switch unit 310 and the second switch unit 311 can control the control end of the transistor to turn off or turn on the transistor. The other module may be a voltage converter or may not be a voltage converter.

[0075] As shown in FIG6 , in FIG6 , the first switch unit 310 and the second switch unit are respectively denoted as S1 and S2. The first end of S1 and the first end of S2 are respectively connected to the first node. When S2 is turned off and S1 is turned on, the voltage V2 of the second end of any driving transistor is the voltage V SL , the voltage at the second end of SL is applied to the control end of each driving transistor, that is, the voltage at the second end of S1 is the voltage V at the control end of each driving transistor G , if the voltage V G Greater than or equal to the threshold voltage V of the driving transistor T , then the driving transistor is turned on. Ignoring the voltage loss between the first terminal and the second terminal of the driving transistor, after the driving transistor is turned on, the voltage at the first terminal of the driving transistor V1=V2=V S , voltage V1 is applied to the BL connected to the first terminal of the driver transistor. The BL transmits the voltage V1 to the bit line contact of the memory string connected to the BL. Under the action of voltage V1, GIDL is generated between the bit line contact and the TSG of the memory string. Holes in the GIDL are transferred to the channel of the memory string, and electrons in the channel are transferred to the bit line contact, so as to perform GIDL erasing on the memory cells in the memory string, thereby enabling the driver transistor to assist in GIDL erasing of the memory string. After any driver transistor is turned on, voltage V2 at the second terminal of the driver transistor is transferred to the N-well by the SL connected to it. Under the action of voltage V2, GIDL is generated between the N-well and the BSG of the memory string. Holes in the GIDL are transferred to the channel of the memory string, and electrons in the channel are transferred to the N-well, so as to perform GIDL erasing on the memory cells in the memory string, thereby enabling the driver transistor to assist in GIDL erasing of the memory string.

[0076] The peripheral circuit described above is configured to perform an erase operation on a memory block in the memory. The erase operation is described below in conjunction with the memory operation method flowchart shown in FIG7 . The method shown in FIG7 includes performing an erase operation on any memory block in the memory, and the erase operation includes the following steps.

[0077] 701. Turn off the first switch unit to float the control terminals of the plurality of driving transistors.

[0078] The first switch unit may be the first switch unit 310 in Figure 5, and the plurality of driving transistors may be the driving transistors 312 in Figure 5. The process of turning off the first switch unit 310 has been described above, and this embodiment of the application will not repeat this step 701.

[0079] Taking any driving transistor as an example, since the first switching unit is connected to the control end of the driving transistor, when the first switching unit is turned off, the first switching unit cannot provide voltage to the control end of the driving transistor, thereby causing the control end of the driving transistor to float. Since the control end of the driving transistor floats, the second end of the driving transistor is coupled to the floating control end.

[0080] 702. Turn on the second switch unit to provide a first voltage to the first node. The first switch unit and the second switch unit are both connected to the first node. The first voltage is greater than the threshold voltage of the driving transistor.

[0081] The second switch unit may be the second switch unit 311 in FIG. 5 , and the first node may be the first node 313 in FIG. The process of turning on the second switch unit 311 has been described above and will not be repeated here. The first voltage is the highest voltage provided to the first node during an erase operation on the memory block. During the erase operation, the highest voltage of each BL and SL is less than or equal to the first voltage. Therefore, the first voltage is the maximum erase voltage applied to the memory string during the erase operation.

[0082] 6, and referring to the voltage waveform diagram shown in FIG8, in the period when S1 is turned off and S2 is turned on, a first voltage is provided to the first node so that the voltage V N The voltage before S2 is turned on gradually rises to the first voltage, and then the voltage V N Maintain at the first voltage, ie, voltage V N is equal to the first voltage.

[0083] In one embodiment, a first pulse signal is applied to the first node to provide a first voltage to the first node. For example, the first pulse signal is continuously applied to the first node so that the voltage V N Gradually rise to the first voltage.

[0084] By controlling the voltage amplitude or pulse frequency of the first pulse signal, the voltage V N For example, when the pulse frequency is fixed, the voltage amplitude of the first pulse signal is increased so that the voltage V N The slope of the pulse signal increases, and the voltage amplitude of the first pulse signal decreases, so that the voltage V N The slope of the first pulse signal decreases, or, when the voltage amplitude is fixed, the pulse frequency of the first pulse signal is increased so that the voltage V N The slope of the first pulse signal increases, and the pulse frequency of the first pulse signal decreases, so that the voltage V N Since the first voltage is the maximum erase voltage during the erase operation, by increasing the voltage V N The slope of the voltage VN It quickly rises to the first voltage, so that the memory strings in the memory block can quickly enter the erase state after turning off S1 and turning on S2, thereby reducing the duration of this erase operation (ie, erase duration), that is, saving erase time.

[0085] Next, referring to FIG6 and FIG8, after S1 is turned off and S2 is turned on, and the first voltage is provided to the first node, the voltage V G , the voltage V of the BL connected to the driving transistor BL , SL voltage V SL The impact is introduced as follows.

[0086] Taking any driving transistor as an example, during the period when S1 is turned off, S2 is turned on, and voltage is supplied to the first node, since S1 is turned off, the second terminal of S1 cannot provide voltage to the control terminal of the driving transistor, causing the control terminal to float. At this time, the first voltage is supplied to the first node. Since S2 is turned on, ignoring the voltage loss between the second terminal of S2 and the first terminal of S2, since the second terminal of S2 is coupled to SL, the first voltage acts on SL through S2, causing the voltage V SL The voltage before S2 is turned on rises to the first voltage. Therefore, during the period of turning off S1, turning on S2, and providing voltage to the first node, the voltage V SL and voltage V N The waveform is similar.

[0087] Since the second terminal of the driving transistor is coupled to SL, SL applies the first voltage to the second terminal of the driving transistor. During the period when S1 is turned off, S2 is turned on, and the voltage is provided to the first node, the voltage V2 at the second terminal of the driving transistor increases with the voltage V SL changes with the change of voltage V SL Gradually rises to the first voltage. Since the control terminal of the driving transistor is floating during this period, the control terminal of the driving transistor and the second terminal of the driving transistor are coupled to form a capacitor. The voltage jump principle at both ends of the capacitor makes the voltage V G As the voltage V2 changes, as shown in Figure 8, during this period, the voltage V G With voltage V SL The waveform is similar.

[0088] Before turning off S1, turning on S2 and providing the first voltage to the first node, the driving transistor may have been turned on or not. If the driving transistor has been turned on, as shown in FIG8 , during the period of turning off S1, turning on S2 and providing the voltage to the first node, as the voltage V SL The voltage V at the control terminal of the driving transistor rises GGradually rises. During this period, the driving transistor is used to power BL. Ignoring the voltage loss between the second terminal and the first terminal of the driving transistor, the driving transistor is turned on so that the voltage V1 = V2 = V at the first terminal of the driving transistor SL , the first terminal of the driving transistor provides a voltage V1 to the BL, so that the voltage V BL Gradually increase until it reaches the first voltage.

[0089] During this period, BL will increase the voltage V BL Continuously acts on the bit line contact of the memory string connected to the BL, as V BL When the voltage V increases to a certain level, GIDL is generated between the bit line contact and the TSG of the memory string to perform GIDL erasing on the memory cells in the memory string, thereby enabling the driving transistor to assist the memory string in performing GIDL erasing. SL Continuous action to the N-well of the SL connection, as V SL When it increases to a certain level, GIDL is generated between the N well and the BSG of the memory string where the N well is located, so as to perform GIDL erasing on the memory cells in the memory string, thereby enabling the driving transistor to assist the memory string in performing GIDL erasing. The first voltage is the erase voltage applied to both ends of the memory string, and the voltage V BL and voltage V SL During the period of rising to the first voltage, i.e., the erase voltage rising period, the voltage V BL and voltage V SL The first voltage is maintained during the erase pulse period, so that during the erase operation, the driving transistor remains in the turned-on state during both the erase rise period and the erase pulse period, avoiding the risk of downgrade or even breakdown caused by the driving transistor being turned off, thereby improving the reliability of the circuit.

[0090] The above is introduced by taking the example of executing step 701 first and then executing step 702. In another embodiment, step 701 and step 702 can also be executed at the same time, or step 702 can be executed first and then step 701. Here, the embodiment of the present application does not limit the execution order of step 701 and step 702.

[0091] In the method embodiment shown in Figure 7, the first node is connected to the control terminal and the second terminal of the driving transistor respectively through the first switching unit and the second switching unit, and the first node is connected to the source line connected to the memory string in the memory block through the second switching unit. During the erase operation on the memory block, the control terminal of the driving transistor is floated by turning off the first switching unit, so that the second terminal of the driving transistor is coupled to the control terminal. By turning on the second switching unit, a first voltage is provided to the first node, so that the first voltage acts on the second terminal of the driving transistor through the turned-on second switching unit and the source line, so that the voltage of the control terminal of the driving transistor changes with the change of the voltage of the second terminal. Since the first voltage is greater than the threshold voltage of the driving transistor, when the voltage of the control terminal reaches the threshold voltage, the driving transistor is turned on to perform GIDL erasure on the memory string coupled to the BL connected to the driving transistor.

[0092] Regarding the process shown in steps 701 and 702 above, for the control terminal of the driving transistor, in other embodiments, the control terminal of the driving transistor is coupled to the first switch unit and is also coupled to other modules in the peripheral circuit. When the first switch unit is turned off, the other modules provide an initial voltage for the control terminal, wherein the initial voltage of the control terminal is greater than or equal to 0V and less than the first voltage. In order to make the voltage V G Can quickly rise to the threshold voltage V T , before floating the control terminal, a voltage higher than the initial voltage can be provided to the control terminal through the first node. Still taking Figure 7 as an example, during the erase operation, S1 and S2 are turned off first, and other modules provide the initial voltage to the control terminal of the driving transistor, so that the voltage V G Maintain the initial voltage, continue to keep S2 closed, then switch to the first node to power the control terminal of the driving transistor, turn on S1, and provide the second voltage to the first node. In other embodiments, before switching to the first node to power the control terminal of the driving transistor, other modules can also first provide the initial voltage to the control terminal of the driving transistor, and then provide the turn-on voltage of the driving transistor to the control terminal of the driving transistor, so that the voltage V G From the initial voltage to the turn-on voltage, the voltage V G After maintaining the on-state voltage, the first node is switched to supply power to the control terminal of the driving transistor, S1 is turned on, and a second voltage is provided to the first node, wherein the on-state voltage is greater than the initial voltage of the control terminal of the driving transistor and less than the second voltage. Before providing the second voltage to the first node, a on-state voltage lower than the second voltage is provided to the first node to avoid voltage V GDirectly rising from the initial voltage to the second voltage can improve the voltage tolerance of the driving crystal control terminal on the one hand, and on the other hand, it is also convenient for the subsequent voltage V G Rapidly rise to the second voltage.

[0093] During the period of providing the second voltage to the first node, S1 applies the second voltage of the first node to the control terminal of the driving transistor, so that the voltage V G The voltage gradually rises from the initial voltage to the second voltage and remains at the second voltage, wherein the second voltage is greater than the threshold voltage V T , as the voltage V G When the voltage V G ≥V T When , the driving transistor is turned on. After that, S2 is kept off and S1 is turned off, the control terminal of the driving transistor floats, making the voltage V G Maintaining the second voltage, the driving transistor remains turned on.

[0094] At voltage V G After maintaining the second voltage, S2 continues to remain off, turning off S1, and entering a period where both S1 and S2 are off. During this period, since S1 is turned off, the control terminal of the driving transistor continues to float, and the voltage V G The voltage V of the first node is kept at the second voltage, and the driving transistor is kept turned on. N It gradually discharges from the second voltage to the third voltage until it remains at the third voltage. After that, S1 continues to be turned off and S2 is turned on. Entering the period of S1 being turned off and S2 being turned on, it switches to powering SL through S2, and powering BL through the first end of the driving transistor, providing the first voltage to the first node. The first node provides the first voltage to the second end of the driving transistor through the turned-on S2 and SL, causing the voltage V2 of the second end of the driving transistor to rise. Since the second end of the driving transistor is coupled to the control end, the voltage V G As the voltage V2 rises, the driving transistor continues to be turned on to transfer the first voltage at the second terminal of the driving transistor to the first terminal of the driving transistor, and the first terminal of the driving transistor transfers the first voltage to BL to trigger the memory string to perform GIDL erasure.

[0095] Before providing the first voltage to the first node, the second voltage is provided to the first node to make the driving transistor in the on state, so that the driving transistor can continue to be in the on state during the subsequent process of the driving transistor transmitting the first voltage to the BL, thereby avoiding the driving transistor from being turned off during the erase rising period and the erase pulse period. In some embodiments, the second voltage is higher than the minimum erase voltage required to generate GIDL at both ends of the memory string. Before providing the first voltage to the first node, the voltage V N Discharging to the third voltage reduces the time it takes for BL and SL to rise to the first voltage, thereby reducing the HCI caused by the memory cell quickly entering the GIDL erase state. In other embodiments, the voltage V N After the voltage V is maintained at the second voltage, the voltage V N Discharging, S1 continues to remain turned off, S2 is turned on, and the first voltage is provided to the first node.

[0096] By providing a second pulse signal to the first node, a second voltage is provided to the first node, and by providing a third pulse signal to the first node, a third voltage is provided to the first node. Before providing the first voltage to the first node, the second voltage is provided to the first node and the voltage V N Discharging to the third voltage will increase the erase time of the memory block. In some embodiments, in order to minimize the increased erase time, the voltage V can be increased by controlling the voltage amplitude or pulse frequency of the second pulse signal. N The slope of the third pulse signal rises to the second voltage to minimize the erase time increased by providing the second voltage, and the voltage V is increased by controlling the voltage amplitude or pulse frequency of the third pulse signal. N The slope of the voltage drop to the third voltage is used to minimize the erase time increased by providing the third voltage. The method of controlling the voltage amplitude or pulse frequency of the second pulse signal and the method of controlling the voltage amplitude or pulse frequency of the third pulse signal can refer to the method of controlling the voltage amplitude or pulse frequency of the first pulse signal above and will not be repeated here.

[0097] During the erase operation, assuming that the initial voltage of the signal line where the first node is located is the fifth voltage, in some embodiments, before providing the second voltage to the first node, S1 and S2 are turned off, and the fifth voltage is provided to the first node, so that the voltage V N Maintaining the fifth voltage, S2 continues to be turned off, S1 is turned on, and the second voltage is provided to the first node, so that the voltage V N Increase from the initial voltage to the second voltage.

[0098] In some other embodiments, as shown in FIG. 7 , before providing the second voltage to the first node, S1 and S2 are turned off, and a fifth voltage is provided to the first node, so that the voltage VN Maintaining the fifth voltage, the fourth voltage is supplied to the first node so that the voltage V N From the fifth voltage rises to the fourth voltage, and remains at the fourth voltage, after which S2 continues to remain off, S1 is turned on, and the second voltage is provided to the first node, so that the voltage V N The voltage is raised from the fourth voltage to the second voltage, where the fourth voltage is less than the second voltage, and a voltage is provided to the first node, that is, a voltage is provided to the signal line where the first node is located. Before providing the second voltage to the first node, the voltage of the first node is raised by providing the fourth voltage to the first node, thereby preventing the voltage of the signal line where the first node is located from rising directly from the initial voltage to the second voltage, thereby increasing the voltage tolerance of the signal line where the first node is located. The fourth voltage is also greater than the fifth voltage, and the fourth voltage may be the same as or different from the third voltage. In other embodiments, the fifth voltage is not used as the initial voltage of the first node, but the fourth voltage is used as the initial voltage of the first node. In this case, it is not necessary to provide the fifth voltage to the first node.

[0099] The above description is based on the example of providing the second voltage to the first node. In other embodiments, the second voltage may not be provided to the first node. In this case, it is not necessary to set the voltage V N Discharge to a third voltage. For example, at the voltage V N When the voltage is maintained at the fifth voltage or the fourth voltage, S1 continues to be turned off, S2 is turned on, and the first voltage is provided to the first node, so that the voltage V N Raises from the currently maintained voltage to the first voltage.

[0100] In some embodiments, in addition to being coupled to the first terminal of the driving transistor, the BL is also coupled to other modules in the peripheral circuit (for example, the BL in FIG4 is also coupled to the page buffer). Before the second switch unit is turned on, the other modules provide an initial voltage to the BL. The initial voltage of the BL is greater than or equal to 0V and less than the first voltage. Still taking FIG7 as an example, during the erase operation, assuming that the initial voltage of the BL is the seventh voltage, before S2 is turned on, S2 remains off. Initially, the other modules first provide the seventh voltage to the BL. When the voltage V BL After maintaining the seventh voltage, the sixth voltage is provided to BL so that V BL Maintain the sixth voltage until S2 is turned on and the driver transistor powers BL, or the driver transistor powers BL first and then S2 is turned on. After that, the first node provides the first voltage to the second terminal of the driver transistor by turning on S2 and SL. As the driver transistor voltage V2 rises, V BLGradually rise from the sixth voltage to the first voltage, wherein the seventh voltage is less than the sixth voltage, and the sixth voltage is less than the first voltage. Before providing the first voltage to the first node, the sixth voltage is provided to BL to raise the voltage V BL , avoid voltage V BL Directly rising from the seventh voltage to the first voltage increases the voltage tolerance of the BL.

[0101] During the erase operation, if the fourth voltage is provided to the first node and the sixth voltage is provided to the BL, in order to facilitate control, in some embodiments, as shown in FIG7 , the fourth voltage can be provided to the first node and the sixth voltage can be provided to the BL at the same time. In other embodiments, the fourth voltage can be provided to the first node and the sixth voltage can be provided to the BL at different times. For example, the fourth voltage can be provided to the first node first and the sixth voltage can be provided to the BL second, or the sixth voltage can be provided to the BL first and the fourth voltage can be provided to the first node. In other embodiments, the seventh voltage is not used as the initial voltage of the BL, but the sixth voltage is used as the initial voltage of the BL. In this case, it is not necessary to provide the seventh voltage to the BL, that is, before turning on S2, the voltage V BL Maintain at seventh voltage.

[0102] In some embodiments, the SL may be powered by other modules. When the memory block is erased, the SL is powered by the second switch unit. For example, before the second switch unit is turned on, the SL is provided with an initial voltage by other modules. The initial voltage of the SL is greater than or equal to 0V and less than the first voltage. Still taking FIG. 7 as an example, during the erase operation of the memory block, assuming that the initial voltage of the SL is the ninth voltage, before S2 is turned on, S2 remains off. Initially, the other modules first provide the ninth voltage to the SL. When the voltage V SL After being maintained at the ninth voltage, the eighth voltage is provided to SL so that the voltage V SL l is maintained at the eighth voltage until S2 is turned on and the SL is powered by S2, or S2 is first switched to power the BL and then S2 is turned on. After that, the first node provides the first voltage to the SL by turning on S2, so that the voltage V SL Gradually rise from the eighth voltage to the first voltage, wherein the ninth voltage is less than the eighth voltage, and the eighth voltage is less than the first voltage. Before providing the first voltage to the first node, the eighth voltage is provided to SL to raise the voltage of SL, thereby avoiding the voltage V SL Directly rising from the ninth voltage to the first voltage increases the voltage tolerance of the SL.

[0103] During the erase operation, if the fourth voltage is provided to the first node and the eighth voltage is provided to the SL, in order to facilitate control, in some embodiments, as shown in FIG7 , the fourth voltage may be provided to the first node and the eighth voltage may be provided to the SL at the same time. In other embodiments, the fourth voltage may be provided to the first node and the eighth voltage may be provided to the SL at different times. For example, the fourth voltage may be provided to the first node first and the eighth voltage may be provided to the SL second, or the eighth voltage may be provided to the SL first and the fourth voltage may be provided to the first node. In other embodiments, the ninth voltage is not used as the initial voltage of the SL, but the eighth voltage is used as the initial voltage of the SL. In this case, it is not necessary to provide the eighth voltage to the SL, that is, before turning on S2, the voltage V SL Maintained at the eighth voltage.

[0104] For the erase operation process described above, for the sake of convenience, the voltage loss between the first node, S2, S1, the driving transistor, and SL is ignored. Based on this, as shown in FIG7 , during the period of providing the first voltage to the first node, the voltage V SL and voltage V BL can rise to the first voltage. If voltage loss is taken into account, during the period of providing the first voltage to the first node, the voltage V SL and / or voltage V BL The first voltage may not be reached, and may be slightly lower than the first voltage. For the erase operation process described above, for the sake of convenience, the signal transmission delay between the first node, S2, S1, the driving transistor, and SL is ignored. Based on this, as shown in Figure 7, after S1 is turned off and S2 is turned on to apply the first voltage to the first node, the voltage V N , voltage V G , voltage V BL , voltage V SL At the same time, if the signal transmission delay is taken into account, during the time period of the first voltage provided to the first node, the voltage V SL , voltage V G and voltage V BL The time when the voltage starts to rise may be later than the voltage V N When the voltage starts to rise, V SL The moment when the voltage starts to rise, V G The time when the voltage starts to rise and the voltage V BL The moment when l starts to rise may be the same or different.

[0105] The memory 100 described above can be applied in a storage system to provide data storage services for hosts in the storage system. Next, the architecture of the storage system is described as follows.

[0106] Figure 9 is a schematic diagram of a storage system according to an exemplary embodiment. As shown in Figure 9, the storage system 900 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0107] As shown in FIG9 , a storage system 900 includes a host 901 and a storage subsystem 902. The host 901 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 901 may be configured to send data to the memory 100 in the storage subsystem 902. Alternatively, the host 901 may be configured to receive data from the memory 100.

[0108] The storage subsystem 902 includes one or more memories 100 and a controller 200. The memories 100 are coupled to the controller 200. The memories 100 can be any memory disclosed herein. Optionally, the memories 100 are NAND flash memory devices, such as three-dimensional (3D) NAND flash memory devices.

[0109] According to some embodiments, the controller 200 is also coupled to the host 901. The controller 200 may manage data stored in the memory 100 and communicate with the host 901.

[0110] In one embodiment, the controller 200 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0111] In one embodiment, the controller 200 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0112] The controller 200 may be configured to control operations of the memory 100, such as read, erase, and program operations. The controller 200 may also be configured to manage various functions regarding data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In one embodiment, the controller 200 is further configured to process error correction code (ECC) on data read from or written to the memory 100.

[0113] The controller 200 may also perform any other suitable functions, such as formatting the memory 100. The controller 200 may communicate with an external device (e.g., the host 901) according to a specific communication protocol. For example, the controller 200 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0114] The controller 200 and one or more memories 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the storage system 900 can be implemented and packaged into different types of terminal electronic products.

[0115] FIG10 is a schematic diagram of a memory card according to an exemplary embodiment. As shown in FIG10 , a controller 200 and a single memory 100 may be integrated into a memory card 1000. The memory card 1000 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 1000 may also include a memory card connector 1001 for coupling the memory card 1000 to a host (e.g., the host 901 in FIG9 ).

[0116] FIG11 is a schematic diagram of a solid-state drive according to an exemplary embodiment. As shown in FIG11 , a controller 200 and a plurality of memories 100 may be integrated into a solid-state drive (SSD) 1100. The solid-state drive 1100 may further include a solid-state drive connector 1101 for coupling the solid-state drive 1100 to a host (e.g., the host 901 in FIG9 ). In one embodiment, the storage capacity and / or operating speed of the solid-state drive 1100 is greater than the storage capacity and / or operating speed of the memory card 900.

[0117] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A memory, characterized in that: The memory comprises: A plurality of memory blocks, each of the memory blocks comprising a plurality of memory strings, each of the memory strings being respectively connected to different bit lines and the same source line; and A peripheral circuit, the peripheral circuit comprising a plurality of driving transistors, a first switch unit connected to the control terminals of the plurality of driving transistors, and a second switch unit connected to the source line, the first terminal of each of the driving transistors being respectively connected to a different bit line, the second terminal being connected to the source line, the first switch unit and the second switch unit being both connected to a first node; wherein the peripheral circuit is configured to perform an erase operation on the storage block, and to perform the erase operation, the peripheral circuit is configured as follows: Turning off the first switch unit to float the control terminals of the plurality of driving transistors; The second switch unit is turned on to provide a first voltage to the first node, where the first voltage is greater than a threshold voltage of the plurality of driving transistors.

2. The memory according to claim 1, characterized in that: The peripheral circuit is further configured as: Before turning off the first switch unit, the first switch unit is turned on, the second switch unit is turned off, and a second voltage is provided to the first node, where the second voltage is lower than the first voltage.

3. The memory according to claim 2, characterized in that: The peripheral circuit is further configured as: After the second voltage is provided to the first node, the first switch unit is turned off to discharge the voltage provided to the first node from the second voltage to a third voltage.

4. The memory according to claim 2 or 3, characterized in that: The peripheral circuit is further configured as: Before providing the second voltage to the first node, a fourth voltage is provided to the first node, or a fifth voltage is provided to the first node first and then the fourth voltage is provided to the first node, the fifth voltage is lower than the fourth voltage, and the fourth voltage is lower than the second voltage.

5. The memory according to any one of claims 1 to 4, characterized in that: The peripheral circuit is further configured as: Before providing the first voltage to the first node, a sixth voltage is provided to the bit line, or a seventh voltage is provided to the bit line first and then the sixth voltage is provided to the bit line, the seventh voltage is smaller than the sixth voltage, and the sixth voltage is smaller than the first voltage.

6. The memory according to any one of claims 1 to 5, characterized in that: The peripheral circuit is further configured as: Before providing the first voltage to the first node, an eighth voltage is provided to the source line, or a ninth voltage is provided to the source line first and then the eighth voltage is provided to the source line, the ninth voltage is lower than the eighth voltage, and the eighth voltage is lower than the first voltage.

7. The memory according to any one of claims 1 to 6, characterized in that: At least one of the first switch unit and the second switch unit includes a transistor.

8. The memory according to any one of claims 1 to 6, characterized in that: At least one of the first switch unit and the second switch unit includes a transistor and a voltage converter, wherein the voltage converter is coupled to a control terminal of the transistor, and the voltage converter is configured as follows: A voltage is provided to the control terminal of the transistor to turn off or turn on the transistor.

9. A storage system, characterized in that: The storage system comprises a controller and the memory according to any one of claims 1 to 8, wherein the controller is coupled to the memory and is configured to control the memory.

10. The system according to claim 9, characterized in that The storage system further includes a host; the host is coupled to the controller, and the host is configured to send data to the memory or receive data from the memory through the controller.

11. A method for operating a memory, characterized in that: The memory comprises: a plurality of memory blocks, each of the memory blocks comprises a plurality of memory strings, each of the memory strings is respectively connected to different bit lines and the same source line, the different bit lines are respectively connected to first ends of different driving transistors, a first switch unit connected to a control end of the driving transistor and a second switch unit connected to the source line are both connected to a first node; The method includes performing an erase operation on the storage block, the erase operation including: Turning off the first switch unit to float the control terminal of the driving transistor; The second switch unit is turned on to provide a first voltage to the first node, where the first voltage is greater than a threshold voltage of the driving transistor.

12. The method according to claim 11, characterized in that The erasing operation further includes: Before turning off the first switch unit, the first switch unit is turned on, the second switch unit is turned off, and a second voltage is provided to the first node, where the second voltage is lower than the first voltage.

13. The method according to claim 12, characterized in that The erasing operation further includes: After the second voltage is provided to the first node, the first switch unit is turned off to discharge the voltage provided to the first node from the second voltage to a third voltage.

14. The method according to claim 12 or 13, characterized in that The erasing operation further includes: Before providing the second voltage to the first node, a fourth voltage is provided to the first node, or a fifth voltage is provided to the first node first and then the fourth voltage is provided to the first node, the fifth voltage is lower than the fourth voltage, and the fourth voltage is lower than the second voltage.

15. The method according to any one of claims 11 to 14, characterized in that The erasing operation further includes: Before providing the first voltage to the first node, a sixth voltage is provided to the bit line, or a seventh voltage is provided to the bit line first and then the sixth voltage is provided to the bit line, the seventh voltage is smaller than the sixth voltage, and the sixth voltage is smaller than the first voltage.

16. The method according to any one of claims 11 to 15, characterized in that The erasing operation further includes: Before providing the first voltage to the first node, an eighth voltage is provided to the source line, or a ninth voltage is provided to the source line first and then the eighth voltage is provided to the source line, the ninth voltage is lower than the eighth voltage, and the eighth voltage is lower than the first voltage.

17. The method according to any one of claims 11 to 15, characterized in that At least one of the first switch unit and the second switch unit includes a transistor.

18. The method according to any one of claims 11 to 16, characterized in that: At least one of the first switch unit and the second switch unit includes a transistor and a voltage converter, and the erasing operation further includes: A voltage is provided to the control terminal of the transistor to turn off or turn on the transistor.

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