Reference voltage source and chip

Abstract

The invention provides a reference voltage source and a chip, the reference voltage source comprises a band-gap reference unit and a clamping unit, and the clamping unit comprises a differential amplifier and a self-biasing circuit; the self-bias circuit is used for providing bias current for the differential amplifier, so that the differential amplifier enters a working state; the differential amplifier is used for providing a feedback signal for the band-gap reference unit, so that the band-gap reference unit generates band-gap reference voltage; wherein the self-biasing circuit is multiplexed with the output stage of the differential amplifier.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of electronic circuits, and more particularly, to a reference voltage source and a chip. Background Art

[0002] A reference voltage source is an indispensable unit module in a mixed-signal unit and is widely used in the integrated circuit design of high-precision power management chips, high-precision analog-to-digital / digital-to-analog conversion chips, and memory chips. Among many reference voltage source technologies, a bandgap reference can provide a stable bandgap reference voltage in an environment where temperature, process, and power supply voltage change, and has become the most widely used reference voltage source technology at present. Summary of the Invention

[0003] An object of embodiments of the present disclosure is to provide a reference voltage source and a chip.

[0004] According to a first aspect of embodiments of the present disclosure, a reference voltage source is provided, including a bandgap reference unit and a clamping unit, where the clamping unit includes a differential amplifier and a self-biasing circuit;

[0005] The self-biasing circuit is configured to provide a bias current for the differential amplifier to enable the differential amplifier to enter a working state;

[0006] The differential amplifier is configured to provide a feedback signal for the bandgap reference unit to enable the bandgap reference unit to generate a bandgap reference voltage;

[0007] Wherein, the self-biasing circuit is multiplexed with an output stage of the differential amplifier.

[0008] Optionally, the reference voltage source further includes a startup unit, and the startup unit is configured to provide a startup current for the self-biasing circuit when the reference voltage source is powered on to enable the self-biasing circuit to enter a working state.

[0009] Optionally, the startup unit is further configured to stop providing the startup current to the self-biasing circuit after the self-biasing circuit is started.

[0010] Optionally, the startup unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor. The first MOS transistor and the second MOS transistor are connected in series between the power supply terminal and the ground terminal of the reference voltage source. The third MOS transistor and the fourth MOS transistor are connected in series between the power supply terminal and the ground terminal. The gate of the second MOS transistor is connected to the gates of the third MOS transistor and the drain of the first MOS transistor. The gate of the first MOS transistor is connected to the power supply terminal. The potential point between the third MOS transistor and the fourth MOS transistor is connected to the gate of the fifth MOS transistor. The gate of the fourth MOS transistor is connected to the output terminal of the self - bias circuit. The fifth MOS transistor is connected between the ground terminal and the input terminal of the self - bias circuit.

[0011] Optionally, the width - to - length ratio of the fourth MOS transistor is greater than that of the third MOS transistor.

[0012] Optionally, the bandgap reference unit includes a sixth MOS transistor, a seventh MOS transistor, a first triode, a second triode, a first resistor, a second resistor, a third resistor, and a reference output terminal for outputting the bandgap reference voltage. The sixth MOS transistor and the seventh MOS transistor are connected in series between the power supply terminal of the reference voltage source and the reference output terminal. The gate of the sixth MOS transistor is connected to the first output terminal of the differential amplifier. The gate of the seventh MOS transistor is connected to the second output terminal of the differential amplifier. The first resistor is connected between a first potential point and the reference output terminal. The first triode is connected between the first potential point and the ground terminal of the reference voltage source. The second resistor is connected between a second potential point and the reference output terminal. The third resistor is connected between the second potential point and the emitter of the second triode. The collector of the second triode is connected to the ground terminal. The bases of the first triode and the second triode are both connected to the ground terminal.

[0013] Optionally, the self - bias circuit includes a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty - first MOS transistor, a twenty - second MOS transistor, and a fourth resistor. The sixteenth MOS transistor, the seventeenth MOS transistor, the fourth resistor, the nineteenth MOS transistor, and the twenty - first MOS transistor are connected in series between the power supply terminal and the ground terminal. The eighteenth MOS transistor, the twentieth MOS transistor, and the twenty - second MOS transistor are connected in series between the power supply terminal and the ground terminal. The gate of the seventeenth MOS transistor, which serves as the output terminal of the self - bias circuit, is connected to the gate and the drain of the eighteenth MOS transistor. The gate of the nineteenth MOS transistor is connected to the gate of the twentieth MOS transistor and the drain of the seventeenth MOS transistor. The gate of the twenty - first MOS transistor, which serves as the input terminal of the self - bias circuit, is connected to the gate of the twenty - second MOS transistor and the drain of the nineteenth MOS transistor.

[0014] Optionally, the gate of the twenty - first MOS transistor is multiplexed as the first output terminal for outputting a feedback signal in the differential amplifier and is connected to the gate of the sixth MOS transistor. The gate of the nineteenth MOS transistor is multiplexed as the second output terminal for outputting another feedback signal in the differential amplifier and is connected to the gate of the seventh MOS transistor.

[0015] Optionally, the differential amplifier further includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, and a fifteenth MOS transistor. The eighth MOS transistor and the ninth MOS transistor are connected in series between the power supply terminal and the source of the tenth MOS transistor. The twelfth MOS transistor and the fourteenth MOS transistor are connected in series between the drain of the tenth MOS transistor and the ground terminal. The source of the eleventh MOS transistor is connected to the source of the tenth MOS transistor. The thirteenth MOS transistor and the fifteenth MOS transistor are connected in series between the drain of the eleventh MOS transistor and the ground terminal. The gate of the eighth MOS transistor is connected to the gate of the twenty - first MOS transistor. The gate of the ninth MOS transistor is connected to the gate of the nineteenth MOS transistor. The gate of the tenth MOS transistor is connected to the first potential point. The gate of the eleventh MOS transistor is connected to the second potential point. The gates of the twelfth MOS transistor and the thirteenth MOS transistor are both connected to the gate of the seventeenth MOS transistor. The gates of the fourteenth MOS transistor and the fifteenth MOS transistor are both connected to the drain of the tenth MOS transistor.

[0016] Optionally, the resistance value of the first resistor is equal to that of the second resistor, and the ratio between the resistance value of the first resistor and that of the third resistor is determined according to the collector current of the first triode, the saturation current of the first triode, and the ratio of the emitter areas of the first triode and the second triode, so that the voltage between the first potential point and the second potential point is equal.

[0017] According to a second aspect of the present disclosure, there is provided a chip including the reference voltage source as described in the first aspect of the present disclosure.

[0018] Through the embodiments of the present disclosure, the reference voltage source multiplexes the self - bias circuit and the output stage of the differential amplifier, which can improve the utilization rate of the devices in the reference voltage source and reduce the circuit area and power consumption of the reference voltage source.

[0019] Other features and advantages of the present invention will become clear from the following detailed description of the exemplary embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.

[0021] Figure 1 is a block diagram of a reference voltage source according to an embodiment of the present disclosure;

[0022] Figure 2 is a block diagram of a reference voltage source according to another embodiment of the present disclosure;

[0023] Figure 3 is a circuit schematic diagram of a reference voltage source according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] Now, various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.

[0025] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present invention or its application or use.

[0026] Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and devices should be regarded as part of the specification.

[0027] In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Thus, other examples of the exemplary embodiments may have different values.

[0028] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

[0029] The present disclosure provides a reference voltage source. As Figure 1 shown, the reference voltage source 1000 may include a bandgap reference unit 1100 and a clamping unit 1200, and the clamping unit 1200 includes a differential amplifier 1210 and a self - biasing circuit 1220.

[0030] The self - biasing circuit 1220 is used to provide a bias current for the differential amplifier 1210 to enable the differential amplifier 1210 to enter the operating state.

[0031] The differential amplifier 1210 is used to provide a feedback signal for the bandgap reference unit 1100 to enable the bandgap reference unit 1100 to generate a bandgap reference voltage.

[0032] Among them, the self - biasing circuit 1220 is multiplexed with the output stage of the differential amplifier 1210.

[0033] In this embodiment, the self - biasing circuit 1220 is multiplexed with the output stage of the differential amplifier 1210, that is, the electronic devices in the self - biasing circuit 1220 are multiplexed to form the output stage of the differential amplifier 1210.

[0034] Through the embodiments of the present disclosure, the reference voltage source multiplexes the self - biasing circuit and the output stage of the differential amplifier, which can improve the utilization rate of the devices in the reference voltage source and reduce the circuit area and power consumption of the reference voltage source.

[0035] In an embodiment of the present disclosure, as Figure 2 shown, the reference voltage source 1000 further includes a startup unit 1300, and the startup unit 1300 is used to provide a startup current for the self - biasing circuit 1220 when the reference voltage source 1100 is powered on to enable the self - biasing circuit 1220 to enter the operating state.

[0036] Specifically, the output terminal of the startup unit 1300 is connected to the input terminal of the self - biasing circuit 1220 to enable the startup unit 1300 to provide a startup current for the self - biasing circuit 1220.

[0037] In an embodiment of the present disclosure, the startup unit 1300 is further used to stop providing the startup current to the self - biasing circuit 1220 after the self - biasing circuit 1220 is started.

[0038] In this embodiment, after the self - bias circuit 1220 enters the working state, it can continue to work according to the input voltage of the reference voltage source 1000. Moreover, the input terminal of the self - bias circuit 1220 is multiplexed with the first output terminal of the differential amplifier 1210, so as to enable the differential amplifier 1210 to normally provide a feedback signal for the band - gap reference unit 1100. Therefore, after the self - bias circuit 1220 is started, the start - up unit 1300 stops providing a start - up current to the self - bias circuit 1220, so as to ensure that the reference voltage source 1000 can normally output the band - gap reference voltage and reduce the power consumption of the reference voltage source.

[0039] In one embodiment of the present disclosure, as Figure 3 shown, the start - up unit 1300 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, and a fifth MOS transistor M5. The first MOS transistor M1 and the second MOS transistor M2 are connected in series between the power supply terminal VDD and the ground terminal GND of the reference voltage source. The third MOS transistor M3 and the fourth MOS transistor M4 are connected in series between the power supply terminal VDD and the ground terminal GND. The gate of the second MOS transistor M2, the gate of the third MOS transistor M3, and the drain of the first MOS transistor M1 are connected. The gate of the first MOS transistor M1 is connected to the power supply terminal. The potential point between the third MOS transistor M3 and the fourth MOS transistor M4 is connected to the gate of the fifth MOS transistor M5. The gate of the fourth MOS transistor M4 is connected to the output terminal of the self - bias circuit. The fifth MOS transistor M5 is connected between the ground terminal and the input terminal of the self - bias circuit.

[0040] In this embodiment, the source of the second MOS transistor M2 and the source of the third MOS transistor M3 are connected to the power supply terminal VDD. The source of the first MOS transistor M1, the source of the fourth MOS transistor M4, and the source of the fifth MOS transistor M5 are all connected to the ground terminal GND. The drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4 are both connected to the gate of the fifth MOS transistor M5.

[0041] In the embodiment of the present disclosure, the width - to - length ratio of the fourth MOS transistor M4 is greater than the width - to - length ratio of the third MOS transistor M3.

[0042] In one embodiment of the present disclosure, as Figure 3As shown, the bandgap reference cell 1100 includes a sixth MOS transistor M6, a seventh MOS transistor M7, a first bipolar transistor Q1, a second bipolar transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a reference output terminal Vout for outputting a bandgap reference voltage Vref. The sixth MOS transistor M6 and the seventh MOS transistor M7 are connected in series between the power supply terminal VDD and the reference output terminal Vout. The gate of the sixth MOS transistor M6 is connected to the first output terminal vp1 of the differential amplifier 1210, and the gate of the seventh MOS transistor M7 is connected to the second output terminal vp2 of the differential amplifier 1210. The first resistor R1 is connected between the first potential point P1 and the reference output terminal Vout. The first bipolar transistor Q1 is connected between the first potential point P1 and the ground terminal GND. The second resistor R2 is connected between the second potential point P2 and the reference output terminal Vout. The third resistor R3 is connected between the second potential point P2 and the emitter of the second bipolar transistor Q2. The collector of the second bipolar transistor Q2 is connected to the ground terminal GND. The bases of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both connected to the ground terminal GND.

[0043] In this embodiment, the source of the sixth MOS transistor M6 is connected to the power supply terminal VDD, the drain of the sixth MOS transistor M6 is connected to the source of the seventh MOS transistor M7, and the drain of the seventh MOS transistor M7 is connected to the reference output terminal Vout.

[0044] In one embodiment of the present disclosure, as Figure 3 shown, the self - bias circuit 1220 includes a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty - first MOS transistor M21, a twenty - second MOS transistor M22, and a fourth resistor R4. The sixteenth MOS transistor M16, the seventeenth MOS transistor M17, the fourth resistor R4, the nineteenth MOS transistor M19, and the twenty - first MOS transistor M21 are connected in series between the power supply terminal and the ground terminal. The eighteenth MOS transistor M18, the twentieth MOS transistor M20, and the twenty - second MOS transistor M22 are connected in series between the power supply terminal VDD and the ground terminal GND. The gate of the seventeenth MOS transistor M17 serves as the output terminal vn of the self - bias circuit 1220 and is connected to the gate and the drain of the eighteenth MOS transistor M18. The gate of the nineteenth MOS transistor M19 is connected to the gate of the twentieth MOS transistor M20 and the drain of the seventeenth MOS transistor M17. The gate of the twenty - first MOS transistor M21 serves as the input terminal vp1 of the self - bias circuit 1220 and is connected to the gate of the twenty - second MOS transistor M22 and the drain of the nineteenth MOS transistor M19.

[0045] In this embodiment, the source electrodes of the twenty-first MOS transistor M21 and the twenty-second MOS transistor M22 are both connected to the power supply terminal VDD. The drain electrode of the twenty-first MOS transistor M21 is connected to the source electrode of the nineteenth MOS transistor M19. The drain electrode of the nineteenth MOS transistor M19 is connected to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is connected to the drain electrode of the seventeenth MOS transistor M17. The source electrode of the seventeenth MOS transistor M17 is connected to the drain electrode of the sixteenth MOS transistor M16. The source electrode of the sixteenth MOS transistor M16 is connected to the ground terminal GND. The drain electrode of the twenty-second MOS transistor M22 is connected to the source electrode of the twentieth MOS transistor M20. The drain electrode of the twentieth MOS transistor M20 is connected to the drain electrode of the eighteenth MOS transistor M18. The source electrode of the eighteenth MOS transistor M18 is connected to the ground terminal GND.

[0046] In one embodiment of the present disclosure, the gate electrode of the twenty-first MOS transistor M21 is multiplexed as the first output terminal vp1 for outputting a feedback signal in the differential amplifier 1210 and is connected to the gate electrode of the sixth MOS transistor M6. The gate electrode of the nineteenth MOS transistor M19 is multiplexed as the second output terminal vp2 for outputting another feedback signal in the differential amplifier 1210 and is connected to the gate electrode of the seventh MOS transistor M7.

[0047] In one embodiment of the present disclosure, as Figure 3 shown, the differential amplifier 1210 further includes an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, and a fifteenth MOS transistor M15. The eighth MOS transistor M8 and the ninth MOS transistor M9 are connected in series between the power supply terminal VDD and the source electrode of the tenth MOS transistor M10. The twelfth MOS transistor M12 and the fourteenth MOS transistor M14 are connected in series between the drain electrode of the tenth MOS transistor M10 and the ground terminal GND. The source electrode of the eleventh MOS transistor M11 is connected to the source electrode of the tenth MOS transistor M10. The thirteenth MOS transistor M13 and the fifteenth MOS transistor M15 are connected in series between the drain electrode of the eleventh MOS transistor M11 and the ground terminal GND. The gate electrode of the eighth MOS transistor M8 is connected to the gate electrode of the twenty-first MOS transistor M21. The gate electrode of the ninth MOS transistor M9 is connected to the gate electrode of the nineteenth MOS transistor M19. The gate electrode of the tenth MOS transistor M10 is connected to the first potential point P1. The gate electrode of the eleventh MOS transistor M11 is connected to the second potential point P2. The gate electrodes of the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 are both connected to the gate electrode of the seventeenth MOS transistor M17. The gate electrodes of the fourteenth MOS transistor M14 and the fifteenth MOS transistor M15 are both connected to the drain electrode of the tenth MOS transistor M10.

[0048] In this embodiment, the source of the eighth MOS transistor M8 is connected to the power supply terminal VDD, the drain of the eighth MOS transistor M8 is connected to the source of the ninth MOS transistor M9, the drain of the ninth MOS transistor M9 is connected to the sources of the tenth MOS transistor M10 and the eleventh MOS transistor M11, the drain of the tenth MOS transistor M10 is connected to the drain of the twelfth MOS transistor M12, the source of the twelfth MOS transistor M12 is connected to the drain of the fourteenth MOS transistor M14, the drain of the fourteenth MOS transistor M14 is connected to the ground terminal GND, the drain of the eleventh MOS transistor M11 is connected to the drain of the thirteenth MOS transistor M13, the source of the thirteenth MOS transistor M13 is connected to the drain of the fifteenth MOS transistor M15, and the source of the fifteenth MOS transistor M15 is connected to the ground terminal GND.

[0049] In an embodiment of the present disclosure, the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2, and the ratio between the resistance value of the first resistor R1 and the resistance value of the third resistor R3 is determined according to the collector current of the first triode Q1, the saturation current of the first triode Q1, and the ratio of the emitter areas of the first triode Q1 and the second triode Q2, so that the voltage between the first potential point and the second potential point is equal.

[0050] In this embodiment, the negative feedback structure formed by the clamping unit 1200 and the bandgap reference unit 1100 can reduce the influence of power supply fluctuations or device mismatches on the bandgap reference voltage.

[0051] In this embodiment, the clamping unit 1200 utilizes the negative feedback characteristic of the differential amplifier 1210 to ensure that the potentials of the first potential point P1 and the second potential point P2 are the same, and assists the bandgap reference unit 1100 to construct a bandgap reference voltage with zero temperature coefficient.

[0052] In this embodiment, the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, the fifteenth MOS transistor M15, the sixteenth MOS transistor M16, the seventeenth MOS transistor M17, and the eighteenth MOS transistor M18 are all N-type MOS transistors, and the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, the nineteenth MOS transistor M19, the twentieth MOS transistor M20, the twenty-first MOS transistor M21, and the twenty-second MOS transistor M22 are all P-type MOS transistors.

[0053] When the reference voltage source 1000 is powered on, the power supply terminal VDD becomes high level. The startup unit 1300 draws current from the vp1 point of the self - bias circuit to lower its potential, and the bandgap reference unit 1100 and the clamping unit quickly enter the normal working state. After the bandgap reference unit 1100 and the clamping unit 1200 work normally, M5 of the startup unit is turned off.

[0054] Specifically, when the reference voltage source 1000 is powered on, the power supply voltage of the power supply terminal VDD increases. When the power supply voltage rises to the threshold voltage of the first MOS transistor M1, the first MOS transistor M1 conducts. After the first MOS transistor M1 conducts, the gate voltages of the second MOS transistor M2 and the third MOS transistor M3 gradually decrease. When the gate voltage of the third MOS transistor M3 is smaller than the power supply voltage by a threshold voltage, the third MOS transistor M3 conducts. The conduction of the third MOS transistor M3 will pull up the gate voltage of the fifth MOS transistor M5 to the power supply voltage. Therefore, the fifth MOS transistor M5 conducts. After the fifth MOS transistor M5 conducts, it pulls down the level of the input terminal vp1 of the self - bias circuit 1220, and the clamping unit 1200 and the bandgap reference unit 1100 enter the normal working state. The gate of the eighteenth MOS transistor M18 is connected to the gate of the fourth MOS transistor M4. After the reference voltage source 1000 is powered on, the gate potentials of the third MOS transistor M3 and the fourth MOS transistor M4 are both fixed values. Since the width - length ratio of the third MOS transistor M3 is much smaller than that of the fourth MOS transistor M4, this imbalance will cause the fourth MOS transistor M4 to enter the linear region after the bandgap reference unit 1100 and the clamping unit 1200 work normally. Therefore, the gate voltage of the fifth MOS transistor M5 will be pulled down to the voltage of the ground terminal GND through the fourth MOS transistor M4, ensuring that the fifth MOS transistor M5 is turned off after the power - on is completed, and stopping providing startup current for the self - bias circuit 1220.

[0055] The startup unit 1300 can ensure that when the reference voltage source 1000 is powered on, the bandgap reference unit 1100 and the clamping unit 1200 get rid of the circuit degeneracy point and quickly enter the normal working state. After the reference voltage source 1000 is powered on, the fifth MOS transistor M5 can be reliably turned off, reducing the circuit power consumption without affecting the normal operation of the rest of the circuit.

[0056] The clamping unit 1200 is essentially a differential amplifier 1210. The first stage of the differential amplifier 1210 is composed of the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, and the fifteenth MOS transistor M15. The second stage is composed of the sixteenth MOS transistor M16, the seventeenth MOS transistor M17, the nineteenth MOS transistor M19, and the twenty-first MOS transistor M21. The second stage of the differential amplifier 1210 adopts a self-biased structure, and generates a feedback voltage through the first output terminal vp1 and the second output terminal vp2. The eighth MOS transistor M8 and the ninth MOS transistor M9 of the first stage copy the current of the nineteenth MOS transistor M19 and the twenty-first MOS transistor M21 one by one, and are used for the first stage of the differential amplifier 1210.

[0057] The bandgap reference unit 1100 dynamically adjusts the voltage VA of the first potential point P1 and the voltage VB of the second potential point P2 through the feedback signals output from the first output terminal vp1 and the second output terminal vp2 of the differential amplifier 1210 to ensure that VA = VB.

[0058] If the voltage VB of the second potential point P2 is slightly greater than the voltage VA of the first potential point P1 due to the change of the power supply voltage or the process deviation, then the current flowing through the eleventh MOS transistor M11, the thirteenth MOS transistor M13, and the fifteenth MOS transistor M15 decreases, and the current flowing through the tenth MOS transistor M10, the twelfth MOS transistor M12, and the fourteenth MOS transistor M14 increases. The gate voltage of the fifteenth MOS transistor M15 increases. Complying with the principle of current consistency, the voltage of the drain of the thirteenth MOS transistor M13 (the gate of the sixteenth MOS transistor M16) decreases, so that the current of the branch of the sixteenth MOS transistor M16, the seventeenth MOS transistor M17, the nineteenth MOS transistor M19, and the twenty-first MOS transistor M21 decreases. The nineteenth MOS transistor M19 and the twenty-first MOS transistor M21 are both in diode connection form. Therefore, the voltages of the first output terminal vp1 and the second output terminal vp2 increase, resulting in a decrease of ΔV in the voltage of the drain of the seventh MOS transistor M7. The voltage division by the resistor causes the decrease amount of the voltage VA of the first potential point P1 to be less than the decrease amount of the voltage VB of the second potential point P2. Through this dynamic feedback regulation, VB is gradually made equal to VA.

[0059] Furthermore, the clamping unit 1200 ensures that the voltage VA at the first potential point P1 is equal to the voltage VB at the second potential point P2. Therefore, the currents in the two branches of the first triode Q1 and the second triode Q2 are the same, and the current in both branches is IQ. VA is the base-emitter voltage of the first triode Q1, and VB is the sum of the voltage drop across the third resistor R3 and the base-emitter voltage of the second triode Q2. Therefore, the voltage across the third resistor R3 is the difference between the base-emitter voltages of the first triode Q1 and the second triode Q2. The ratio of the emitter areas of the first triode Q1 and the second triode Q2 is 1:N. Then, the bandgap reference voltage Vref can be expressed as:

[0060]

[0061] where T represents the absolute temperature, I Q represents the collector currents of the first triode Q1 and the second triode Q2, I S represents the saturation current of the triode, R02 represents the resistance values of the first resistor and the second resistor, R01 represents the resistance value of the third resistor, N represents the ratio of the emitter area of the second triode Q2 to that of the first triode Q1, and k and q represent set values.

[0062] In this embodiment, by reasonably selecting the values of R01 and R02, the bandgap reference voltage Vref can be made a voltage independent of temperature.

[0063] The present disclosure also provides a chip, including the reference voltage source 1000 described in the foregoing embodiment.

[0064] This chip can be, for example, a high-precision power management chip, a high-precision analog-to-digital / digital-to-analog conversion chip, a memory chip, etc.

[0065] The present invention can be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0066] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example—but not limited to—an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punch card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer-readable storage medium as used herein is not construed as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0067] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include a copper transmission cable, an optical fiber transmission, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0068] The computer program instructions for carrying out the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine - related instructions, microcode, firmware instructions, state - setting data, or source code or object code written in any combination of one or more programming languages, including object - oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer - readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand - alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer - readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field - programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer - readable program instructions to implement various aspects of the present invention.

[0069] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer - readable program instructions.

[0070] These computer - readable program instructions can be provided to a processor of a general - purpose computer, a special - purpose computer, or other programmable data - processing apparatus to produce a machine, such that the instructions, when executed by the processor of the computer or other programmable data - processing apparatus, create a means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer - readable program instructions can also be stored in a computer - readable storage medium, which causes a computer, a programmable data - processing apparatus, and / or other devices to operate in a particular manner, so that the computer - readable medium storing the instructions comprises a manufacture, which includes instructions for implementing various aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0071] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, causing a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process such that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0072] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a segment of code, or a portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions. As will be apparent to those of ordinary skill in the art, implementations using hardware, implementations using software, and implementations using a combination of software and hardware are equivalent.

[0073] The embodiments of the present invention have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the market, or to enable other ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present invention is defined by the appended claims.

Claims

1. A reference voltage source, characterized in that: It includes a bandgap reference unit and a clamping unit, wherein the clamping unit includes a differential amplifier and a self-biasing circuit; The self-bias circuit is used to provide a bias current for the differential amplifier so as to put the differential amplifier into a working state; The differential amplifier is used to provide a feedback signal to the bandgap reference unit so that the bandgap reference unit generates a bandgap reference voltage; Wherein, the self-bias circuit is multiplexed with the output stage of the differential amplifier.

2. The reference voltage source according to claim 1, characterized in that: The reference voltage source further includes a startup unit, which is used to provide a startup current for the self-bias circuit when the reference voltage source is powered on, so as to put the self-bias circuit into a working state.

3. The reference voltage source according to claim 2, characterized in that: The startup unit is further configured to stop providing the startup current to the self-bias circuit after the self-bias circuit is started.

4. The reference voltage source according to claim 3, characterized in that: The startup unit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube. The first MOS tube and the second MOS tube are connected in series between the power supply terminal and the ground terminal of the reference voltage source, the third MOS tube and the fourth MOS tube are connected in series between the power supply terminal and the ground terminal, the gate of the second MOS tube is connected to the gate of the third MOS tube and the drain of the first MOS tube, the gate of the first MOS tube is connected to the power supply terminal, the potential point between the third MOS tube and the fourth MOS tube is connected to the gate of the fifth MOS tube, the gate of the fourth MOS tube is connected to the output terminal of the self-bias circuit, and the fifth MOS tube is connected between the ground terminal and the input terminal of the self-bias circuit.

5. The reference voltage source according to claim 4, characterized in that: The width-to-length ratio of the fourth MOS tube is greater than the width-to-length ratio of the third MOS tube.

6. The reference voltage source according to claim 1, characterized in that: The bandgap reference unit includes a sixth MOS transistor, a seventh MOS transistor, a first triode, a second triode, a first resistor, a second resistor, a third resistor, and a reference output terminal for outputting the bandgap reference voltage. The sixth MOS transistor and the seventh MOS transistor are connected in series between the power supply terminal of the reference voltage source and the reference output terminal. The gate of the sixth MOS transistor is connected to the first output terminal of the differential amplifier, and the gate of the seventh MOS transistor is connected to the second output terminal of the differential amplifier. The first resistor is connected between a first potential point and the reference output terminal, the first triode is connected between the first potential point and the ground terminal of the reference voltage source, the second resistor is connected between the second potential point and the reference output terminal, the third resistor is connected between the second potential point and the emitter of the second triode, the collector of the second triode is connected to the ground terminal, and the base of the first triode and the base of the second triode are both connected to the ground terminal.

7. The reference voltage source according to claim 6, characterized in that: The self-bias circuit includes a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube and a fourth resistor. The sixteenth MOS tube, the seventeenth MOS tube, the fourth resistor, the nineteenth MOS tube and the twenty-first MOS tube are connected in series between the power supply terminal and the ground terminal. The eighteenth MOS tube, the twenty-th MOS tube and the twenty-second MOS tube are connected in series between the power supply terminal and the ground terminal. The gate of the seventeenth MOS tube is connected to the gate of the eighteenth MOS tube and the drain of the eighteenth MOS tube as the output terminal of the self-bias circuit, the gate of the nineteenth MOS tube is connected to the gate of the twentieth MOS tube and the drain of the seventeenth MOS tube, and the gate of the twenty-first MOS tube is connected to the gate of the twenty-second MOS tube and the drain of the nineteenth MOS tube as the input terminal of the self-bias circuit.

8. The reference voltage source according to claim 7, characterized in that: The gate of the twenty-first MOS tube is multiplexed as the first output terminal of the differential amplifier for outputting a feedback signal and is connected to the gate of the sixth MOS tube. The gate of the nineteenth MOS tube is multiplexed as the second output terminal of the differential amplifier for outputting another feedback signal and is connected to the gate of the seventh MOS tube.

9. The reference voltage source according to claim 8, characterized in that: The differential amplifier further includes an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, and a fifteenth MOS tube. The eighth MOS tube and the ninth MOS tube are connected in series between the power supply terminal and the source of the tenth MOS tube, the twelfth MOS tube and the fourteenth MOS tube are connected in series between the drain of the tenth MOS tube and the ground terminal, the source of the eleventh MOS tube is connected to the source of the tenth MOS tube, the thirteenth MOS tube and the fifteenth MOS tube are connected in series between the drain of the eleventh MOS tube and the ground terminal, the gate of the eighth MOS tube is connected to the gate of the twenty-first MOS tube, the gate of the ninth MOS tube is connected to the gate of the nineteenth MOS tube, the gate of the tenth MOS tube is connected to the first potential point, the gate of the eleventh MOS tube is connected to the second potential point, the gate of the twelfth MOS tube and the gate of the thirteenth MOS tube are both connected to the gate of the seventeenth MOS tube, and the gate of the fourteenth MOS tube and the gate of the fifteenth MOS tube are both connected to the drain of the tenth MOS tube.

10. A chip, characterized in that: The invention comprises a reference voltage source as claimed in any one of claims 1 to 9.

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