Dynamic binary translation method and system for software pipeline codes

Abstract

The invention provides a dynamic binary translation method and system for software pipeline codes, and the method comprises the steps: obtaining an original guest code, and translating the guest code line by line according to a first translation mode; after processing in the first translation mode is completed, whether circulation is ended or not is judged on the basis of a circulation counter after execution is completed, and if the circulation is not ended, the guest code is translated row by row according to a second translation mode; after the processing in the second translation mode is completed, when the loop is ended, judging whether to translate the guest code row by row according to a third translation mode based on an outer loop judgment value in the loop processing identifier; and in the processing process of the third translation mode, constructing a corresponding relationship between the outer loop code and the inner loop code in the same period, sequentially translating the outer loop code and the inner loop code according to a period sequence, ending the outer loop translation when an end identifier of the outer loop is recognized, and ending the translation when a loop end identifier is recognized.

Description

Technical Field

[0001] The present invention relates to the technical field of dynamic binary translation, and particularly to a method and system for dynamically translating software pipelined code into binary code. Background Art

[0002] Instruction Set Architecture (ISA) emulation technology uses software to simulate the execution of a real CPU, enabling us to run binary programs of one ISA on a machine with another ISA. This technology can assist software developers in software development and testing without a real machine, avoiding extended development cycles due to hardware limitations, and can also help hardware developers verify some new hardware features to reduce hardware development costs.

[0003] Dynamic Binary Translation (DBT) is a typical ISA emulation technology. Given a binary program for a client, DBT technology translates the client instructions in the program into host instructions in units of basic blocks, traces, or regions and runs them on the host. Compared with instruction set emulation technology based on interpretation execution, DBT technology provides higher performance for the emulator.

[0004] Very Long Instruction Word (VLIW) architecture is a CPU architecture that can execute multiple instructions in parallel in one cycle. Different from other architectures, VLIW architecture relies on the compiler (rather than hardware) to exploit instruction-level parallelism and resolve data conflicts in the instruction pipeline. This architecture significantly reduces the complexity of processor design and also reduces the power consumption of the processor. Therefore, VLIW architecture, such as the C6X series of Texas Instruments, is commonly used in scenarios that require high-performance processing in the embedded field.

[0005] Software pipelining is commonly used to optimize loop code structures on VLIW architectures. Software pipelining takes advantage of the fact that multiple instructions can be executed in parallel in VLIW architectures, changing the serial execution of multiple iterations of a loop to parallel execution, thereby improving the execution efficiency of the loop.

[0006] Existing technologies can solve data conflicts generated when using DBT technology to translate VLIW code, but their algorithms are only applicable to the emulation of ISAs without software pipeline special instructions, such as the TI C62X and C67X series. For ISAs with software pipeline special instructions such as TI C64X+ and C66X, due to complex mechanisms such as instruction reordering and instruction overlap during the execution of software pipelined code, the original algorithms are not applicable. Summary of the Invention

[0007] In view of this, an embodiment of the present invention provides a dynamic binary translation method for software pipelined code to eliminate or improve one or more defects existing in the prior art.

[0008] One aspect of the present invention provides a dynamic binary translation method for software pipelined code, and the steps of the method include:

[0009] Obtain and translate the original guest code. If a loop processing identifier is recognized, translate the guest code line by line according to the first translation mode, and end the translation when the loop end identifier is recognized;

[0010] After the processing in the first translation mode is completed, execute the translation block generated in the first translation mode. When the execution is completed, determine whether the loop ends based on the loop counter. If it does not end, translate the guest code line by line again according to the second translation mode, and end the translation when the loop end identifier is recognized;

[0011] After the processing in the second translation mode is completed, execute the translation block generated in the second translation mode. When the execution is completed, determine whether the loop ends based on the loop counter. When the loop ends, determine whether to translate the guest code line by line according to the third translation mode based on the determination value of the outer loop in the loop processing identifier;

[0012] During the processing in the third translation mode, establish a corresponding relationship between the outer loop code and the inner loop code in the same cycle, and translate the outer loop code and the inner loop code in sequence according to the cycle order. End the outer loop translation when the end identifier of the outer loop is recognized, and end the translation when the loop end identifier is recognized.

[0013] Adopting the above solution, on the one hand, the guest code is translated line by line in this solution, changing the originally parallel loop iterations to serial execution, and solving the problem that the runtime values cannot be obtained during the translation stage and thus the instruction reordering phenomenon cannot be simulated; on the other hand, through three different translation modes, the instruction masking and instruction overlapping phenomena during the execution of the software pipelined code are simulated. In the second translation mode, the masked instructions are skipped, simulating the instruction masking situation in the software pipelined code. In the third translation mode, a corresponding relationship is established between the outer loop code and the inner loop code in the same cycle, which can effectively solve the situations of instruction overlapping and instruction masking.

[0014] In some embodiments of the present invention, the processing of translating the guest code line by line again according to the second translation mode further includes:

[0015] Identify the masked instructions in the guest code, and determine the target instructions masked by the masked instructions in the instruction sequence executed in the same cycle as the masked instructions;

[0016] Skip the translation of the target instruction masked by this masking instruction during the translation process.

[0017] In some embodiments of the present invention, in the step of obtaining and translating the original guest code, if a loop processing identifier is recognized, record the predicate of the loop processing identifier as the outer loop determination value. If the loop processing identifier has no predicate, the outer loop determination value is a null value.

[0018] In some embodiments of the present invention, in the step of determining whether the loop ends based on the loop counter, when determining that one loop ends, obtain the count value of the loop counter. If the count value is 0, determine that the loop ends; if the count value is not 0, subtract 1 from the count value and start a new loop.

[0019] In some embodiments of the present invention, in the step of translating the guest code line by line again according to the second translation mode and ending the translation when the loop end identifier is recognized, when ending the translation, determine whether the outer loop determination value is a null value. If it is a null value, no determination statement for the outer loop determination value will be generated, and the third translation mode will not be entered.

[0020] In the step of determining whether to translate the guest code line by line according to the third translation mode based on the outer loop determination value in the loop processing identifier, the determination statement generated in the second translation mode determines whether the outer loop determination value is 0. If it is not 0, translate the guest code line by line in an overlapping and aligned manner according to the third translation mode.

[0021] In some embodiments of the present invention, in the step of establishing the corresponding relationship between the outer loop code and the inner loop code in the same cycle, set the outer loop code and the inner loop code in the same cycle on the same line, arrange each line in the order of the cycle, and use the outer loop code and the inner loop code as two columns respectively to obtain the table to be translated.

[0022] In some embodiments of the present invention, in the step of sequentially translating the outer loop code and the inner loop code in the order of the cycle, perform sequential translation of each line of the table to be translated. In the translation of each line, translate the outer loop code first and then the inner loop code.

[0023] In some embodiments of the present invention, the process of sequentially translating each line of the table to be translated further includes:

[0024] Identify the masking instructions in each line and determine the target instructions masked in the line where the masking instructions are located;

[0025] Skip the translation of the masked target instructions in the inner loop.

[0026] In some embodiments of the present invention, the end identifier of the outer loop is the end point of the delay slot of the conditional jump instruction in the outer loop. The predicate of this jump instruction is the same as the predicate of the loop processing identifier, and the jump target is the start address of the outer loop. During the processing of the third translation mode, the jump function of this jump instruction is ignored, and only its delay slot is obtained, and the end point of the delay slot is used as the end identifier of the outer loop.

[0027] The second aspect of the present invention also provides a dynamic binary translation system for software pipelined code. The system includes a computer device, the computer device includes a processor and a memory, the memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the system implements the steps implemented by the method described above.

[0028] The third aspect of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps implemented by the foregoing dynamic binary translation method for software pipelined code.

[0029] The additional advantages, objectives, and features of the present invention will be partially described below, and will become partially apparent to those of ordinary skill in the art after studying the following text, or can be learned from the practice of the present invention. The objectives and other advantages of the present invention can be pointed out and obtained specifically in the specification and the drawings.

[0030] Those skilled in the art will understand that the objectives and advantages that can be achieved by the present invention are not limited to the above specifically described, and the above and other objectives that the present invention can achieve will be more clearly understood according to the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of this application, and do not constitute a limitation to the present invention.

[0032] Figure 1 It is a schematic diagram of an embodiment of the dynamic binary translation method for software pipelined code of the present invention;

[0033] Figure 2 It is a schematic diagram of the processing architecture of the dynamic binary translation method for software pipelined code of the present invention;

[0034] Figure 3 It is a schematic diagram of the translation processing of three translation modes of the dynamic binary translation method for software pipelined code of the present invention;

[0035] Figure 4 This is a schematic diagram showing the processing procedure of the third translation mode of the dynamic binary translation method for the software pipelining code of the present invention. Detailed implementation manners

[0036] To make the objectives, technical solutions and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the implementation manners and the accompanying drawings. Herein, the illustrative implementation manners of the present invention and their descriptions are used to explain the present invention, but not to limit the present invention.

[0037] Herein, it should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only the structures and / or processing steps closely related to the solution according to the present invention are shown in the drawings, while other details less relevant to the present invention are omitted.

[0038] Introduction to the prior art:

[0039] Different from other architectures, the very long instruction word architecture has three remarkable characteristics:

[0040] 1. Instruction parallelism is explicitly manifested in the binary code;

[0041] 2. The compiler or the assembly programmer needs to explicitly rearrange the instructions or insert NOP instructions to resolve possible data conflicts, while in other architectures, these data conflicts are resolved by the hardware;

[0042] 3. There is a delay in the jump instruction, and the execution of other instructions is not affected during the delay period of the jump instruction.

[0043] These characteristics result in a large number of data conflicts when using the DBT technology for instruction translation. The prior art resolves the data conflicts brought about by instruction parallelism and instruction delay through a register copy scheduling algorithm.

[0044] The original algorithm first generates multiple copies for each register, and only the value of the current copy is the value of the register in the current cycle. If the instruction in the current cycle needs to read the value of a certain register, the value of the current copy of that register should be read. Initially, the current copy is the 0th copy.

[0045] When translating each instruction, the original algorithm allocates an idle copy for the destination register of the instruction, stores the calculation result of the instruction in the idle copy, and records the delay of the instruction at the same time. At the end of each EP translation, the original algorithm updates the register copies with the number of cycles consumed by the current EP. If the delay of a certain copy expires, that copy is taken as the current copy.

[0046] In a DBT-based emulator, the TBs should be independent of each other. That is, we should not assume the predecessor and successor relationships between TBs, which can ensure a high code cache hit rate and avoid repeated translation.

[0047] To ensure the independence of TBs, the original algorithm proposed to return to the canonical state at the end of each TB, that is, copy the values of all current copies to the copy No. 0. In this way, when translating the next TB, there is no need to consider which copy is the current copy at the end of the previous TB, but directly use copy No. 0 as the current copy.

[0048] Store and restore the state of unexpired instructions

[0049] At the end of the current TB, there may still be some unexpired instructions. In the original algorithm, a function call instruction is generated for each unexpired instruction, and the function name is save_context, which is used to save the calculation results of unexpired instructions and the remaining delay cycles.

[0050] Then, function call instructions with the function name restore_context are generated at the end of each of the first several EPs of the TB, which are used to update the delay cycles saved at the end of the previous TB. If a certain delay cycle count is reduced to 0, it means that the unexpired instruction at the end of the previous TB has expired. Therefore, the calculation result of the instruction is restored to the corresponding register copy. If the value restored by the restore_context function is the program counter (PC), the execution of the current TB ends immediately.

[0051] Disadvantages of the prior art

[0052] The prior art can solve the data conflicts generated by translating VLIW code using DBT technology, but its algorithm is only applicable to the simulation of instruction set architectures without software pipeline special instructions, such as TI C62X and C67X series. For instruction set architectures with software pipeline special instructions such as TI C64X+ and C66X, due to the complex mechanisms such as instruction rearrangement, instruction overlap, and instruction masking during the execution of software pipeline code, the original algorithm is not applicable.

[0053] In the specific implementation process, software pipeline is commonly used to optimize loop code structures on very long instruction word architectures. The software pipeline takes advantage of the feature that multiple instructions can be executed in parallel in a very long instruction word architecture, changing the serial execution of multiple iterations of a loop to parallel execution, thereby improving the execution efficiency of the loop. The TI C62X and C67X series do not add hardware support for software pipeline, but developers or compilers can achieve the effect of software pipeline by carefully arranging instructions, and this kind of software pipeline code can be correctly executed through the original algorithm.

[0054] In contrast, the TI C64X+ and C66X series add dedicated hardware (loopbuffer) for software pipeline, and also add instructions dedicated to software pipeline in the instruction set, including SPLOOP(D / W) instruction, SPKERNEL(R) instruction, and SPMASK(R) instruction. These dedicated instructions simplify the work of developers and compilers, and also improve the readability of assembly code to a certain extent, but they are still not as intuitive as non-software-pipelined loop code.

[0055] Different from non-software-pipelined loops, there are no explicit conditional jump instructions and operations to modify the loop counter in software pipeline loop code. In addition, the additional hardware and instructions break the limitation that the CPU can only read instructions from memory, enabling the CPU to execute some or all of the instructions in the loop body in parallel in each cycle. During the translation stage, it is difficult to directly generate an instruction stream from the assembly code because the number of iterations of the loop is usually a runtime value and cannot be determined during translation, so it is impossible to know how many cycles of instructions should be generated, nor can it be known how many instructions in the loop body are executed in parallel in each cycle.

[0056] As Figure 1 、 2 shown in FIG. 3, the present invention proposes a dynamic binary translation method for software pipeline code, and the steps of this method include:

[0057] Step S100, obtaining and translating the original guest code. If a loop processing identifier is recognized, the guest code is translated line by line according to the first translation mode, and the translation ends when a loop end identifier is recognized;

[0058] In the specific implementation process, this solution uses a DBT system (such as QEMU) to translate and execute very long instruction word code.

[0059] The loop processing identifier can be the SPLOOP instruction, the SPLOOPW instruction, and the SPLOOPD instruction. When the SPLOOP instruction is encountered, the starting address of the next execution packet is recorded and the first translation mode is entered starting from the next execution packet. An execution packet refers to an execution sequence composed of instructions that need to be executed in parallel in the current cycle. In the assembly code, if there is a double vertical line at the beginning of the line where the current instruction is located, it means that the current instruction and the previous instruction are in the same execution packet;

[0060] The loop end identifier can be the SPKERNEL instruction. When the SPKERNEL instruction is encountered, two operations are added at the end of the execution packet containing the SPKERNEL instruction in this solution: 1. The operation of decrementing the count value of the loop counter (ILC); 2. The conditional jump operation. When the count value is greater than 0, jump to the starting address of the previously recorded loop body and enter the second translation mode.

[0061] For the software pipelined code starting with the SPLOOPW instruction, this solution uses a similar processing method, except that the loop termination condition is changed to the predicate condition of the SPLOOPW instruction. For the software pipelined code starting with the SPLOOPD instruction, this solution pre-adds the count value of the ILC according to the parameters of the SPLOOPD instruction.

[0062] Step S200, after the processing in the first translation mode is completed, execute the translation block generated in the first translation mode. When the execution is completed, determine whether the loop ends based on the loop counter. If it does not end, translate the guest code line by line again according to the second translation mode, and end the translation when the loop end identifier is recognized;

[0063] Step S300, after the processing in the second translation mode is completed, execute the translation block generated in the second translation mode. When the execution is completed, determine whether the loop ends based on the loop counter. When the loop ends, determine whether to translate the guest code line by line according to the third translation mode based on the outer loop determination value in the loop processing identifier;

[0064] Step S400, during the processing in the third translation mode, establish the corresponding relationship between the outer loop code and the inner loop code in the same cycle, and translate the outer loop code and the inner loop code in sequence according to the cycle order. End the outer loop translation when the outer loop end identifier is recognized, and end the translation when the loop end identifier is recognized.

[0065] With the above solution, on the one hand, the guest code is translated line by line, changing the originally parallel loop iterations to serial execution, which solves the problem that the runtime values cannot be obtained during the translation stage, thus unable to simulate instruction reordering. On the other hand, through three different translation modes, the instruction masking and instruction overlapping phenomena during the execution of software pipelined code are simulated. In the second translation mode, the masked instructions are skipped, simulating the instruction masking situation in software pipelined code. In the third translation mode, a corresponding relationship is constructed for the outer loop code and the inner loop code in the same cycle, which can effectively solve the instruction overlapping situation.

[0066] In some embodiments of the present invention, the process of re-translating the guest code line by line according to the second translation mode further includes:

[0067] Identifying the masked instructions in the guest code and determining the target instructions masked by the masked instructions in the instruction sequence executed in the same cycle as the masked instructions;

[0068] Skipping the translation of the target instructions masked by the masked instructions during the translation process.

[0069] In the specific implementation process, the masked instruction can be the SPMASK instruction, and the SPMASK instruction is used to mask specific execution units. If an instruction is in the loop buffer and is assigned to a masked execution unit, then the instruction will be ignored. The masked instructions are generally used for initializing variables in the loop. Regardless of the number of loop iterations, these instructions will only be executed once during the entire execution of the loop, that is, they will be executed when initially read from memory and will not be executed again in subsequent iterations.

[0070] To implement such an instruction masking function, this solution generates multiple different translated codes for the same segment of guest code and uses a state variable (abbreviated as state) to distinguish these generated translated codes, as Figure 3 shown. When the state variable is 0, we normally translate all instructions in the loop body, including the masked instructions; when the state variable is 1, all masked instructions are ignored.

[0071] As Figure 3 shown, initially, the value of the state variable is 0. This solution translates all instructions in the loop body, including the masked instructions, and generates the translation block TB0. Then, TB0 is executed to complete the first iteration of the loop, and the loop termination condition is checked at the end of TB0. If the condition is not satisfied, this solution sets the state variable to 1 and jumps back to the start of the loop.

[0072] Before the second iteration of the execution loop, this solution re-translates this code, ignoring the masked instructions during the translation process, and generates the translation block TB1. At the end of TB1, this solution checks the loop termination condition again. If the condition is still not met, this solution continues to set the status variable to 1 and jumps back to the start of the loop; otherwise, we reset the status variable to 0 and exit the loop.

[0073] In the specific implementation process, the status variable being 0 corresponds to the first translation mode, the status variable being 1 corresponds to the second translation mode, and the status variable being 2 corresponds to the third translation mode.

[0074] In some embodiments of the present invention, in the step of obtaining and translating the original guest code, if a loop processing identifier is recognized, the predicate of the loop processing identifier is recorded as the outer loop determination value. If the loop processing identifier has no predicate, the outer loop determination value is a null value.

[0075] In some embodiments of the present invention, in the step of determining whether the loop ends based on the loop counter when determining that one loop ends, when determining that one loop ends, the count value of the loop counter is obtained. If the count value is 0, it is determined that the loop ends; if the count value is not 0, the count value is decremented by 1, and another loop starts.

[0076] In the step of re-translating the guest code line by line according to the second translation mode and ending the translation when a loop end identifier is recognized, when ending the translation, it is determined whether the outer loop determination value is a null value. If it is a null value, no determination statement for the outer loop determination value is generated, and the third translation mode is not entered.

[0077] In some embodiments of the present invention, in the step of determining whether to translate the guest code line by line according to the third translation mode based on the outer loop determination value in the loop processing identifier, the determination statement generated in the second translation mode determines whether the outer loop determination value is 0. If it is not 0, the guest code is translated line by line with overlapping and alignment according to the third translation mode.

[0078] In some embodiments of the present invention, in the step of constructing a corresponding relationship between the outer loop code and the inner loop code in the same cycle, the outer loop code and the inner loop code in the same cycle are set on the same line, and are arranged in sequence for each line based on the order of the cycles. The outer loop code and the inner loop code are used as two columns respectively to obtain the table to be translated.

[0079] In some embodiments of the present invention, the process of sequentially translating each line of the table to be translated further includes:

[0080] Identify the masking instructions in each line and determine the target instructions masked in the line where the masking instruction is located;

[0081] Skip the translation of the target instructions masked in the inner loop.

[0082] In some embodiments of the present invention, in the step of sequentially translating the outer loop code and the inner loop code in cycle order, the table to be translated is sequentially translated line by line. In the translation of each line, the translation is performed in the order of the outer loop code first and then the inner loop code.

[0083] In some embodiments of the present invention, the end identifier of the outer loop is the end point of the delay slot of the conditional jump instruction in the outer loop. The predicate of this jump instruction is the same as the predicate of the loop processing identifier, and the jump target is the start address of the outer loop. During the processing of the third translation mode, the jump function of this jump instruction is ignored, and only its delay slot is obtained, and the end point of the delay slot is used as the end identifier of the outer loop.

[0084] In the specific implementation process, the SPLOOP series of instructions support single-level nested loops. In this solution, the part between the SPLOOP instruction and the SPKERNEL(R) instruction is called the inner loop, and the part after the SPKERNEL(R) instruction is called the outer loop. In this solution, a single execution of the inner loop instruction sequence is called one iteration of the inner loop, and multiple iterations of the inner loop until the loop terminates is called one overall iteration of the inner loop.

[0085] On the hardware chip, not only is the inner loop pipelined, but the outer loop also becomes part of the pipeline and overlaps with the execution of the inner loop.

[0086] The function of the outer loop includes initializing the variables of the inner loop and completing part of the functions of the first iteration of the inner loop. Therefore, the inner loop and the outer loop cannot be executed separately in series, otherwise the part of the functions of the inner loop completed in the outer loop will be overwritten by the inner loop. The processing method of the nested software pipelined loop in this solution is as follows: when the inner loop needs to be reloaded, this solution overlaps the first iteration of the inner loop with the outer loop and executes them in parallel, and then the subsequent iterations of the inner loop are executed serially with the first iteration.

[0087] Specifically, when the first overall iteration of the inner loop ends, if the condition for reloading the inner loop is met, this solution sets the status variable to 2, saves the current program counter (PC) value, and changes the PC to the start address of the inner loop. After that, when it is detected that the status variable has changed, we re-translate this client code. As Figure 4 shown, this solution overlaps the instructions of the inner loop and the outer loop and aligns them according to the cycle, reads the instructions synchronously from the current PC value and the previously saved PC value and translates them, and finally generates the translation block TB2.

[0088] When the first iteration of the inner loop (i.e., TB0) finishes execution, if the inner loop termination condition is false, this solution sets the status variable to 1 and jumps back to the start address of the inner loop to start translating and executing TB1. If the termination condition is true, this solution checks the condition for reloading the inner loop. If the condition is true, this solution sets the status variable to 2 and jumps back to the start address of the inner loop to start translating and executing TB2. If the condition is false, indicating that the entire loop has ended, this solution sets the status variable to 0 and exits the loop.

[0089] The length of the overlapping outer loop must be shorter than that of the inner loop, as stipulated by the assembler. The boundary of the outer loop is specified by a conditional jump instruction in the outer loop, whose predicate is the same as the reloading condition of the inner loop, and the target address is the start address of the outer loop. The position where the delay of this jump instruction expires is the boundary of the outer loop.

[0090] Note that both the SPKERNELR instruction and the SPMASKR instruction can reload the inner loop in a nested loop, but only one of them can be used in a nested loop. If the SPMASKR is used, although the instructions between SPKERNEL and SPMASKR belong to the outer loop, only the instructions after SPMASKR need to be overlapped with the first iteration of the inner loop.

[0091] In addition, when the status variable is 2, if there is an SPMASK instruction in the current cycle (whether in the outer loop or in the inner loop), this solution will ignore the masked instructions in the inner loop and normally translate the masked instructions in the outer loop. Because when executed on hardware, the instructions in the inner loop in this iteration are all read from the loop buffer, while the instructions in the outer loop are read from memory.

[0092] There is a special case in software pipelining loops, that is, the initial value of the loop counter (ILC) is 0. If the loop counter is 0 when the inner loop is first executed, only the masked instructions in the inner loop are executed. If the ILC is set to 0 when reloading the inner loop, only the instructions in the outer loop are executed.

[0093] To handle the above situations, we add two values to the status variable (i.e., state = 3 or 4), corresponding to the above two situations respectively. During execution, when encountering the SPLOOP instruction, this solution checks the value of the ILC. If the ILC is 0, we set the status variable to 3 and end the execution of the current translation block. The next translation block starts translating from the next execution packet, only translating the masked instructions and skipping the unmasked instructions.

[0094] If the overloaded ILC is detected to be 0 when overloading the inner loop, we set the state variable to 4 and jump to the starting address of the inner loop. Then, the instruction sequences of the outer loop and the inner loop are overlapped for translation, and only the instructions of the outer loop are translated, skipping the instructions of the inner loop.

[0095] In summary, the loop body wrapped by SPLOOP and SPKERNEL in this solution is translated into a translation block (TB0). In the translation block, this solution only shows the guest instructions that will be actually translated later to highlight the role played by this solution during the translation process, rather than showing the long host instructions. Among them, the SPKERNEL instruction only serves to mark the end of the loop body, so it is removed in the translation block. Executing TB0 once completes one iteration of the loop. At the end of each iteration, if the loop termination condition is not met, the value of state is modified to 1, and it jumps back to the starting address of the loop to re-translate the loop body to generate a new translation block (TB1), and then execute TB1 to complete the next iteration. If the loop termination condition is met, the outer loop determination value is checked. If it is non-zero, the value of state is modified to 2, and it jumps back to the starting address of the loop. Then, the inner and outer loops are overlapped and aligned to generate a new translation block (TB2), and then execute TB2 to complete the next iteration of the loop.

[0096] Specifically, in the translation stage, when this solution encounters the SPLOOP instruction, this solution records the starting address of the next execution packet, that is, Figure 3 and 4 the address of the LDW instruction in, which is represented by START in the translation block. The execution packet refers to the execution sequence composed of instructions that need to be executed in parallel in the current cycle. In the assembly code, if there is a double vertical line at the beginning of the line where the current instruction is located, it means that the current instruction and the previous instruction are in the same execution packet. When encountering the SPKERNEL instruction, this solution adds two operations at the end of the execution packet containing this SPKERNEL instruction. These two operations are represented in pseudocode in the figure and can be mapped to the corresponding IR or host instructions in the actual DBT system: 1. The decrement operation of the loop counter (ILC), that is, ILC-- in the translation block in the above figure; 2. The conditional jump operation. When ILC is greater than 0, state is modified to 1 and it jumps to the starting address of the previously recorded loop body. If ILC is equal to 0, the outer loop determination value is judged, that is, the value of A1. If it is greater than 0, state is modified to 2 and it jumps to the starting address of the previously recorded loop body, that is, Figure 3 and 4 the conditional judgment statement in the translation block in. Finally, TB0 is generated.

[0097] For software pipelined code starting with the SPLOOPW instruction, this solution uses a similar processing method, except that the loop termination condition is changed to the predicate condition of the SPLOOPW instruction. For software pipelined code starting with the SPLOOPD instruction, this solution needs to pre-add the value of ILC according to the parameters of the SPLOOPD instruction. The guest code in this embodiment starts with the SPLOOP instruction, so it is not applicable to this case.

[0098] When state is 1, the inner loop is retranslated and the masked instructions are skipped. In this embodiment, there is no SPMASK instruction in the inner loop of the guest code, so the generated TB1 and TB0 are exactly the same.

[0099] When state is 2, as Figure 4 shown, the outer loop and the inner loop are overlapped and aligned by cycle. After alignment, taking the cycle as the unit, the outer loop and the inner loop are alternately translated in the order of translating the outer loop first and then the inner loop. Moreover, under the action of the SPMASK instruction in the outer loop, the translation of the LDW instruction in the inner loop is skipped. In addition, the conditional jump instruction in the outer loop does not actually perform a jump, and only the end point of its delay slot is used as the identifier for the end of the translation of the outer loop. Finally, TB2 is generated.

[0100] An embodiment of the present invention also provides a dynamic binary translation system for software pipelined code. The system includes a computer device, the computer device includes a processor and a memory, the memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the system implements the steps implemented by the method described above.

[0101] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps implemented by the aforementioned dynamic binary translation method for software pipelined code. The computer-readable storage medium may be a tangible storage medium, such as a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a floppy disk, a hard disk, a removable storage disk, a CD-ROM, or any other form of storage medium well known in the technical field.

[0102] Those of ordinary skill in the art should understand that the various exemplary components, systems, and methods described in connection with the embodiments disclosed herein can be implemented in hardware, software, or a combination of both. Specifically, whether to implement in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, etc. When implemented in software, the elements of the present invention are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave on a transmission medium or a communication link.

[0103] It should be clear that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order between steps after understanding the spirit of the present invention.

[0104] In the present invention, the features described and / or illustrated for one embodiment can be used in the same or a similar manner in one or more other embodiments, and / or combined with the features of other embodiments or replace the features of other embodiments.

[0105] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, various changes and variations can be made to the embodiments of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for dynamic binary translation of software pipeline code, characterized in that: The steps of the method include: Obtaining and translating the original guest code, if a loop processing mark is identified, translating the guest code line by line according to the first translation mode, and ending the translation when a loop end mark is identified; After the first translation mode processing is completed, executing the translation block generated in the first translation mode, determining whether the loop is finished based on the loop counter when the execution is completed, and if not finished, translating the guest code again line by line according to the second translation mode, and ending the translation when a loop end mark is identified; After the second translation mode processing is completed, executing the translation block generated in the second translation mode, determining whether the loop is finished based on the loop counter when the execution is completed, and when the loop is finished, determining whether to translate the guest code line by line according to the third translation mode based on the outer loop determination value in the loop processing identifier; During the processing of the third translation mode, a correspondence is established between the outer loop code and the inner loop code of the same cycle, and the outer loop code and the inner loop code are sequentially translated according to the cycle order. The outer loop translation is terminated when the end mark of the outer loop is recognized, and the translation is terminated when the loop end mark is recognized.

2. The method for dynamic binary translation of software pipeline code according to claim 1, characterized in that: The process of translating the guest code again line by line according to the second translation mode further includes: Identify a shielding instruction in the guest code, and determine a target instruction shielded by the shielding instruction in an instruction sequence executed in the same cycle as the shielding instruction; During the translation process, the translation of the target instruction masked by the mask instruction is skipped.

3. The method for dynamic binary translation of software pipeline code according to claim 1, characterized in that: In the step of obtaining and translating the original guest code, if a loop processing identifier is identified, the predicate of the loop processing identifier is recorded as the outer loop determination value. If the loop processing identifier has no predicate, the outer loop determination value is a null value.

4. The method for dynamic binary translation of software pipeline code according to claim 1, characterized in that: In the step of determining whether a loop is finished based on a loop counter, when determining that a loop is finished, the count value of the loop counter is obtained. If the count value is 0, the loop is determined to be finished; if the count value is not 0, the count value is reduced by 1 and another loop is started.

5. The method for dynamic binary translation of software pipeline code according to claim 1, characterized in that: In the step of translating the guest code again line by line according to the second translation mode and terminating the translation when a loop end mark is identified, determining whether the outer loop determination value is a null value when the translation ends, if it is a null value, no determination statement for the outer loop determination value is generated, and the third translation mode is not entered; In the step of determining whether to translate the guest code line by line according to the third translation mode based on the outer loop determination value in the loop processing identifier, a determination statement generated under the second translation mode determines whether the outer loop determination value is 0; if not, the guest code is overlapped and aligned and translated line by line according to the third translation mode.

6. The method for dynamic binary translation of software pipeline code according to any one of claims 1 to 5, characterized in that: In the step of establishing a corresponding relationship between the outer loop code and the inner loop code of the same period, the outer loop code and the inner loop code of the same period are set in the same row, and the rows are arranged sequentially based on the order of the period, and the outer loop code and the inner loop code are respectively used as two columns to obtain a table to be translated.

7. The method for dynamic binary translation of software pipeline code according to claim 6, characterized in that: In the step of sequentially translating the outer loop code and the inner loop code in a periodic order, the table to be translated is sequentially translated row by row, and in the translation of each row, the translation is performed in the order of first the outer loop code and then the inner loop code.

8. The method for dynamic binary translation of software pipeline code according to claim 7, characterized in that: The process of sequentially translating the table to be translated row by row also includes: Identify the masking instruction in each row, and determine the masked target instruction in the row where the masking instruction is located; Skip translation of masked target instructions in inner loops.

9. The method for dynamic binary translation of software pipeline code according to claim 1, characterized in that: The end marker of the outer loop is the end point of the delay slot of the conditional jump instruction in the outer loop, the predicate of the jump instruction is consistent with the predicate of the loop processing identifier, and the jump target is the starting address of the outer loop; during the third translation mode processing, the jump function of this jump instruction is ignored, only its delay slot is obtained, and the end point of the delay slot is used as the end marker of the outer loop.

10. A dynamic binary translation system for software pipeline code, characterized in that: The system includes a computer device, which includes a processor and a memory. The memory stores computer instructions. The processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the system implements the steps implemented by the method as described in any one of claims 1 to 9.

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