Deep learning synaptic device multi-dimensional performance prediction method based on neural network
Through the deep learning method based on neural network, the mapping relationship between synaptic device performance and influencing factors is learned, and the problem of high cost and long period of synaptic device performance prediction in the existing technology is solved, high-precision and rapid performance prediction are achieved, and the development of neuromorphic computing hardware is promoted.
Patent Information
- Application Number
- CN202510270869.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2025-06-10
AI Technical Summary
The prior art has high cost, long cycles, and high professional knowledge requirements in synaptic device performance prediction, making it difficult to achieve efficient and accurate performance prediction.
Using a deep learning method based on neural networks, a complex mapping relationship between device performance and influencing factors is learned through a large amount of experimental data, and a neural network model is constructed for synaptic device performance prediction.
It realizes high-precision prediction of synaptic device performance, significantly shortens the R&D cycle, and provides theoretical support for device design and optimization, promoting the development of neuromorphic computing hardware.
Smart Images
Figure CN120124561A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology, and further relates to artificial intelligence and semiconductor device simulation technology. Specifically, it is a multi-dimensional performance prediction method for deep learning synaptic devices based on neural networks, which can be used for the design and optimization of synaptic devices, significantly shortening the R & D cycle. Background Art
[0002] With the rapid development of artificial intelligence and neuromorphic computing, the traditional von Neumann architecture has gradually shown limitations in terms of energy efficiency and parallel computing capabilities. To break through this bottleneck, researchers have begun to explore brain-inspired computing systems based on synaptic devices. A synaptic device is an electronic device that mimics the behavior of biological synapses and can store and process information through changes in its conductance state. It has advantages such as low power consumption, high parallelism, and plasticity, and is considered a core component for building the next-generation neuromorphic computing hardware.
[0003] The performance of synaptic devices is affected by various factors, including material properties, device structure, manufacturing process, and working conditions, etc. The complex interaction of these factors makes the performance prediction of synaptic devices extremely challenging. Traditional experimental methods usually require a large number of trial-and-error processes, which are time-consuming and costly.
[0004] Currently, the prediction of synaptic device performance is usually completed by experimental tests or semiconductor simulation software. However, experimental tests require the preparation of a large number of synaptic devices under different design conditions, which requires a lot of manpower and material resources, and the trial-and-error cost is high. Compared with experimental tests, the cost of simulating synaptic devices under different design conditions through semiconductor simulation software to obtain corresponding performance indicators is reduced, but it requires high professional knowledge in this field and takes several days or weeks to build a complete model, and the time cycle for completing the prediction is relatively long. Summary of the Invention
[0005] The purpose of the present invention is to propose a multi-dimensional performance prediction method for deep learning synaptic devices based on neural networks in view of the above-mentioned deficiencies of the prior art, solving the problems of large input cost, long cycle, and high requirement for professional knowledge in the prior art. This method utilizes the powerful capabilities demonstrated by neural network models in complex system modeling and prediction, uses a large amount of experimental data, and learns the complex mapping relationship between device performance and its influencing factors through neural networks, thereby achieving efficient and accurate performance prediction. The present invention can achieve high-precision prediction of synaptic device performance, not only significantly shortening the R & D cycle, but also providing strong theoretical support for device design and optimization, thus promoting the development of neuromorphic computing hardware.
[0006] The technical solution for achieving the purpose of the present invention includes the following steps:
[0007] (1) Use computer-aided design TCAD simulation software to model synaptic devices, that is, construct simulated synaptic devices. By changing the design parameters of the simulated synaptic devices multiple times, obtain the performance indicators corresponding to different design parameters; take each design parameter and its corresponding performance indicator as a set of samples, and use all samples to form a sample set;
[0008] (2) Preprocess the data in the sample set and randomly divide it into a training set, a validation set, and a test set according to a certain proportion;
[0009] (3) Construct a deep learning neural network model for predicting the performance of synaptic devices;
[0010] (4) Use the training set and the validation set to train and validate the constructed deep learning neural network model to obtain a trained neural network model;
[0011] (5) Input the test set into the trained neural network model to check the prediction accuracy;
[0012] (6) Take the neural network model with high accuracy after verification as the final model, input the design parameters of the synaptic device into this model, and obtain the performance prediction result of the device.
[0013] Compared with the prior art, the present invention has the following advantages:
[0014] First, since the present invention uses the automatic feature extraction and high-efficiency computing ability of the neural network to predict the device performance of synaptic devices, there is no need to fabricate a large number of devices or perform modeling and simulation on the devices, enabling the performance indicators of synaptic devices to be obtained quickly and accurately, thereby significantly reducing the cost and time of device design and optimization.
[0015] Second, since the present invention adopts an end-to-end autonomous learning architecture based on the neural network, converting the traditional modular design that relies on professional knowledge into a data-driven global optimization problem, non-professionals can realize the characteristic modeling of synaptic devices without relying on microelectronics professional knowledge, thereby quickly and accurately predicting the key parameters of the devices, and significantly improving the design efficiency and reliability of the devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 is a schematic diagram of the neural network architecture built in the present invention;
[0017] Figure 2 is a schematic diagram of the electrolyte-gated synaptic device model constructed in Embodiment 3 of the present invention;
[0018] Figure 3 is a schematic diagram of the floating-gate synaptic device model constructed in Embodiment 4 of the present invention;
[0019] Figure 4It is a schematic diagram of the ferroelectric gate synaptic device model constructed in the fifth embodiment of the present invention; Specific embodiments
[0020] The following further describes the present invention in detail with reference to the drawings and embodiments.
[0021] Example 1: Refer to Figure 1 , the multi-dimensional performance prediction method for deep learning synaptic devices based on neural networks proposed by the present invention specifically includes the following steps:
[0022] Step 1) Use computer-aided design TCAD simulation software to model the synaptic device, that is, construct a simulated synaptic device. By changing the design parameters of the simulated synaptic device multiple times, obtain the performance indicators corresponding to different design parameters; Take each design parameter and its corresponding performance indicator as a group of samples, and use all samples to form a sample set. In this embodiment, the above performance indicators include on-off ratio, single-pulse power consumption, state retention time, and nonlinear factor. Other performance indicators of the synaptic device can also be adopted here; The above design parameters include channel layer thickness, electrolyte thickness, electrolyte solubility, and electrolyte ionic conductivity. Of course, other design parameters that can affect the performance of the synaptic device can also be used; The number of times of changing the design parameters of the simulated synaptic device is not less than 8 times, and preferably 10 times in this embodiment.
[0023] Step 2) Preprocess the sample set data and randomly divide it into a training set, a validation set, and a test set according to a certain proportion; The preprocessing operations performed in this step in this embodiment include standardizing the input data and normalizing the output data. The formulas are as follows:
[0024]
[0025]
[0026] Among them, Z represents the standardized value, x i is the i-th sample data, and λ and σ are the arithmetic mean and standard deviation of the data set respectively; x n represents the normalized value, x max and x min are the maximum and minimum values in the sample respectively.
[0027] Step 3) Construct a deep learning neural network model for predicting the performance of synaptic devices; a neural network with non-linear fitting ability and automatic feature extraction ability can be adopted here. In this embodiment, a convolutional neural network is preferably used to construct the deep learning neural network model. The model architecture sequentially includes an input layer, a feature mapping layer, a convolutional layer 1, a pooling layer 1, a convolutional layer 2, a pooling layer 2, a fully connected layer 1, a fully connected layer 2, and an output layer; the input features of the input layer are variables corresponding to the number of design parameters; the feature mapping layer is used to reshape multi-dimensional features and use them as convolutional inputs; the convolutional layer is used to extract local features from the data, and the pooling layer is used to compress the data output by the convolutional layer; the fully connected layer is used to integrate the extracted features and make a final prediction; the output layer uses neurons corresponding to the number of performance metrics to output the predicted performance metrics. The convolutional kernels of the above convolutional layer 1 and convolutional layer 2 are both 2×2, and the number of channels are 16 and 32 respectively; the pooling layer 1 and the pooling layer 2 adopt the maximum pooling method and the global average pooling method respectively; the fully connected layer 1 is used to map multi-dimensional features to a higher-dimensional space, and the fully connected layer 2 uses 32 neurons to achieve prediction.
[0028] Step 4) Use the training set and the validation set to train and validate the constructed deep learning neural network model to obtain a trained neural network model. The specific implementation steps are as follows:
[0029] (4a) Set the error function, optimization method, and initial learning rate of the deep learning neural network;
[0030] (4b) Use the design parameters as the network input and the corresponding performance metrics as the output;
[0031] (4c) Input the training set data into the deep learning neural network, calculate the loss function for each batch of training, and use backpropagation to optimize the network parameters;
[0032] (4d) After each training cycle, use the validation set to evaluate the performance of the model, calculate the loss value of the validation set, and determine whether to stop training early. If training is stopped early, save the model parameters with the smallest loss value in the validation set as the optimal parameters to obtain a trained neural network model; otherwise, train according to the preset number of training cycles until the preset number of cycles is reached to obtain a trained neural network model. Whether to stop training early is specifically judged in the following way: If the loss of the validation set remains stable for at least 10 consecutive training cycles, stop training early; otherwise, continue the training process.
[0033] Step 5) Input the test set into the trained neural network model to check the prediction accuracy;
[0034] Step 6) Take the neural network model with high accuracy after inspection as the final model. Here, the judgment criterion for the neural network model with high accuracy is that the model prediction accuracy is greater than 90%; input the design parameters of the synaptic device into this model to obtain the performance prediction result of the device.
[0035] Example 2: Refer to Figure 1 , the overall implementation steps of the prediction method proposed in this example are the same as those in Example 1. Now, specific examples are given for each step to further describe the implementation process of the present invention in detail:
[0036] First step, use TCAD to build a synaptic device simulation model. The built synaptic device model can adopt a floating-gate synaptic device, a ferroelectric-gate synaptic device, or an electrolyte-gated synaptic device.
[0037] The design conditions affecting the floating-gate synaptic device are: the selection of the floating-gate material (such as polysilicon, silicon nitride, etc.) affects the charge storage capacity and stability; the thickness and quality of the tunneling layer material (such as SiO 2 , high-k dielectric) affect the charge injection and retention characteristics; the distance between the floating gate and the channel affects the electric field distribution and charge tunneling efficiency; the geometric dimensions of the device (such as channel length, width) affect the conductance modulation range and power consumption; the amplitude and pulse width of the programming / erasing voltage affect the charge injection and erasing efficiency; the operating temperature may affect the charge retention characteristics and the long-term stability of the device.
[0038] The design conditions affecting the ferroelectric-gate synaptic device are: the selection of the ferroelectric material (such as HfO 2 , AlScN, etc.) affects the polarization switching speed and durability; the thickness and crystalline quality of the ferroelectric layer affect the polarization intensity and stability; the interface characteristics between the ferroelectric layer and the channel affect the modulation efficiency of the polarization field on the channel conductance; the deposition method and annealing process of the ferroelectric layer affect its crystalline quality and interface characteristics; the amplitude and pulse width of the polarization voltage affect the switching speed and accuracy of the polarization state.
[0039] The design conditions affecting the electrolyte-gated synaptic device are: the selection of the electrolyte material (such as solid electrolyte, ionic liquid) affects the ion mobility and stability; the carrier mobility and interface characteristics of the channel material (such as oxide semiconductor, two-dimensional material) affect the conductance modulation range; the inherent properties of the electrolyte such as crystallinity, solubility, and ionic conductivity; the geometric dimensions of the device (such as channel length, electrolyte thickness) affect the response speed and power consumption.
[0040] When using simulation to obtain the performance indicators of the synaptic device, corresponding simulation conditions should be set according to the required performance indicators, and then the data should be processed to obtain the corresponding performance indicators.
[0041] In the second step, the specific operation for preprocessing the sample set is to standardize the input data and normalize the output data; then divide the simulated I-V data set into an 80% training set, a 10% validation set, and a 10% test set.
[0042] In the third step, a convolutional neural network is used to predict the performance of the synaptic device. The input of the neural network is the design parameters of the synaptic device, and the output is the performance indicators of the synaptic device. The neural network model architecture used includes an input layer, a feature mapping layer, a convolutional layer 1, a pooling layer 1, a convolutional layer 2, a pooling layer 2, a fully connected layer 1, a fully connected layer 2, and an output layer; in this embodiment, it is preferably that the input features of the input layer are 4 variables, corresponding to 4 design parameters; the input layer uses a fully connected layer to map the 4-dimensional features to a higher-dimensional space to enhance the feature expression ability; the feature mapping layer reshapes 64 dimensions into the convolutional input; the convolutional kernel size of convolutional layer 1 is 2×2, the number of channels is 16, and the output is a 7×7 matrix; pooling layer 1 uses the maximum pooling method, and the output is a 3×3 matrix; the convolutional kernel size of convolutional layer 2 is 2×2, and the number of channels is 32; pooling layer 2 uses the global average pooling method, and the output is a 1×1 matrix; fully connected layer 2 uses 32 neurons; the output layer uses 4 neurons, corresponding to four performance indicators: on / off ratio, single-pulse power consumption, state retention time, and non-linearity factor.
[0043] In the fourth step, during the training process, the mean squared error (MSE) is used as the loss function to measure the difference between the current value in the hysteresis curve predicted by the model and the actual current value; the Adam optimizer is used to update the network parameters, and the learning rate is dynamically adjusted through an exponential decay strategy, with the initial learning rate set to 0.001.
[0044] After each training cycle ends, the validation set is used to evaluate the performance of the model, and the loss value of the validation set is calculated. If the loss of the validation set does not decrease significantly for several consecutive cycles, the training is stopped in advance to prevent overfitting. The model parameters with the smallest validation set loss are saved as the final trained model.
[0045] In the fifth step, the trained model is evaluated using the test set, and the loss value and prediction accuracy of the test set are calculated.
[0046] In the sixth step, the neural network model with the highest prediction accuracy is used as the final model, and the design parameters of the synaptic device are input into this model. After running, the performance prediction result of this device is obtained.
[0047] Example 3: Refer to Figure 2 , the overall implementation steps of the prediction method proposed in this embodiment are the same as those in Example 1 or 2. Now, the implementation process of using the present invention to predict the performance of the electrolyte-gated synaptic device is given:
[0048] Step 1: Use TCAD to build a simulation model of the electrolyte-gated synaptic device, as Figure 2 shown; and change the design parameters of the simulated electrolyte-gated synaptic device to obtain a data set.
[0049] Use TCAD to build a simulation model of the electrolyte-gated synaptic device. The constructed electrolyte-gated synaptic device model consists of a source electrode, a drain electrode, a gate electrode, an ionic liquid, and a channel layer. Define the source electrode, drain electrode, and gate electrode as Au, the ionic liquid as 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, and the channel layer uses MoO 3 .
[0050] Determine that the design parameters to be changed are the channel layer thickness, electrolyte thickness, electrolyte solubility, and electrolyte ionic conductivity. By continuously changing the channel layer thickness, electrolyte thickness, electrolyte solubility, and electrolyte ionic conductivity, the switching ratio, single-pulse power consumption, state retention time, and non-linearity factor of the corresponding synaptic device are obtained through simulation. The channel layer thickness is taken as 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm respectively; the electrolyte thickness is taken as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm respectively; the electrolyte solubility is taken as 0.5mol / L, 0.7mol / L, 0.9mol / L, 1.1mol / L, 1.3mol / L, 1.5mol / L, 1.7mol / L, 1.9mol / L, 2.1mol / L, 2.5mol / L respectively; the electrolyte ionic conductivity is taken as 1×10 -2 S / m, 2×10 -2 S / m, 3×10 - 2 S / m, 4×10 -2 S / m, 5×10 -2 S / m, 6×10 -2 S / m, 7×10 -2 S / m, 8×10 -2 S / m, 9×10 -2 S / m, 1×10 -1 S / m. Combine the design parameters to obtain a set of design conditions, such as: the channel layer thickness is 5nm, the electrolyte thickness is 20nm, the electrolyte solubility is 0.5mol / L, and the electrolyte ionic conductivity is 1×10 -2 S / m. Under each set of design conditions, use TCAD for simulation to obtain the switching ratio, single-pulse power consumption, state retention time, and non-linearity factor of the corresponding synaptic device.
[0051] Take the design parameters and the corresponding switching ratio, single-pulse power consumption, state holding time, and nonlinear factor as a set of samples.
[0052] Step 2: Preprocess the data in the collected sample set, and randomly divide the sample set data into a training set, a validation set, and a test set according to a ratio.
[0053] Before preprocessing the sample set, it is necessary to first perform a base-10 logarithmic operation on the switching ratio, single-pulse power consumption, and state holding time output in the data set, so as to reduce the difference in the order of magnitude between the data.
[0054] Use the normalization formula to normalize the input data of the channel layer thickness, electrolyte thickness, electrolyte solubility, and electrolyte ionic conductivity.
[0055] Use the normalization formula to normalize the output data of the switching ratio, single-pulse power consumption, state holding time, and nonlinear factor.
[0056] After processing, randomly divide the data set into an 80% training set, a 10% validation set, and a 10% test set.
[0057] Step 3: Construct a deep learning neural network model suitable for predicting the performance of synaptic devices, as Figure 4 shown.
[0058] Adopt a convolutional neural network to construct a deep learning neural network model suitable for predicting the performance of synaptic devices, including an input layer, a feature mapping layer, a convolutional layer 1, a pooling layer 1, a convolutional layer 2, a pooling layer 2, a fully connected layer, and an output layer.
[0059] The input features of the input layer are 4 variables, corresponding to the 4 design parameters of the channel layer thickness, electrolyte thickness, electrolyte solubility, and electrolyte ionic conductivity. The input layer uses a fully connected layer to map the 4D features to a higher-dimensional space to enhance the feature expression ability;
[0060] The feature mapping layer reshapes the 64 dimensions into a convolutional input;
[0061] The convolutional kernel size of convolutional layer 1 is 2×2, the number of channels is 16, and the output is a 7×7 matrix;
[0062] Pooling layer 1 adopts the maximum pooling method, and the output is a 3×3 matrix;
[0063] The convolutional kernel size of convolutional layer 2 is 2×2, and the number of channels is 32;
[0064] Pooling layer 2 adopts the global average pooling method, and the output is a 1×1 matrix;
[0065] The fully connected layer 2 uses 32 neurons;
[0066] The output layer uses 4 neurons, corresponding to four performance indicators: switching ratio, single-pulse power consumption, state retention time, and non-linearity factor.
[0067] Step 4: Use the training set and the validation set to train and validate the constructed deep learning neural network model to obtain a trained neural network model.
[0068] The mean squared error (MSE) is used as the loss function to measure the difference between the predicted current value and the actual current value of the model; the Adam optimizer is used to update the network parameters, and the learning rate is dynamically adjusted through an exponential decay strategy, with the initial learning rate set to 0.001.
[0069] After each training epoch, use the validation set to evaluate the performance of the model and calculate the loss value of the validation set. If the loss of the validation set does not decrease significantly for several consecutive epochs, stop training early to prevent overfitting. Save the model parameters with the minimum loss of the validation set as the final trained model.
[0070] Step 5: Input the test set into the trained neural network model to test its prediction accuracy.
[0071] Use the test set to evaluate the trained model and calculate the loss value and prediction accuracy of the test set.
[0072] Example 4: Refer to Figure 3 , the overall implementation steps of the prediction method proposed in this example are the same as those in Example 1 or 2. Now, the implementation process of using the present invention to predict the performance of a floating-gate synaptic device is given:
[0073] Step 1: Use TCAD to construct a simulation model of a floating-gate synaptic device, as shown in Figure 2 ; and change the design parameters of the simulated floating-gate synaptic device to obtain a data set.
[0074] Use TCAD to construct a simulation model of a floating-gate synaptic device. The constructed floating-gate synaptic device model consists of a source electrode, a drain electrode, a channel layer, a tunneling layer, a floating gate, an insulating layer, a bottom gate, and a substrate. It is defined that the source electrode, drain electrode, and gate are made of metal carbon nanotubes m-CNT, the channel layer is made of semiconductor carbon nanotubes s-CNT, the tunneling layer is made of Al 2 O 3 , the floating gate is made of MXene, the insulating layer is made of organic-inorganic hybrid polyimide-Al 2 O 3 (HPI), and the substrate is made of polyimide (PI).
[0075] The design parameters selected to be changed are the thickness of the floating gate, the thickness of the tunneling layer (the vertical distance from the floating gate to the channel layer), the thickness of the insulating layer, and the length of the channel layer. The switching ratio, single-pulse power consumption, state retention time, and non-linearity factor of the corresponding synaptic device are obtained through simulation. The thickness of the floating gate is taken as 3nm, 6nm, 9nm, 12nm, 15nm, 18nm, 21nm, 24nm, 27nm, 30nm respectively; the thickness of the tunneling layer is 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm respectively; the thickness of the insulating layer is taken as 2nm, 4nm, 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm respectively; the length of the channel layer is taken as 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2μm respectively. A set of design conditions is obtained by combining the design parameters, such as: the thickness of the floating gate is 3nm, the thickness of the tunneling layer is 1nm, the thickness of the insulating layer is 2nm, and the length of the channel layer is 0.2μm. Under each set of design conditions, TCAD is used for simulation to obtain the switching ratio, single-pulse power consumption, state retention time, and non-linearity factor of the corresponding synaptic device.
[0076] Take the design parameters and the corresponding switching ratio, single-pulse power consumption, state retention time, and non-linearity factor as a set of samples.
[0077] Step 2: Preprocess the data in the collected sample set, and randomly divide the sample set data into a training set, a validation set, and a test set according to a certain proportion.
[0078] Use the standardization formula to perform standardization processing on the input data, namely the thickness of the floating gate, the thickness of the tunneling layer, the thickness of the insulating layer, and the length of the channel layer.
[0079] Use the normalization formula to perform normalization processing on the output data, namely the switching ratio, single-pulse power consumption, state retention time, and non-linearity factor.
[0080] Randomly divide the data set into an 80% training set, a 10% validation set, and a 10% test set.
[0081] Step 3: Construct a deep learning neural network model suitable for predicting the performance of synaptic devices, as Figure 4 shown.
[0082] Adopt a convolutional neural network to construct a deep learning neural network model suitable for predicting the performance of synaptic devices, including an input layer, a feature mapping layer, a convolutional layer 1, a pooling layer 1, a convolutional layer 2, a pooling layer 2, a fully connected layer, and an output layer.
[0083] The input features of the input layer are 4 variables, corresponding to 4 design parameters: the thickness of the floating gate, the thickness of the tunneling layer, the thickness of the insulating layer, and the length of the channel layer. The input layer uses a fully connected layer to map the 4D features to a higher-dimensional space to enhance the feature expression ability;
[0084] The feature mapping layer reshapes the 64 dimensions into a convolutional input;
[0085] The convolutional kernel size of convolutional layer 1 is 2×2, the number of channels is 16, and the output is a 7×7 matrix;
[0086] Pooling layer 1 uses the maximum pooling method, and the output is a 3×3 matrix;
[0087] The convolutional kernel size of convolutional layer 2 is 2×2, and the number of channels is 32;
[0088] Pooling layer 2 uses the global average pooling method, and the output is a 1×1 matrix;
[0089] Fully connected layer 2 uses 32 neurons;
[0090] The output layer uses 4 neurons, corresponding to four performance indicators: the switching ratio, the single-pulse power consumption, the state retention time, and the non-linearity factor.
[0091] Step 4: Use the training set and the validation set to train and validate the constructed deep learning neural network model to obtain the trained neural network model.
[0092] The mean squared error (MSE) is used as the loss function to measure the difference between the predicted current value and the actual current value of the model; the Adam optimizer is used to update the network parameters, and the learning rate is dynamically adjusted through an exponential decay strategy. The initial learning rate is set to 0.001.
[0093] After each training epoch, use the validation set to evaluate the performance of the model and calculate the loss value of the validation set. If the loss of the validation set does not decrease significantly for several consecutive epochs, stop training early to prevent overfitting. Save the model parameters with the smallest validation set loss as the final trained model.
[0094] Step 5: Input the test set into the trained neural network model to test its prediction accuracy.
[0095] Use the test set to evaluate the trained model and calculate the loss value and prediction accuracy of the test set.
[0096] Example 5: Refer to Figure 4 , the overall implementation steps of the prediction method proposed in this example are the same as those in Example 1 or 2. Now, the implementation process of using the present invention to predict the performance of ferroelectric gate synaptic devices is given:
[0097] Step A: Use TCAD to build a simulation model of a ferroelectric gate synaptic device, as Figure 4 shown; and change the design parameters of the simulated ferroelectric gate synaptic device to obtain a dataset.
[0098] Use TCAD to build a simulation model of a ferroelectric gate synaptic device. The constructed ferroelectric gate synaptic device model consists of a source electrode, a drain electrode, a channel layer, a ferroelectric layer, a gate electrode, and a substrate. Define the source electrode and the drain electrode to use Pt / Ti, 3 and the gate electrode to use SrRuO 3 , the channel layer to use ZnO, and the ferroelectric layer to use Pb(Zr,Ti)O 3 .
[0099] Determine that the design parameters to be changed are the distance between the source electrode and the drain electrode, the thickness of the channel layer, the thickness of the ferroelectric layer, and the thickness of the gate electrode. Simulate to obtain the switching ratio, single-pulse power consumption, state retention time, and non-linearity factor of the corresponding synaptic device. The distances between the source electrode and the drain electrode are taken as 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 5.5μm, 6μm, 6.5μm, 7μm respectively; the thicknesses of the channel layer are 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm respectively; the thicknesses of the ferroelectric layer are taken as 3nm, 6nm, 9nm, 12nm, 15nm, 18nm, 21nm, 24nm, 27nm, 30nm respectively; the thicknesses of the gate electrode are taken as 2nm, 4nm, 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm respectively. Combine the design parameters to obtain a set of design conditions, such as: the distance between the source electrode and the drain electrode is 2μm, the thickness of the channel layer is 1nm, the thickness of the ferroelectric layer is 3nm, and the thickness of the gate electrode is 2nm. Under each set of design conditions, use TCAD to simulate to obtain the switching ratio, single-pulse power consumption, state retention time, and non-linearity factor of the corresponding synaptic device.
[0100] Take the design parameters and the corresponding switching ratio, single-pulse power consumption, state retention time, and non-linearity factor as a set of samples.
[0101] Step B: Preprocess the data of the collected sample set, and randomly divide the sample set data into a training set, a validation set, and a test set according to a ratio.
[0102] Use the standardization formula to perform standardization processing on the input data of the distance between the source electrode and the drain electrode, the thickness of the channel layer, the thickness of the ferroelectric layer, and the thickness of the gate electrode.
[0103] Use the normalization formula to perform normalization processing on the output data of the switching ratio, single-pulse power consumption, state retention time, and non-linearity factor.
[0104] Randomly divide the data set into an 80% training set, a 10% validation set, and a 10% test set.
[0105] Step C: Construct a deep learning neural network model suitable for predicting the performance of synaptic devices, as Figure 4 shown.
[0106] Use a convolutional neural network to construct a deep learning neural network model suitable for predicting the performance of synaptic devices, including an input layer, a feature mapping layer, a convolutional layer 1, a pooling layer 1, a convolutional layer 2, a pooling layer 2, a fully connected layer, and an output layer.
[0107] The input features of the input layer are 4 variables, corresponding to 4 design parameters: the distance between the source and the drain, the thickness of the channel layer, the thickness of the ferroelectric layer, and the thickness of the gate. The input layer uses a fully connected layer to map the 4-dimensional features to a higher-dimensional space to enhance the feature expression ability;
[0108] The feature mapping layer reshapes 64 dimensions into a convolutional input;
[0109] The convolution kernel size of convolutional layer 1 is 2×2, the number of channels is 16, and the output is a 7×7 matrix;
[0110] Pooling layer 1 uses the maximum pooling method, and the output is a 3×3 matrix;
[0111] The convolution kernel size of convolutional layer 2 is 2×2, and the number of channels is 32;
[0112] Pooling layer 2 uses the global average pooling method, and the output is a 1×1 matrix;
[0113] The fully connected layer 2 uses 32 neurons;
[0114] The output layer uses 4 neurons, corresponding to four performance indicators: on-off ratio, single-pulse power consumption, state retention time, and non-linearity factor.
[0115] Step D: Use the training set and the validation set to train and validate the constructed deep learning neural network model to obtain a trained neural network model.
[0116] Use the mean squared error (MSE) as the loss function to measure the difference between the predicted current value and the actual current value of the model; use the Adam optimizer to update the network parameters, and dynamically adjust the learning rate through an exponential decay strategy. The initial learning rate is set to 0.001.
[0117] After each training cycle, the performance of the model is evaluated using the validation set, and the loss value of the validation set is calculated. If the loss of the validation set does not decrease significantly for several consecutive cycles, the training is stopped early to prevent overfitting. The model parameters with the minimum validation set loss are saved as the final trained model.
[0118] Step E: Input the test set into the trained neural network model to check the prediction accuracy.
[0119] Evaluate the trained model using the test set, and calculate the loss value and prediction accuracy of the test set.
[0120] Currently, although there have been studies on applying neural network models to the field of semiconductor devices, no researchers have considered using them for predicting the performance of synaptic devices. The present invention proposes a multi-dimensional performance prediction method for deep learning synaptic devices based on neural networks, which fills the above gap. It realizes a low-cost, high-precision, simple and fast prediction method for the performance of synaptic devices, can provide theoretical support for the design and optimization of synaptic devices, and has broad application prospects in promoting the development of neuromorphic computing hardware.
[0121] The parts not detailed in the present invention belong to the common general knowledge of those skilled in the art. And the above description is only several specific examples of the present invention, and does not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principle of the present invention, various modifications and changes in form and details may be made without departing from the principle and structure of the present invention. For example, in addition to the channel layer thickness, electrolyte thickness, electrolyte solubility, and electrolyte ionic conductivity used in this example for design parameters, other design parameters that can affect the performance of synaptic devices can also be used; in addition to the convolutional neural network used in this example for the constructed neural network model, other neural networks with non-linear fitting ability and automatic feature extraction ability can also be adopted; in addition to the on-off ratio, single-pulse power consumption, state retention time, and non-linear factor used in this example for the predicted synaptic device performance, other performance indicators of synaptic devices can also be adopted. However, these corrections and changes based on the idea of the present invention are still within the scope of protection of the claims of the present invention.
Claims
1. A multi-dimensional performance prediction method for synaptic devices based on deep learning of neural networks, characterized in that: The steps include: (1) Modeling the synaptic device using computer-aided design (TCAD) simulation software, i.e., constructing a simulated synaptic device, and obtaining performance indicators corresponding to different design parameters by changing the design parameters of the simulated synaptic device multiple times; taking each design parameter and its corresponding performance indicator as a group of samples, and using all samples to form a sample set; (2) Preprocess the sample set data and randomly divide it into training set, validation set and test set according to proportion; (3) Construct a deep learning neural network model for synaptic device performance prediction; (4) Use the training set and the validation set to train and validate the constructed deep learning neural network model to obtain a trained neural network model; (5) Input the test set into the trained neural network model to test its prediction accuracy; (6) The verified high-accuracy neural network model is used as the final model, and the design parameters of the synaptic device are input into the model to obtain the performance prediction results of the device.
2. The method according to claim 1, characterized in that: In step (1), the design parameters of the simulated synaptic device are changed multiple times to obtain performance indicators corresponding to different design parameters; the performance indicators include switching ratio, single pulse power consumption, state retention time, and nonlinear factor; the design parameters include channel layer thickness, electrolyte thickness, electrolyte solubility, and electrolyte ion conductivity; the number of times the design parameters of the simulated synaptic device are changed is no less than 8 times.
3. The method according to claim 1, characterized in that: In step (2), the sample set data is preprocessed, specifically, the input data is standardized and the output data is normalized.
4. The method according to claim 3, characterized in that: The standardization and normalization processing are as follows: Among them, Z represents the standardized value, x i is the i-th sample data, λ and σ are the arithmetic mean and standard deviation of the data set respectively; x n represents the normalized value, x max and x min are the maximum and minimum values in the sample respectively.
5. The method according to claim 1, characterized in that: The deep learning neural network model in step (3) adopts a convolutional neural network; the model architecture includes an input layer, a feature mapping layer, a convolutional layer 1, a pooling layer 1, a convolutional layer 2, a pooling layer 2, a fully connected layer 1, a fully connected layer 2 and an output layer in sequence; the input features of the input layer are variables of a number corresponding to the design parameters; the feature mapping layer is used to reshape the multidimensional features and use them as convolution input; the convolution layer is used to extract local features of the data, and the pooling layer is used to compress the data output by the convolution layer; the fully connected layer is used to integrate the extracted features and make a final prediction; the output layer uses neurons of a number corresponding to the performance index to output the predicted performance index.
6. The method according to claim 5, characterized in that: The convolution kernel size of the convolution layer 1 and the convolution layer 2 are both 2×2, and the number of channels are 16 and 32 respectively; the pooling layer 1 and the pooling layer 2 adopt the maximum pooling method and the global average pooling method respectively; the fully connected layer 1 is used to map the multi-dimensional features to a higher-dimensional space, and the fully connected layer 2 uses 32 neurons to achieve prediction.
7. The method according to claim 1, characterized in that: Step (4) is to train and verify the constructed deep learning neural network model. The specific implementation steps are as follows: (4a) Setting the error function, optimization method and initial learning rate of the deep learning neural network; (4b) taking the design parameters as network input and the corresponding performance indicators as output; (4c) Input the training set data into the deep learning neural network, calculate the loss function of each batch of training, and use back propagation to optimize the network parameters; (4d) After each training cycle, the validation set is used to evaluate the performance of the model, the loss value of the validation set is calculated, and it is determined whether to stop the training early. If it is stopped early, the model parameters with the smallest loss of the validation set are saved and used as the optimal parameters to obtain a trained neural network model; otherwise, training is performed according to the preset number of training cycles until the preset number of cycles is reached to obtain a trained neural network model.
8. The method according to claim 7, characterized in that: Whether to stop training early in step (4d) is determined as follows: if the loss of the validation set remains stable for at least 10 consecutive training cycles, then stop training early; otherwise, continue the training process.
9. The method according to claim 1, characterized in that: The high accuracy neural network model in step (6) is judged by a model prediction accuracy greater than 90%.