Extraction Method of Six-Terminal Model of NMOS Device with DNW Isolation Structure

Abstract

The present invention provides a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure, the method comprising: designing an NMOS device structure; measuring the NMOS structure to obtain electrical test parameters; establishing an initial NMOS model; performing a first curve fitting; judging whether the curve fitting is qualified; if qualified, establishing a mismatch model of the NMOS structure; designing DNW structures of different sizes; measuring the C-V curve and the I-V curve of the parasitic diode; establishing an initial diode model; performing a second curve fitting; judging whether the curve fitting is qualified; if qualified, obtaining a voltage value, a current value, and a capacitance value mismatch model of the six-terminal NMOS structure with the DNW isolation structure, and verifying it. The present invention extracts the area and perimeter of the parasitic diode through LVS to establish an initial diode model, thereby accurately reflecting the model characteristic differences brought about by layout differences and improving the accuracy of the device model.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure. Background Art

[0002] There are two types of NMOS (N-Metal-Oxide-Semiconductor): one with isolation and one without. Because digital circuits are noisy and analog circuits are sensitive, to prevent noise from interfering with the analog circuits, a circuit with an N-well connected to the power supply and a P-substrate grounded circuit are typically placed around the analog circuits to provide isolation. If the noise impact is still significant during post-simulation and the area allows, additional circuits with N-wells connected to the power supply and P-substrate grounded circuits can be added, interleaved.

[0003] In traditional CMOS processes, NMOS devices are formed in a P-well or substrate connected to ground. Guard rings are used to collect substrate noise caused by minority carrier injection into the substrate and well. However, one issue is that capacitive coupling of noise from the well to the substrate means that more noise reaches the power supply. In digital circuits, this is generally not a problem due to the relatively high noise immunity of logic gates. However, in analog designs, such as 12-bit analog-to-digital converters (ADCs), noise can become a serious problem. Various techniques can be used to minimize this noise, such as surrounding analog devices with guard rings or using a separate power supply for the substrate / well. However, guard rings alone cannot prevent noise coupling deep into the substrate; they can only prevent surface currents. Another issue is that it is impossible to isolate the NMOS devices. As a result, the relatively noisy digital logic cannot be completely isolated from the more sensitive analog areas.

[0004] One solution is to isolate the NMOS devices by using an additional well, the "deep N-well" (DNW). In this case, the deep N-well is formed by high-energy ion implantation to provide a sufficiently deep peak impurity concentration without affecting NMOS device performance. The connection to the deep N-well is formed by an N-well ring connected to VDD. The deep N-well has the effect of reducing noise coupling through it to the substrate and has the advantage of completely isolating the NMOS devices. In mixed-signal designs, the use of deep N-well devices can significantly reduce noise coupling between sensitive analog areas and noisy digital areas.

[0005] Due to the widespread application of isolation structures in MOS devices (especially NMOS devices), circuit design engineers need to continuously improve device structures to enhance the accuracy of isolation structure models. Summary of the Invention

[0006] The object of the present invention is to provide a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure, which has a better isolation effect, better reduces the influence of noise, and improves the accuracy of the device model.

[0007] To solve the above technical problems, the present invention provides a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure, comprising the following steps:

[0008] Design NMOS structures of different sizes;

[0009] Measure NMOS structure to obtain electrical test parameters;

[0010] Establishing an initial NMOS model according to the obtained electrical test parameters;

[0011] Changing the characteristic parameters of the NMOS structure to perform the first curve fitting on the electrical test parameters;

[0012] Determine whether the first curve fitting is qualified. If not, modify the characteristic parameters of the NMOS structure and return to the previous step;

[0013] If qualified, a mismatch model of the NMOS structure is established;

[0014] Design DNW structures of different sizes;

[0015] Measure the CV curve and IV curve of the parasitic diode between the DNW and the substrate and between the DNW and the pwell;

[0016] The area and perimeter of the parasitic diode are extracted through LVS to establish the initial diode model;

[0017] Changing the characteristic parameters of the diode to perform a second curve fitting on the voltage, current and capacitance values;

[0018] Determine whether the second curve fitting is qualified. If not, modify the relevant characteristic parameters of the DNW structure and return to the previous step;

[0019] If qualified, a voltage value, current value and capacitance value mismatch model of the six-terminal NMOS structure with the DNW isolation structure is obtained, and the mismatch model is verified.

[0020] Optionally, the characteristic parameters of the NMOS structure include size, threshold voltage and temperature; and the electrical test parameters include voltage value and current value.

[0021] Optionally, the method for determining whether the first curve fitting is qualified includes: determining the offset between the voltage value and current value of the NMOS structure obtained by measurement and the voltage value and current value obtained according to the initial NMOS model; if the offset is greater than or equal to 10%, the fitting is unqualified; if the offset is less than 10%, the fitting is qualified.

[0022] Optionally, relevant characteristic parameters of the diode include size, threshold voltage and temperature.

[0023] Alternatively, the initial diode model is:

[0024] *pwell to dnw

[0025] d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw

[0026] *dnw to psub

[0027] d2 psub dnw d_5_dnpwpsub_2t area=area_dnwpsub pj=pj_dnwpsub;

[0028] Among them, area_pwdnw represents the total area of pwell, pj_pwdnw represents the total perimeter of pwell, area_dnwpsub represents the total area of dnwell, pj_dnwpsub represents the total perimeter of dnwell, dnw is a deep n-well, pwell is a p-well, dnwell is a deep n-well surrounding the p-well, and psub is a p-substrate.

[0029] Optionally, the method for determining whether the second curve fitting is qualified includes: determining the offset between the voltage value, current value and capacitance value of the diode obtained by measurement and the voltage value, current value and capacitance value obtained according to the initial diode model; if the offset is greater than or equal to 10%, the fitting is unqualified; if the difference is less than 10%, the fitting is qualified.

[0030] Optionally, the method for verifying the mismatch model includes:

[0031] A first mismatch rate is obtained by simulation based on a mismatch model of voltage, current and capacitance values of a six-terminal NMOS structure with a DNW isolation structure; and a second mismatch rate of voltage, current and capacitance values of the six-terminal NMOS structure with a DNW isolation structure is obtained by measurement.

[0032] Parameters related to the NMOS structure and parameters related to the size of the NMOS device isolation structure are modified according to the difference between the second mismatch rate and the first mismatch rate.

[0033] Optionally, the method of extracting the area and perimeter of the parasitic diode by LVS includes: extracting the distance from the pwell to the active area in the X / Y direction by LVS; the method of extracting the distance from the pwell to the active area in the X / Y direction by LVS includes:

[0034] Find the vertical edge A1 of the active area;

[0035] Find the horizontal edge A2 of the active area;

[0036] Calculate the horizontal distance between the vertical edge of pwell and the vertical edge A1 of the active area, and assign it to the A1 edge;

[0037] Calculate the vertical distance between the horizontal edge of pwell and the horizontal edge A2 of the active area and assign it to the A2 edge;

[0038] Count the horizontal distance vectors X1n / X2n and assign them to the GATE auxiliary layer A3 to obtain the horizontal distance parameters from the pwell to the vertical edges A1 of each active area.

[0039] Count the vertical distance vectors Y1n / Y2n and assign them to the GATE auxiliary layer A4 to obtain the vertical distance parameters from the pwell to the horizontal edge A2 of each active area;

[0040] Assign the calculated horizontal and vertical distance vector values to the GATE auxiliary layer A5 (X1n / X2n / Y1n / Y2n);

[0041] Calculate the weighted average (X1 / X2 / Y1 / Y2).

[0042] Optionally, the method of extracting the area and perimeter of the parasitic diode through LVS also includes: extracting the X / Y direction distance from the DNW to the active area through LVS; the method of extracting the X / Y direction distance from the DNW to the active area through LVS is the same as the method of extracting the X / Y direction distance from the pwell to the active area through LVS.

[0043] Optional voltage, current, and capacitance mismatch models for a six-terminal NMOS structure with a DNW isolation structure include:

[0044] .subckt m_n5_iso_6t_ckt dgsb dnw psub w=10e-6 l=0.5e-6 nf=1 mr=1dtemp=0 sa=1.238E-6 sb=1.238E-6 sd=4.66e-7 sca=0 scb=0 scc=0 mismod=1

[0045] .param

[0046] <h2 style=";text-align:left;direction:ltr">+ X1 = 15<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0047] <h2 style=";text-align:left;direction:ltr"> + X2 = 15<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0048] <h2 style=";text-align:left;direction:ltr"> + Y1 = 6<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0049] <h2 style=";text-align:left;direction:ltr"> + Y2 = 6<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0050] <h2 style=";text-align:left;direction:ltr"> + Xdn1 = 4<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0051] <h2 style=";text-align:left;direction:ltr"> + Xdn2 = 4<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0052] <h2 style=";text-align:left;direction:ltr"> + Ydn1 = 4<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0053] <h2 style=";text-align:left;direction:ltr"> + Ydn2 = 4<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0054] <h2 style=";text-align:left;direction:ltr"> + wf = 'w / nf'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0055] <h2 style=";text-align:left;direction:ltr"> + Lpwell = '(nf-1)*sd+l*nf+sa+sb+X1+X2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0056] <h2 style=";text-align:left;direction:ltr"> + Wpwell = 'wf+Y1+Y2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0057] <h2 style=";text-align:left;direction:ltr"> + Ldnwell = '(nf-1)*sd+l*nf+sa+sb+X1+X2+Xdn1+Xdn2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0058] <h2 style=";text-align:left;direction:ltr"> + Wdnwell = 'wf+Y1+Y2+Ydn1+Ydn2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0059] <h2 style=";text-align:left;direction:ltr"> + area_pwdnw = 'Lpwell*Wpwell'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0060] <h2 style=";text-align:left;direction:ltr"> + pj_pwdnw = '(Lpwell+Wpwell)*2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0061] <h2 style=";text-align:left;direction:ltr"> + area_dnwpsub = 'Ldnwell*Wdnwell'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0062] <h2 style=";text-align:left;direction:ltr"> + pj_dnwpsub = '(Ldnwell+Wdnwell)*2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0063] <h2 style=";text-align:left;direction:ltr"> *pwell to dnw<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0064] <h2 style=";text-align:left;direction:ltr"> d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0065] <h2 style=";text-align:left;direction:ltr"> *dnw to psub<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0066] d2 psub dnw d_5_dnpwpsub_2t area=area_dnwpsub pj=pj_dnwpsub

[0067] .ends m_n5_iso_6t_ckt

[0068] Where l represents the length of the gate, nf represents the number of gates, sd represents the distance between the gates, wf represents the width of the active area, sa represents the distance between the right edge of the active area and the gate, sb represents the distance between the left edge of the active area and the gate, X1 and X2 represent the distance from the pwell to the active area in the X direction, Y1 and Y2 represent the distance from the pwell to the active area in the Y direction, Xdn1 and Xdn2 Represents the distance from pwell to psub in the X direction, Ydn1 and Ydn2 represent the distance from pwell to psub in the Y direction, Lpwell represents the total length of pwell, Wpwell represents the total width of pwell, Ldnwell represents the total length of dnwell, Wdnwell represents the total width of dnwell, area_pwdnw represents the total area of pwell, pj_pwdnw represents the total perimeter of pwell, area_dnwpsub represents the total area of dnwell, pj_dnwpsub represents the total perimeter of dnwell, dnw is a deep n-well, pwell is a p-well, dnwell is a deep n-well surrounding the p-well, and psub is a p-substrate.

[0069] Compared to the prior art, the present invention provides a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure. LVS extracts the area and perimeter of the parasitic diode to establish an initial diode model. Leveraging the LVS tool's inherent ability to accurately extract the characteristic dimensions of the parasitic diode, the actual object dimensions in the layout are fed back for model calculation. The extracted values are consistent with the actual dimensions of the layout, allowing the actual dimensions in the layout to be used as input for model calculation. This accurately reflects the differences in model characteristics caused by layout differences and improves the accuracy of the device model. Furthermore, the addition of two parasitic diodes between the DNW and Pwell, and between the DNW and Psub, allows the six-terminal model of the NMOS device to better and more accurately reflect the device characteristics of the NMOS device after adding DNW isolation. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 This is the design layout of NMOS with DNW isolation structure.

[0071] Figure 2 This is a flow chart of a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0072] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0073] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense including "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense including "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense including "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0074] The NMOS with DNW isolation structure adds a parasitic diode (diode) on the basis of the NMOS device without isolation structure. Figure 1 This is the design layout of NMOS with DNW isolation structure, please refer to Figure 1 As shown, the first parasitic diode is from pwell (p-well) to dnwell (abbreviated as dnw or DNW, deep n-well), and the second parasitic diode is from dnwell to psub (p-substrate). These diodes primarily serve to isolate noise and generally have no impact on the performance of the underlying device. When modeling an NMOS device with a DNW isolation structure, simply attach the DNW parasitic diode to the NMOS model without the DNW. Specifically, the area (area) and perimeter (pj) of the first diode are expressed as formulas related to wf, l, sa, sb, nf, ds, and the distance from the pwell package AA. The area (area) and perimeter (pj) of the second diode are expressed as formulas related to the pwell area pj and the distance from the dnwell package pwell.

[0075] For example, please refer to Figure 1As shown in the figure, pwell is a p-well, dnwell is a deep n-well (also referred to as DNW) surrounding the p-well, psub is a p-substrate, l is the length of the gate, nf is the number of gates, sd is the distance between the gates, and multiple dummy gates are set on both sides of the gate. Figure 1 The figure shows five gates, with three dummy gates on either side, but this is not the only example. wf represents the width of the active area (AA), X1 and X2 represent the X-direction distances from the pwell to the active area, Y1 and Y2 represent the Y-direction distances from the pwell to the active area, Xdn1 and Xdn2 represent the X-direction distances from the pwell to the psub, and Ydn1 and Ydn2 represent the Y-direction distances from the pwell to the psub.

[0076] In the parasitic diode pwell_dnw between pwell and dnwell, the total length Lpwell of pwell is (nf-1)*sd+l*nf+sa+sb+X1+X2, the total width Wpwell of pwell is wf+Y1+Y2, the total area area_pwdnw of pwell is Lpwell*Wpwell, and the total perimeter pj_pwdnw of pwell is (Lpwell+Wpwell)*2.

[0077] In the parasitic diode dnw_psub between dnwell and psub, the total length of dnwell, Ldnwell, is: (nf-1)*sd+l*nf+sa+sb+X1+X2+Xdn1+Xdn2, the total width of dnwell, Wdnwell, is: wf+Y1+Y2+Ydn1+Ydn2, the total area of dnwell, area_dnwpsub, is: Ldnwell*Wdnwell, and the total perimeter of dnwell, pj_dnwpsub, is: (Ldnwell+Wdnwell)*2.

[0078] In view of the above two parasitic diodes, the present invention provides a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure. Figure 2 This is a flowchart of a method for extracting a six-terminal model of an NMOS device with a DNW isolation structure provided in one embodiment of the present invention. Please refer to Figure 2 As shown, the method for extracting the six-terminal model of the NMOS device with the DNW isolation structure provided in this embodiment includes the following steps:

[0079] Design NMOS structures of different sizes;

[0080] Measure NMOS structure to obtain electrical test parameters;

[0081] Establishing an initial NMOS model according to the electrical test parameters;

[0082] Changing the characteristic parameters of the NMOS structure to perform the first curve fitting on the electrical test parameters;

[0083] Determine whether the first curve fitting is qualified. If not, modify the characteristic parameters of the NMOS structure and return to the previous step;

[0084] If qualified, a mismatch model of the NMOS structure is established;

[0085] Design DNW structures of different sizes;

[0086] Measure the CV curve and IV curve of the parasitic diodes between DNW and Psub, and between DNW and pwell;

[0087] The area and perimeter of the parasitic diode are extracted through LVS to establish the initial diode model;

[0088] Changing the characteristic parameters of the diode to perform a second curve fitting on the voltage, current and capacitance values;

[0089] Determine whether the second curve fitting is qualified. If not, modify the relevant characteristic parameters of the DNW structure and return to the previous step;

[0090] If qualified, a voltage value, current value and capacitance value mismatch model of the six-terminal NMOS structure with the DNW isolation structure is obtained, and the mismatch model is verified.

[0091] In this embodiment, NMOS structures of different sizes are first designed, and then the electrical parameters of the NMOS structures are measured. That is, the electrical parameters of the NMOS structures of all sizes designed in the previous step are measured to obtain the electrical test parameters of the NMOS structures. In this embodiment, the electrical parameters of the NMOS structures are measured at different sizes, threshold voltages, or temperatures. The electrical test parameters include but are not limited to voltage values and current values. Then, an initial NMOS model is established based on the electrical test parameters.

[0092] Then, the characteristic parameters of the NMOS structure are changed to perform a first curve fit on the electrical test parameters. In this embodiment, the characteristic parameters of the NMOS structure include dimensions, threshold voltage, and temperature. Specifically, the dimensions, threshold voltage, and temperature of the NMOS structure are changed to perform a first curve fit on the voltage and current values. Next, a determination is made as to whether the first curve fit is satisfactory. If not, the characteristic parameters of the NMOS structure are modified, and the process returns to the previous step, i.e., "changing the characteristic parameters of the NMOS structure to perform curve fit on the electrical test parameters to obtain a first fitting curve." If satisfactory, a mismatch model for the NMOS structure is established, such as a voltage-current mismatch model for the NMOS structure. In one embodiment, determining whether the second curve fit is satisfactory includes determining an offset between the measured voltage and current values of the NMOS structure and the voltage and current values obtained based on the initial NMOS model. If the offset is greater than or equal to 10%, the fit is deemed unsatisfactory; if the offset is less than 10%, the fit is deemed satisfactory. In this embodiment, the voltage and current values of the initial NMOS model are obtained through simulation.

[0093] Next, DNW structures of different sizes (i.e., the aforementioned dnwell) were designed, and the CV and IV curves of the parasitic diodes between the DNW and Psub, and between the DNW and Pwell, were measured.

[0094] Then, the area and perimeter of the parasitic diode are extracted using LVS (Layout Versus Schematics) to establish an initial diode model. In this embodiment, the method of extracting the area and perimeter of the parasitic diode using LVS includes: extracting the X / Y direction distance from the pwell to the active area using LVS; the method of extracting the X / Y direction distance from the pwell to the active area using LVS includes:

[0095] Find the vertical edge A1 of the GATE active area:

[0096] ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient = COINCIDENT EDGEntgate_no_mis;

[0097] Find the horizontal edge A2 of the GATE active area:

[0098] nsdntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient=NOT COINCIDENTEDGE ntgate_no_mis;

[0099] Calculate the horizontal distance between the vertical edge of the pwell and the vertical edge A1 of the active area, and assign it to the A1 edge:

[0100] nsdntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace = DFMSPACE ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient pwell <= 10 BY ENC BYLAYER pwell COUNT == 0;

[0101] Calculate the vertical distance between the horizontal edge of pwell and the horizontal edge A2 of the active area, and assign it to the A2 edge:

[0102] ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace = DFMSPACE ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient pwell <= 10 BY ENC BYLAYER pwell COUNT == 0;

[0103] Count the horizontal distance vectors X1n / X2n and assign them to the GATE auxiliary layer A3 to obtain the horizontal distance parameters from the pwell to the vertical edge A1 of each active area segment:

[0104] ntgate_no_mis__pwell__enc__TVF_tmp_1.side = DFM PROPERTY ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient ntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace OVERLAP ABUT ALSO MULTI

[0105] [PER=RANGE_XXY( SORT_MERGE_XXY( CONCAT( VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace), ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace),EW(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_enclosure.dfmspace)+0), VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient),ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient),10)), VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient),ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.side_orient)))];

[0106] Count the vertical distance vectors Y1n / Y2n and assign them to the GATE auxiliary layer A4 to obtain the vertical distance parameters from the pwell to the horizontal edge A2 of each active area:

[0107] ntgate_no_mis__pwell__enc__TVF_tmp_1.end=DFM PROPERTY ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace OVERLAP ABUT ALSO MULTI [ PAR = RANGE_XXY( SORT_MERGE_XXY(CONCAT(VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace),

[0108] ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace),EW(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_enclosure.dfmspace)+0), VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient).ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient),10))), VECTOR(ECMIN(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient),ECMAX(ntgate_no_mis__pwell__enc__TVF_tmp_1.end_orient)) ) ];

[0109] Assign the calculated horizontal and vertical distance vector values to the GATE auxiliary layer A5 (X1n / X2n / Y1n / Y2n):

[0110] nsgate15_wpe = DFM PROPERTY ntgate_no_mis ntgate_no_mis__pwell__enc__TVF_tmp_1.side ntgate_no_mis__pwell__enc__TVF_tmp_1.end OVERLAP ABUT ALSO

[0111] [PER_1 = VPROPERTY( ntgate_no_mis__pwell__enc__TVF_tmp_1.side, PER,1 ) ]

[0112] [PER_2 = VPROPERTY( ntgate_no_mis__pwell__enc__TVF_tmp_1.side, PER, 2 ) ]

[0113] [PAR_1 = VPROPERTY( ntgate_no_mis__pwell__enc__TVF_tmp_1.end, PAR, 1 ) ]

[0114] [PAR_2 = VPROPERTY(ntgate_no_mis__pwell__enc__TVF_tmp_1.end, PAR, 2)]

[0115] Calculate the weighted average (X2 / X2 / Y1 / Y2):

[0116] proc calc_sca_dfm {PER_1 PER_2 PAR_1 PAR_2 W L UNITS} {set scale 1.0

[0117] set side_1 [device::dfm_vec_measurements $PER_1]

[0118] set side_2 [device::dfm_vec_measurements $PER_2]

[0119] set sides [concat $side_1 $side_2]

[0120] set end_1 [device::dfm_vec_measurements $PAR_1]

[0121] set end_2 [device::dfm_vec_measurements $PAR_2]

[0122] set sum [expr {[calc_sca_dfm__getsum $sides [$L] [$UNITS]] + [calc_sca_dfm__getsum $end_1 [$W] [$UNITS]] + [calc_sca_dfm__getsum $end_2 [$W] [$UNITS]]}] return [expr {$sum / ([$W] * $scale * [$L] * $scale * 1e12)}]。

[0123] In this embodiment, the method for extracting the area and perimeter of the parasitic diode using LVS further includes: extracting the X / Y distances from the DNW to the active area using LVS. The X / Y distances from the DNW to the active area, Xdn1+X1, Xdn2+X2, Ydn1+Y1, and Ydn2+Y2, can be calculated using the same method as described above, thereby obtaining the area and perimeter of the parasitic diodes between the DNW and Psub and between the DNW and Pwell.

[0124] In this embodiment, the initial diode model is:

[0125] *pwell to dnw

[0126] d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw

[0127] *dnw to psub

[0128] d2 psub dnw d_5_dnpwpsub_2t area=area_dnwpsub pj=pj_dnwpsub.

[0129] Then, the characteristic parameters of the diode are changed to perform a second curve fitting on the voltage value, current value and capacitance value. In this embodiment, the characteristic parameters of the diode include size, threshold voltage and temperature. Then, it is judged whether the second curve fitting is qualified. If it is unqualified, the relevant characteristic parameters of the DNW structure are modified, and the previous step is returned, that is, the step of "changing the characteristic parameters of the diode to perform curve fitting on the voltage value, current value and capacitance value to obtain a second fitting curve". Among them, the method for judging whether the second curve fitting is qualified includes: judging the offset between the voltage value, current value and capacitance value of the diode obtained by measurement and the voltage value, current value and capacitance value obtained according to the initial diode model. If the offset is greater than or equal to 10%, the fitting is unqualified. If the difference is less than 10%, the fitting is qualified. In this embodiment, the voltage value, current value and capacitance value of the initial diode model are obtained by simulation.

[0130] If qualified, a mismatch model of the voltage, current, and capacitance values of the six-terminal NMOS structure with the DNW isolation structure is obtained, and the mismatch model is verified. In this embodiment, the method for verifying the mismatch model includes: obtaining a first mismatch ratio through simulation based on the mismatch model of the voltage, current, and capacitance values of the six-terminal NMOS structure with the DNW isolation structure; obtaining a second mismatch ratio of the voltage, current, and capacitance values of the six-terminal NMOS structure with the DNW isolation structure through measurement; and modifying parameters related to the NMOS structure and parameters related to the size of the NMOS device isolation structure based on the difference between the second mismatch ratio and the first mismatch ratio.

[0131] The present invention uses LVS to extract the area and perimeter of the parasitic diode to establish an initial diode model. LVS takes advantage of the tool's ability to accurately extract the characteristic dimensions of the parasitic diode, and feeds back the actual object dimensions in the layout for model calculation. The extracted values are consistent with the actual dimensions of the layout, so that the actual dimensions in the layout can be used as input for model calculation, thereby accurately reflecting the differences in model characteristics caused by layout differences and improving the accuracy of the device model.

[0132] In this embodiment, the voltage, current, and capacitance mismatch model of a six-terminal NMOS structure with a DNW isolation structure (i.e., a six-terminal model of an NMOS device with a DNW isolation structure) includes:

[0133] .subckt m_n5_iso_6t_ckt dgsb dnw psub w=10e-6 l=0.5e-6 nf=1 mr=1dtemp=0 sa=1.238E-6 sb=1.238E-6 sd=4.66e-7 sca=0 scb=0 scc=0 mismod=1

[0134] .param

[0135] + X1 = 15

[0136] + X2 = 15

[0137] + Y1 = 6

[0138] + Y2 = 6

[0139] + Xdn1 = 4

[0140] + Xdn2 = 4

[0141] + Ydn1 = 4

[0142] + Ydn2 = 4

[0143] + wf = 'w / nf'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0144] <h2 style=";text-align:left;direction:ltr"> + Lpwell = '(nf-1)*sd+l*nf+sa+sb+X1+X2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0145] <h2 style=";text-align:left;direction:ltr"> + Wpwell = 'wf+Y1+Y2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0146] <h2 style=";text-align:left;direction:ltr"> + Ldnwell = '(nf-1)*sd+l*nf+sa+sb+X1+X2+Xdn1+Xdn2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0147] <h2 style=";text-align:left;direction:ltr"> + Wdnwell = 'wf+Y1+Y2+Ydn1+Ydn2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0148] <h2 style=";text-align:left;direction:ltr"> + area_pwdnw = 'Lpwell*Wpwell'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0149] <h2 style=";text-align:left;direction:ltr"> + pj_pwdnw = '(Lpwell+Wpwell)*2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0150] <h2 style=";text-align:left;direction:ltr"> + area_dnwpsub = 'Ldnwell*Wdnwell'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0151] <h2 style=";text-align:left;direction:ltr"> + pj_dnwpsub = '(Ldnwell+Wdnwell)*2'<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0152] <h2 style=";text-align:left;direction:ltr"> *pwell to dnw<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0153] <h2 style=";text-align:left;direction:ltr"> d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0154] <h2 style=";text-align:left;direction:ltr"> *dnw to psub<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0155] <h2 style=";text-align:left;direction:ltr"> d2 psub dnw d_5_dnpwpsub_2t area=area_dnwpsub pj=pj_dnwpsub<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0156] <h2 style=";text-align:left;direction:ltr"> .ends m_n5_iso_6t_ckt<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0157] Where l represents the length of the gate, nf represents the number of gates, sd represents the distance between the gates, wf represents the width of the active area, sa represents the distance between the right edge of the active area and the gate, sb represents the distance between the left edge of the active area and the gate, X1 and X2 represent the distance from the pwell to the active area in the X direction, Y1 and Y2 represent the distance from the pwell to the active area in the Y direction, Xdn1 and Xdn2 Represents the distance from pwell to psub in the X direction, Ydn1 and Ydn2 represent the distance from pwell to psub in the Y direction, Lpwell represents the total length of pwell, Wpwell represents the total width of pwell, Ldnwell represents the total length of dnwell, Wdnwell represents the total width of dnwell, area_pwdnw represents the total area of pwell, pj_pwdnw represents the total perimeter of pwell, area_dnwpsub represents the total area of dnwell, pj_dnwpsub represents the total perimeter of dnwell, dnw is a deep n-well, pwell is a p-well, dnwell is a deep n-well surrounding the p-well, and psub is a p-substrate.

[0158] This embodiment adds a DNW and psub to the six-terminal model of an NMOS device with a DNW isolation structure, creating a six-terminal model. This provides enhanced isolation and reduces the impact of noise. Furthermore, the addition of two parasitic diodes between the DNW and pwell, and between the DNW and Psub, allows the six-terminal model to better and more accurately reflect the device characteristics of the NMOS device with the added DNW isolation, thereby improving the accuracy of the device model.

[0159] In summary, in the method for extracting a six-terminal model of an NMOS device with a DNW isolation structure provided by the present invention, the area and perimeter of the parasitic diode are extracted through LVS to establish an initial diode model. Leveraging the LVS tool's inherent ability to accurately extract the characteristic dimensions of the parasitic diode, the actual object dimensions in the layout are fed back for model calculation. The extracted values are consistent with the actual dimensions of the layout, allowing the actual dimensions in the layout to be used as input for model calculation, thereby accurately reflecting the differences in model characteristics caused by layout differences and improving the accuracy of the device model. Furthermore, due to the addition of two parasitic diodes between the DNW and Pwell, and between the DNW and Psub, the six-terminal model of the NMOS device can better and more accurately reflect the device characteristics of the NMOS after adding DNW isolation.

[0160] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for extracting a six-terminal model of an NMOS device with a DNW isolation structure, characterized in that: The following steps are involved: Design NMOS structures of different sizes; Measure NMOS structure to obtain electrical test parameters; Establishing an initial NMOS model according to the electrical test parameters; Changing the characteristic parameters of the NMOS structure to perform the first curve fitting on the electrical test parameters; Determine whether the first curve fitting is qualified. If not, modify the characteristic parameters of the NMOS structure and return to the previous step; If qualified, a mismatch model of the NMOS structure is established; Design DNW structures of different sizes; Measure the CV curve and IV curve of the parasitic diodes between DNW and Psub, and between DNW and pwell; The area and perimeter of the parasitic diode are extracted through LVS to establish the initial diode model; Changing the characteristic parameters of the diode to perform a second curve fitting on the voltage, current and capacitance values; Determine whether the second curve fitting is qualified. If not, modify the characteristic parameters of the DNW structure and return to the previous step; If qualified, a diode model is established, and the established diode model is added to the established mismatch model of the NMOS structure to obtain a voltage, current and capacitance mismatch model of the six-terminal NMOS structure with a DNW isolation structure, and the mismatch model is verified.

2. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, characterized in that: The characteristic parameters of the NMOS structure include size, threshold voltage and temperature; the electrical test parameters include voltage value and current value.

3. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 2, wherein: The method for determining whether the first curve fitting is qualified includes: determining the offset between the voltage value and the current value of the NMOS structure obtained by measurement and the voltage value and the current value obtained according to the initial NMOS model; if the offset is greater than or equal to 10%, the fitting is unqualified; if the offset is less than 10%, the fitting is qualified.

4. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, wherein: The characteristic parameters of a diode include size, threshold voltage and temperature.

5. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, wherein: The initial diode model is: d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw d2 psub dnw d_5_dnwpsub_2t area=area_dnwpsub pj=pj_dnwpsub; Among them, area_pwdnw represents the total area of pwell, pj_pwdnw represents the total perimeter of pwell, area_dnwpsub represents the total area of dnwell, pj_dnwpsub represents the total perimeter of dnwell, dnw is a deep n-well, pwell is a p-well, dnwell is a deep n-well surrounding the p-well, psub is the p-substrate, b is the bulk, the bulk of the NMOS device is pwell, d1 is the first diode formed between the bulk and dnw, d_5_pwdnw_2t is the two-terminal diode model formed by pw and dnw in the 5V NMOS device, d2 is the second diode formed between psub and dnw, and d_5_dnwpsub_2t is the two-terminal diode model formed between dnw and psub in the 5V NMOS device.

6. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, wherein: The method for determining whether the second curve fitting is qualified includes: determining the offset between the voltage value, current value and capacitance value of the diode obtained by measurement and the voltage value, current value and capacitance value obtained according to the initial diode model; if the offset is greater than or equal to 10%, the fitting is unqualified; if the difference is less than 10%, the fitting is qualified.

7. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, characterized in that: The method for validating the model includes: A first mismatch rate is obtained by simulation based on a mismatch model of voltage, current and capacitance values of a six-terminal NMOS structure with a DNW isolation structure; and a second mismatch rate of voltage, current and capacitance values of the six-terminal NMOS structure with a DNW isolation structure is obtained by measurement. Parameters related to the NMOS structure and parameters related to the size of the NMOS device isolation structure are modified according to the difference between the second mismatch rate and the first mismatch rate.

8. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, wherein: Methods for extracting the area and perimeter of the parasitic diode using LVS include: extracting the distance from the pwell to the active area in the X / Y direction using LVS; Methods for extracting the distance from the pwell to the active area in the X / Y direction using LVS include: Find the vertical edge A1 of the GATE active area; Find the horizontal edge A2 of the GATE active area; Calculate the horizontal distance between the vertical edge of pwell and the vertical edge A1 of the active area, and assign it to the A1 edge; Calculate the vertical distance between the horizontal edge of pwell and the horizontal edge A2 of the active area and assign it to the A2 edge; Calculate the horizontal distance vector X1n / X2n and assign it to the GATE auxiliary layer A3 to obtain the horizontal distance parameters from the pwell to the vertical edge A1 of each active area segment, where X1n and X2n represent the horizontal distance vectors between the vertical edge of the pwell and the vertical edge A1 of the active area; Count the vertical distance vectors Y1n / Y2n and assign them to the GATE auxiliary layer A4 to obtain the vertical distance parameters from the pwell to the horizontal edge A2 of each active area segment, where Y1n and Y2n represent the vertical distance vectors between the horizontal edge of the pwell and the horizontal edge A2 of the active area; Assign the calculated horizontal and vertical distance vector values to the GATE auxiliary layer A5 (X1n / X2n / Y1n / Y2n); Calculate the weighted average (X1 / X2 / Y1 / Y2), where X1 and X2 represent the distance from the pwell to the active area in the X direction, and Y1 and Y2 represent the distance from the pwell to the active area in the Y direction.

9. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 8, characterized in that: The method of extracting the area and perimeter of the parasitic diode through LVS also includes: extracting the X / Y direction distance from the DNW to the active area through LVS; the method of extracting the X / Y direction distance from the DNW to the active area through LVS is the same as the method of extracting the X / Y direction distance from the pwell to the active area through LVS.

10. The method for extracting a six-terminal model of an NMOS device with a DNW isolation structure according to claim 1, wherein: The voltage, current, and capacitance mismatch models for the six-terminal NMOS structure with DNW isolation include: <h2 style=";text-align:left;direction:ltr">.subckt m_n5_iso_6t_ckt dgsb dnw psub w=10e-6l=0.5e-6nf=1mr=1dtemp=0sa=1.238E-6sb=1.238E-6sd=4.66e-7sca=0scb=0scc=0mismod=1 <h2 style=";text-align:left;direction:ltr"> .param +X1＝15 +X2＝15 +Y1＝6 +Y2＝6 <h2 style=";text-align:left;direction:ltr"> +Xdn1=4 <h2 style=";text-align:left;direction:ltr"> +Xdn2=4 <h2 style=";text-align:left;direction:ltr"> +Ydn1=4 <h2 style=";text-align:left;direction:ltr"> +Ydn2=4 <h2 style=";text-align:left;direction:ltr"> +wf = 'w / nf' <h2 style=";text-align:left;direction:ltr"> +Lpwell='(nf-1)*sd+l*nf+sa+sb+X1+X2' <h2 style=";text-align:left;direction:ltr"> +Wpwell='wf+Y1+Y2' <h2 style=";text-align:left;direction:ltr"> +Ldnwell='(nf-1)*sd+l*nf+sa+sb+X1+X2+Xdn1+Xdn2' <h2 style=";text-align:left;direction:ltr"> +Wdnwell='wf+Y1+Y2+Ydn1+Ydn2' <h2 style=";text-align:left;direction:ltr"> +area_pwdnw='Lpwell*Wpwell' <h2 style=";text-align:left;direction:ltr"> +pj_pwdnw='(Lpwell+Wpwell)*2' <h2 style=";text-align:left;direction:ltr"> +area_dnwpsub='Ldnwell*Wdnwell' <h2 style=";text-align:left;direction:ltr"> +pj_dnwpsub='(Ldnwell+Wdnwell)*2' <h2 style=";text-align:left;direction:ltr"> d1 b dnw d_5_pwdnw_2t area=area_pwdnw pj=pj_pwdnw <h2 style=";text-align:left;direction:ltr"> d2 psub dnw d_5_dnwpsub_2t area = area_dnwpsub pj = pj_dnwpsub <h2 style=";text-align:left;direction:ltr"> .ends m_n5_iso_6t_ckt Where l represents the length of the gate, w represents the width of the gate, nf represents the number of gates, sd represents the distance between the gates, wf represents the width of the active area, sa represents the distance between the right edge of the active area and the gate, sb represents the distance between the left edge of the active area and the gate, X1 and X2 represent the distance from pwell to the active area in the X direction, Y1 and Y2 represent the distance from pwell to the active area in the Y direction, Xdn1 and Xdn2 represent the distance from pwell to psub in the X direction, Ydn1 and Ydn2 represent the distance from pwell to psub in the Y direction, Lpwell represents the total length of pwell, and Wpwell represents the total width of pwell , Ldnwell represents the total length of dnwell, Wdnwell represents the total width of dnwell, area_pwdnw represents the total area of pwell, pj_pwdnw represents the total perimeter of pwell, area_dnwpsub represents the total area of dnwell, pj_dnwpsub represents the total perimeter of dnwell, dnw is a deep n-well, pwell is a p-well, dnwell is a deep n-well surrounding the p-well, psub is the p-substrate, b is bulk, the bulk of the NMOS device is pwell, d1 is the first diode formed between bulk and dnw, d_5_pwdnw_2t is a two-terminal diode model formed by pw and dnw in a 5V NMOS device, d2 is the second diode formed between psub and dnw, and d_5_dnwpsub_2t is a two-terminal diode model formed between dnw and psub in a 5V NMOS device.

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