Simulation integrated circuit test excitation generation method based on multi-stage Bayesian optimization

Abstract

The invention discloses an analog integrated circuit test excitation generation method based on multi-stage Bayesian optimization, which comprises the following steps: performing defect modeling on a to-be-tested analog integrated circuit to obtain a defect analog integrated circuit, then setting a search space according to an excitation source of the to-be-tested analog integrated circuit and discretizing, sampling in the search space to obtain an initial point, and generating an excitation source of the to-be-tested analog integrated circuit; secondly, searching a test excitation set by adopting multi-stage Bayesian optimization, taking a set of detectable fault sets of initial points as a combined fault detection set during searching, and taking a combined fault detection number as a target function of each initial point to form an initial historical excitation set; and a test excitation set required by the analog integrated circuit is obtained through multiple rounds of Bayesian optimization search. According to the method, the characteristics of Bayesian optimization are utilized, a multi-stage Bayesian optimization algorithm is designed, the search efficiency of the test excitation is improved, the simulation time is shortened, and the generation efficiency of the test excitation of the analog integrated circuit is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuit testing. More specifically, it relates to a method for generating test stimuli for analog integrated circuits based on multi-stage Bayesian optimization. Background Art

[0002] Testing of analog and mixed-signal circuits remains a challenging problem in the industry. Especially in the post-silicon testing phase after tape-out, performing functional tests based on established specifications may introduce significant test costs to the integrated circuit. Functional tests generally can obtain high-quality test results, but they require testing all key specifications of the circuit one by one, which may result in overly long test times. Additionally, performing functional tests requires expensive automatic test equipment (ATE), which is typically equipped with high-resolution analog instruments, digital signal processing (DSP) capabilities, and a large amount of storage space to store test response data.

[0003] With the growing demand in the Internet of Things (IoT) market for short-range communication systems, it has become increasingly necessary to develop low-cost test methods for analog and radio frequency modules. Low-cost integrated circuits (ICs) require production test technologies with low complexity, which can also be applied to wafer screening tests to avoid faulty parts from being packaged. Therefore, fault-oriented analog testing may provide a low-cost alternative for test engineers to avoid or at least reduce the complexity of developing and applying specification-based testing.

[0004] In fault-oriented analog testing, the voltages of each voltage source and the currents of each current source are used as input stimuli. To evaluate the test stimuli, fault injection and simulation of the circuit are required. Circuit simulation is completed by SPICE (Simulation program with integrated circuit emphasis) to obtain numerical solutions of circuit node voltages and other metrics by solving matrices. Different from test stimulus generation for digital circuits, the voltage of each node is a real number and cannot be evaluated through simple 0, 1 logical combinations.

[0005] During the testing process of analog and mixed-signal circuits, the combination of test stimuli (real number combinations within a certain range) compared to the combination of test stimuli for pure digital circuits (0 and 1 logical combinations) requires the number of test stimuli to be evaluated to increase from 2 n to m n(Where m is the number of values of each simulated power supply after introducing the step size, and n is the number of simulated power supplies), it increases exponentially. During the testing process of analog and mixed-signal circuits, the "units" where faults occur have been reduced from the gate circuit level to the component level, and the number of "units" that require fault injection has increased by 2 to 15 times. Similarly, during the testing process of analog and mixed-signal circuits, the types of the most basic faults that need to be injected have increased from stuck-at faults and stuck-open faults to at least six types such as open and short-circuit faults of three-terminal components and two-terminal components.

[0006] Therefore, during the process of evaluating test stimuli, if all stimuli are evaluated one by one, it will greatly increase the evaluation time in terms of both the evaluation method and the number of test stimulus combinations. Therefore, search algorithms similar to random search and heuristic search need to be used to reduce the number of evaluations.

[0007] At the same time, in terms of the number of "units" that require fault injection and the types of faults, the cost of evaluating each stimulus is also high. Obtaining information to guide the next search in the search algorithm itself is one of the optimization goals. Therefore, it is necessary to minimize the number of stimuli that need to be evaluated. That is, it is necessary to select the stimuli that need to be evaluated next under the limited current information, and the cost of each evaluation is very high. Therefore, it is necessary to find a balance between exploring unknown areas and utilizing areas with relatively high evaluated values currently. Summary of the Invention

[0008] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method for generating test stimuli for analog integrated circuits based on multi-stage Bayesian optimization. By utilizing the characteristics of Bayesian optimization, a multi-stage Bayesian optimization algorithm is designed to improve the search efficiency of test stimuli, reduce the simulation time, and improve the generation efficiency of test stimuli for analog integrated circuits.

[0009] To achieve the above-mentioned invention purpose, the method for generating test stimuli for analog integrated circuits based on multi-stage Bayesian optimization of the present invention includes the following steps:

[0010] S1: For the analog integrated circuit to be tested, identify all components in the circuit netlist, establish fault models for all components except the power supply respectively, generate a fault list, perform equivalent compression on each fault model, and inject them into the analog integrated circuit to be tested one by one to obtain a fault simulation analog integrated circuit;

[0011] S2: According to the number M of excitation sources of the analog integrated circuit to be tested and the voltage range of each excitation source, establish an M-dimensional search space; set the test stimulus step size according to actual needs, and then discretize the search space to obtain the coordinates of each search grid point;

[0012] S3: Sample D initial points start in the search space d , where d = 1, 2, …, D. For each initial point start in the analog integrated circuit d perform fault simulation and record the detectable fault set f of each initial point start d ; startd ;

[0013] S4: Search for the test excitation set based on multi-stage Bayesian optimization, including the following steps:

[0014] S4.1: Obtain the union of the detectable fault sets f of the D initial points start d as the combined fault detection set F startd , and take the number of detectable faults in the combined fault detection set F 1 as the combined fault detection quantity V 1 , then take the combined fault detection quantity V 1 as the objective function value of each initial point start 1 to obtain the historical excitation set E d ; 1 ;

[0015] S4.2: Set the surrogate model according to actual needs and pre-train the surrogate model using the historical excitation set E 1 ;

[0016] S4.3: Let the Bayesian optimization round s = 1;

[0017] S4.4: Perform the s-th round of Bayesian optimization. The specific method is as follows:

[0018] S4.4.1: Let the search round r = 1;

[0019] S4.4.2: Set the sampling function according to actual needs and select the excitation p in the complement of the historical excitation set E s in the search space according to the maximum value of the sampling function s,r ;

[0020] S4.4.3: Simulate the analog acquisition circuit to obtain the detectable fault set f of the excitation p s,r ; Obtain the union of the detectable fault set f s,r and the combined fault detection set F s,r , and take the number of detectable faults in this union as the combined fault detection quantity V s corresponding to the excitation p s,r ; s,r ;

[0021] S4.4.4: Use the excitation p s,rand the corresponding combined fault detection quantity V s,r Update the surrogate model;

[0022] S4.4.5: Determine whether r < R, where R represents the number of search rounds for each round of Bayesian optimization. If so, go to step S4.4.6; otherwise, this round of Bayesian optimization ends;

[0023] S4.4.6: Let the search round r = r + 1, and return to step S4.4.2;

[0024] S4.5: Determine whether the Bayesian optimization end condition is reached. If so, go to step S4.6; otherwise, go to step S4.8;

[0025] S4.6: Obtain the detectable fault set f s,r of the R excitations p s,r searched in this round of Bayesian optimization and the combined fault detection set F s as the combined fault detection set F s+1 , and use the number of detectable faults in this set as the combined fault detection quantity V s+1 ; Then use the combined fault detection quantity V s+1 as the objective function values of the R excitations p s,r searched in this round of Bayesian optimization and the original excitations in the historical excitation set E s to obtain the historical excitation set E s+1 ;

[0026] S4.7: Let the Bayesian optimization round s = s + 1, and return to step S4.4;

[0027] S4.8: Use the historical excitation set E S as the test excitation set E for the final analog circuit test.

[0028] The method for generating test excitations for analog integrated circuits based on multi-stage Bayesian optimization in the present invention performs defect modeling on the analog integrated circuit to be tested to obtain a defect simulation analog integrated circuit, then sets the search space according to the excitation source of the analog integrated circuit to be tested and discretizes it, samples initial points in the search space, and then uses multi-stage Bayesian optimization to search for the test excitation set. When searching, the union of the detectable fault sets of the initial points is used as the combined fault detection set, and the combined fault detection quantity is used as the objective function for each initial point to form an initial historical excitation set, and then the test excitation set required for the analog integrated circuit is obtained through multiple rounds of Bayesian optimization search.

[0029] The present invention proposes a multi-stage Bayesian optimization method. In each stage, the position of the next excitation to be evaluated is determined through a sampling function and a surrogate model, taking into account both "exploration-exploitation". It can also take into account that a single excitation can detect more faults and multiple excitation combinations can detect as many faults as possible. Compared with grid search and random search, it shows better performance, and can greatly reduce the simulation time during the process of selecting test excitation combinations, which has important practical significance for reducing the test cost of analog integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a flowchart of the specific implementation of the method for generating test excitations for analog integrated circuits based on multi-stage Bayesian optimization of the present invention;

[0031] Figure 2 is an information table of the hard fault model of components specified by IEEE P2427;

[0032] Figure 3 is an example diagram of MOS transistor fault injection in this embodiment;

[0033] Figure 4 is an example diagram of the search space;

[0034] Figure 5 is a flowchart of searching for a test excitation set based on multi-stage Bayesian optimization in the present invention;

[0035] Figure 6 is a flowchart of Bayesian optimization in the present invention;

[0036] Figure 7 is a flowchart of the optimization of test excitations based on the Pareto genetic algorithm in this embodiment;

[0037] Figure 8 is a structural diagram of the bandgap reference circuit in this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] The following describes the specific implementation of the present invention with reference to the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be particularly noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0039] To better illustrate the technical solution of the present invention, the technical principle of the present invention will be briefly described first.

[0040] In the testing of analog integrated circuits, fault coverage and detectable fault coverage are two very important metrics. The fault coverage, defect_coverage, is equal to the number of detectable faults, defect, divided by the total number of injected faults, defectall, and can be used to evaluate the quality of the current fault detection algorithm:

[0041]

[0042] Because some circuit components are added during the design of analog integrated circuits to mitigate the impact of process variations. At the same time, as the scale of analog integrated circuits increases and the circuit structure becomes more complex, there are some faults in the circuit structure that cannot be detected. Then, if there are undetectable faults, the detectable fault coverage should be added as one of the measurement criteria while measuring the current fault detection algorithm through the fault coverage. The formula for the detectable fault coverage, detectable_defect_coverage, is:

[0043]

[0044] where detectable_defect represents the number of detectable faults.

[0045] In the process of design for testability (DFT) of analog integrated circuits, it is often necessary to ensure the quality of integrated circuits by leading out internal test points with high detectable fault coverage in advance. However, the cost of leading out internal test points in this process is very high. Therefore, without changing the leading out of internal test points, each measurement point of the analog integrated circuit is modeled as a system of non-linear equations about input excitation:

[0046]

[0047] where i m represents the m-th excitation, m = 1, 2, …, M, and M represents the number of excitations. node n represents the n-th measurement point, n = 1, 2, …, N, and N represents the number of measurement points. fault j represents the j-th fault state, j = 0 indicates that the analog integrated circuit has no fault, j = 1, 2, …, K, and K represents the number of faults. represents the algebraic relationship between the node response and the test excitation under the current fault state fault j Therefore, under different faults, the algebraic relationship between the measurement point response and the test excitation of the analog integrated circuit is different, that is

[0048] Therefore, under different faults, the algebraic relationship between the measurement point response and the test excitation of the analog integrated circuit is different, that is They are different. By comparing the outputs of the same measurement point under different fault states under the same excitation, if the output exceeds the set threshold, it can be determined that this fault is measurable.

[0049] There is already a fair amount of expertise in digital integrated circuit test vector generation (ATPG), but the progress in analog integrated circuit (ATPG) has been relatively slow. At the same time, different from the excitation types in digital integrated circuit ATPG which are simple binary 0, 1 codes representing digital voltages, the test excitations of analog integrated circuits can be complex test excitations such as continuous-time signals, multi-tone multi-frequency signals, etc., can also be single-frequency single-amplitude sine signals, or even single-amplitude DC excitations.

[0050] However, the evaluation of test excitations depends on the fault coverage rate. To obtain the fault coverage rate, it is necessary to solve the above-mentioned non-linear equations, that is, to perform SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The more complex the excitation, the longer the required simulation time, but the stronger the ability to reflect the differences in algebraic relationships.

[0051] With the continuous increase in the complexity of analog integrated circuits (ICs), especially mixed-signal circuits, the time cost of using complex excitation signals in the simulation process has increased significantly. To address this challenge, the present invention proposes a test method based on direct current (DC) excitation. This method uses the DC analysis with the optimal execution speed of the SPICE tool to evaluate the fault coverage rate, thereby effectively shortening the test cycle.

[0052] In traditional analog IC design, there are usually one or two voltage sources. However, when the number of voltage sources increases, the potential combinations of test excitations will increase exponentially. For example, for a single voltage source, if there are 20 different effective voltage levels within its operating range, there will be 20 possible test excitations. In the case of a dual voltage source, the number of different voltage combinations will reach 400; while for a triple voltage source, this number jumps to 8,000. Even if each combination is quickly simulated in the SPICE DC simulation mode, the cumulative time overhead is still not negligible.

[0053] Therefore, it is a challenging task to select a single test excitation or a combination of test excitations that can achieve a sufficiently high fault coverage rate without comprehensively evaluating all potential test excitations.

[0054] One challenge in evaluating test stimuli is that it is impossible to know exactly their specific fault coverage before actually executing these tests. Therefore, when choosing the next test stimulus to evaluate, one must rely on prior experience and existing information to make decisions. In other words, based on the information currently at hand, one needs to decide which test stimulus should be evaluated next to optimize the fault detection efficiency.

[0055] During the process of test stimulus generation, a typical "exploration-exploitation" problem is faced: on the one hand, it is necessary to explore uncertain regions that have not been evaluated but may have a higher fault coverage; on the other hand, it is also necessary to focus on regions that are shown to be able to produce good results based on the existing information. To achieve the best fault detection efficiency, a reasonable balance must be found between the two. Specifically, based on the information provided by the currently evaluated test stimuli, strategies can be formulated to decide which test stimulus should be evaluated next, so as to ensure that potential better test points are not missed and the verified effective resources can be fully utilized.

[0056] Bayesian optimization is a method used to solve such problems. Bayesian optimization is a sequential design strategy for global optimization, especially suitable for cases where the evaluation cost of the objective function is high, non-differentiable, or noisy. Different from traditional gradient-based methods, Bayesian optimization approximates the unknown objective function by constructing a surrogate model (usually a Gaussian process) and uses this model to guide the search process. The Bayesian optimization process can be briefly described as follows:

[0057] 1) Select a set of initial observation points and evaluate the objective function values at these points. This data will be used to train the initial surrogate model.

[0058] 2) Based on the existing observation data, use a statistical model such as a Gaussian process as a surrogate model to model the objective function. This model can not only predict the output values at unvisited locations but also give an estimate of the uncertainty of the prediction. This step reflects the "prior" in the Bayesian method, that is, our assumption about the objective function when there is no new information.

[0059] 3) Define an acquisition function, which is a function of the posterior distribution of the surrogate model. The acquisition function measures the value of potential evaluation points, taking into account both exploration and exploitation. Select the point that maximizes the acquisition function as the candidate point for the next objective function to be evaluated.

[0060] 4) Evaluate the objective function value at the selected new point and add this new observation to the existing dataset. Then, based on all available data, update the parameters of the surrogate model using Bayes' rule to obtain the "posterior" distribution of the objective function. This update reflects that as new information arrives, the understanding of the objective function becomes more precise.

[0061] By adopting the Bayesian optimization algorithm to explore and optimize the test stimuli, the fault coverage rate can be maximized within a limited number of evaluations. However, in this process, the fault coverage rate not only depends on the number of faults that can be diagnosed by the test stimuli, but is also affected by the mutual coverage characteristics among the test stimuli. Some test stimuli with low fault coverage rates may be able to detect unique faults that high-fault-coverage test stimuli fail to reach.

[0062] Therefore, in order to more efficiently utilize all the test stimuli in the exploration process, a comprehensive evaluation method needs to be adopted, that is, comprehensively analyze all the evaluated test stimuli and select a combination that can achieve the maximum fault coverage as a whole. This is not simply to select the test stimuli with the highest individual fault coverage rate, but to construct a set of test stimuli, where each member can contribute its unique fault coverage ability, so as to ensure that as many potential faults as possible are diagnosed.

[0063] In addition, this phenomenon reminds us that if simply selecting test stimuli with high fault coverage rates as the goal of Bayesian optimization during the test stimulus generation process, it may lead to insufficient overall fault coverage of the final test stimulus combination. To solve this problem, the present invention proposes a test stimulus generation strategy based on multi-stage Bayesian optimization.

[0064] In multi-stage Bayesian optimization, a fixed number of evaluations is set for each stage. At the beginning of each stage, the algorithm selects the new test stimulus with the highest fault coverage rate under the current selected test stimulus combination. At the end of the stage, all the test stimuli participating in the optimization will be added to the selected test stimulus pool. At the same time, the fault detection rates and stimulus point information of these test stimuli will be input into the Gaussian model for pre-learning to better guide the selection in the subsequent stages.

[0065] At the same time, as more and more faults are covered, the uncovered faults will concentrate on some singular points, and the number of detectable faults of these singular points is almost irrelevant to the surrounding points, that is, as the number of rounds increases, the role of prior experience becomes smaller and smaller. Therefore, the present invention gradually increases the randomness of the algorithm as the number of rounds increases, and selects exploration more in the balance of "exploration - exploitation" rather than using prior experience.

[0066] In this way, at each new stage, the optimization goal is to select those new test stimuli that, when combined with the test stimuli already evaluated in the previous stage, achieve the highest fault coverage. This process continues until the pre-set maximum number of evaluations or the expected fault coverage is reached. Once the optimization process stops, a subset is selected from all the evaluated test stimuli to ensure the use of the minimum number of test stimuli while maintaining the same fault coverage level.

[0067] This method not only improves the efficiency of fault diagnosis but also ensures the diversity of test stimulus combinations, avoiding the limitations that may arise from solely pursuing high fault coverage. Through multi-stage optimization and pre-learning of the Gaussian model, the most effective test stimuli can be more accurately identified and selected, thus achieving comprehensive and efficient fault coverage.

[0068] Based on the above analysis, the present invention proposes a method for generating test stimuli for analog integrated circuits based on multi-stage Bayesian optimization, aiming to find the test stimulus combination with the highest fault coverage within a limited number of evaluations. Figure 1 It is a flowchart of the specific implementation manner of the method for generating test stimuli for analog integrated circuits based on multi-stage Bayesian optimization of the present invention. As Figure 1 shown, the specific steps of the method for generating test stimuli for analog integrated circuits based on multi-stage Bayesian optimization of the present invention include:

[0069] S101: Component fault modeling and injection:

[0070] For the analog integrated circuit to be tested, all components in the circuit netlist are identified, fault models are established for all components except the power supply, and a fault list is generated. Each fault model is equivalently compressed and injected into the analog integrated circuit to be tested one by one to obtain a fault-simulated analog integrated circuit.

[0071] In this way, faults that may occur due to various fault mechanisms (such as additional metal deposition) during the actual manufacturing process can be simulated. In this embodiment, the fault 10 model provided by the IEEE P2427 standard proposal is adopted. According to the definition of the IEEE P2427 standard draft, a fault is considered an unexpected permanent change in a circuit component or component connection that is outside the component manufacturing specifications. Device-level faults that occur in integrated circuits are generally divided into two categories: parametric faults and hard faults. Hard faults are usually caused by problems in the silicon manufacturing process such as dust particles, insufficient etching, etc., which will cause a change in the topology of the manufactured circuit.

[0072] Defect - Oriented Testing (DOT) relies on a precisely defined fault model to achieve a quantitative assessment of fault coverage. Although fault modeling in analog integrated circuits has not reached the same level of standardization as in digital circuits, a draft emerging standard proposed by the IEEE P2427 working group is working on solving the standardization problem of hard - fault modeling in the fields of analog integrated circuits and power electronics. Figure 2 It is the information table of the component hard - fault model specified by IEEE P2427. As Figure 2 shown, for two - port components (such as resistors and capacitors), two basic fault modes of open - circuit and short - circuit are defined; for three - port components (such as MOS transistors and bipolar transistors), an open - circuit condition is set for each port and short - circuits between any two ports, totaling six fault modes. In this embodiment, to improve the simulation efficiency and avoid unnecessary computational overhead, short - circuit faults are not injected into components with the same ports.

[0073] In this embodiment, fault injection is completed by generating code blocks for different devices in the circuit description language netlist (SPICE Netlist). The ".alter" statement of SPICE is used to modify the netlist structure to achieve the modification and simulation of the netlist of the circuit describing the fault - free state. Here, the generation of code blocks is implemented by Python, and the specific netlist modification and simulation are implemented by HSPICE software. That is, simulate circuits with various faults and obtain circuit performance parameters. By comparing the responses of the faulty circuits with the reference responses of the fault - free circuits, the fault detection results can be analyzed. Figure 3 It is an example diagram of MOS transistor fault injection in this embodiment. As Figure 3 shown, Figure (a) shows the injection methods of short - circuit faults, open - circuit faults, and open - gate faults of three - terminal devices, and Figure (b) shows the fault models of short - circuit faults, open - circuit faults, and open - gate faults of three - terminal devices.

[0074] S102: Establish a search space:

[0075] According to the number of excitation sources M of the analog integrated circuit to be tested and the voltage range of each excitation source, an M - dimensional search space is established. Given that modifying the value of the excitation source within a specific granularity does not change the circuit response, the present invention introduces the concept of an excitation step size, sets the test excitation step size (i.e., search accuracy) according to actual needs, and then discretizes the search space to obtain the coordinates of each search grid point.

[0076] Figure 4 It is an example diagram of the search space. As Figure 4As shown, in this embodiment, 0.1V is selected as the excitation step. Additionally, since it is a CMOS circuit, the general voltage range is [0, 2.5]. If there are two excitation sources, then the search space is a two-dimensional search space, where the blue points correspond to the available excitation points. If there are three excitation sources, the search space is a three-dimensional search space, where the red points are the available excitation points.

[0077] S103: Sampling the initial points:

[0078] Sample D initial points start in the search space d , d = 1, 2, …, D, and for each initial point start in the analog integrated circuit d perform fault simulation and record the detectable fault set of each initial point start d

[0079]

[0080] In this embodiment, the Latin hypercube sampling method is used to sample the initial points. Latin Hypercube Sampling (LHS) is a random sampling technique for multi-dimensional spaces, commonly used in computer experiments and Monte Carlo simulations. It aims to uniformly cover the multi-dimensional parameter space, improving the efficiency and accuracy of sampling. The core idea of Latin hypercube sampling is to divide the range of each dimension into equally probable intervals and ensure that each interval is sampled once in each dimension. This can ensure the uniform distribution of each parameter in the high-dimensional space and avoid the aggregation of sample points. The specific method of Latin hypercube sampling is as follows:

[0081] Uniformly divide the interval of each dimension in the search space into L small intervals. For each dimension m, normalize the corresponding excitation value space to the interval [0, 1] and divide it into L equal-length sub-intervals:

[0082]

[0083] For each dimension, randomly select a point in these sub-intervals and ensure that in each dimension, each sub-interval is selected once. This can ensure the uniform distribution in each dimension. Combine the random points in each dimension to form D M-dimensional initial points.

[0084] S104: Search for the test excitation set based on multi-stage Bayesian optimization:

[0085] Next, search for the test excitation set based on multi-stage Bayesian optimization. Figure 5 is the flow chart of searching for the test excitation set based on multi-stage Bayesian optimization in the present invention. As Figure 5As shown in the figure, the specific steps of the multi-stage Bayesian optimization search test excitation set in the present invention include:

[0086] S501: Initialize the historical excitation set:

[0087] Obtain the set of detectable faults for D initial points start d and take the union as the combined fault detection set F of 1 , and take the number of detectable faults in the combined fault detection set F 1 as the combined fault detection quantity V 1 , and then take the combined fault detection quantity V 1 as the objective function value of each initial point start d to obtain the historical excitation set E 1 .

[0088] S502: Pre-train the surrogate model:

[0089] Set the surrogate model according to actual needs and pre-train the surrogate model using the historical excitation set E 1 .

[0090] In Bayesian optimization, the surrogate model can not only predict the output values of unvisited locations but also give an estimate of the uncertainty of the prediction. This step reflects the "prior" in the Bayesian optimization method, that is, the assumption of the objective function when there is no new information. The surrogate model can be set according to actual needs, and the surrogate model used in this embodiment is a Gaussian process model.

[0091] S503: Let the Bayesian optimization round s = 1.

[0092] S504: Bayesian optimization:

[0093] Perform the s-th round of Bayesian optimization. Figure 6 is the flowchart of Bayesian optimization in the present invention. As Figure 6 shown, the specific steps of Bayesian optimization in the present invention include:

[0094] S601: Let the search round r = 1.

[0095] S602: Select an excitation:

[0096] Set the sampling function according to actual needs and select the excitation p s in the search space according to the maximum value of the sampling function in the complement of the historical excitation set E s,r .

[0097] In Bayesian optimization, the most crucial technique is the acquisition function, which is a function of the posterior distribution of the surrogate model and is generally denoted by α(x). In this embodiment, the selected acquisition function is the Probability of Improvement (PI) function, and its calculation formula is:

[0098] α PI (x) = P(f(x) ≥ (f(x + ) + ∈)) (2)

[0099] Among them, α PI (x) represents the probability of improvement, P(·) represents probability, x + is the point x i that maximizes f(x i ) in the previous t steps, where i ∈ [1, t]. ∈ is a very small positive constant used to balance "exploration - exploitation".

[0100] Since the surrogate model used in this embodiment is a Gaussian process model, the formula for the probability of improvement PI can be expressed as:

[0101]

[0102] Among them, Φ(·) is the cumulative distribution function CDF (Cumulative Distribution Function), μ t (x) is the mean of the t points that have been evaluated, and σ t (x) is the standard deviation of the t points that have been evaluated.

[0103] Φ(x) = P(X ≤ x) (4)

[0104] When searching, according to formula (3), x t is the known optimal value, and the CDF value higher than μ t (x) near it will be relatively large, and the position of x t+1 will be near x t , which reflects the "exploitation" of the existing optimal value. Since the purpose of Bayesian optimization is not to simulate the entire curve with a Gaussian process but to find the best value with as few sampling times as possible. Therefore, it is necessary to increase ∈ as a constant to balance exploration and exploitation. Since the σ t (x) of the unexplored region is relatively large, after appropriately increasing ∈, the CDF of the unexplored region is relatively large. In short, increasing the value of ∈ helps to explore unknown regions, and decreasing the value of ∈ helps to exploit the existing region.

[0105] S603: Simulate to obtain the set of detectable faults:

[0106] Simulate the analog acquisition circuit to obtain the excitation p s,r of the detectable fault set f s,r . Obtain the detectable fault set f s,r and the combined fault detection set F s . Take the number of detectable faults in this set as the combined fault detection number V s,r corresponding to the excitation p s,r .

[0107] S604: Update the surrogate model:

[0108] Use the excitation p s,r and its corresponding combined fault detection number V s,r to update the surrogate model.

[0109] Update the parameters of the surrogate model using the excitation selected in each search and the corresponding objective function values, and the "posterior" distribution of the objective function can be obtained. This update reflects that as new information arrives, the understanding of the objective function becomes more precise.

[0110] S605: Determine whether r < R, where R represents the number of search rounds for each round of Bayesian optimization. If so, go to step S606; otherwise, this round of Bayesian optimization ends.

[0111] S606: Let the search round r = r + 1, and return to step S602.

[0112] S505: Determine whether the Bayesian optimization end condition is reached. If so, go to step S506; otherwise, go to step S508. The Bayesian optimization end condition can be set according to actual needs, such as setting the maximum number of rounds of Bayesian optimization or the number of detectable faults reaching the total number of faults.

[0113] S506: Update the historical excitation set:

[0114] Obtain the detectable fault set f s,r and the combined fault detection set F s,r of the R excitations p s searched in this round of Bayesian optimization, and use it as the combined fault detection set F s+1 . Take the number of detectable faults in this set as the combined fault detection number V s+1 . Then use the combined fault detection number V s+1 as the objective function values of the R excitations p s,r searched in this round of Bayesian optimization and the original excitations in the historical excitation set E s to obtain the historical excitation set E s+1 .

[0115] S507: Set the Bayesian optimization round s=s+1, and return to step S504.

[0116] S508: Get the test stimulus set:

[0117] The historical incentive set E S The test stimulus in is used as the test stimulus set E for the final analog integrated circuit test.

[0118] The test stimulus set obtained as above covers all simulated stimuli in the search process. This approach certainly ensures the comprehensiveness of the test, but it also inevitably introduces a large number of redundant test stimuli. In order to more effectively control the test cost and improve the test efficiency, after the defect coverage of the test stimulus set reaches the expected index, the test stimulus can be screened and optimized, aiming to achieve the highest possible defect detection rate with the most streamlined number of test stimuli. Since it is a multi-objective optimization problem to meet the two goals of low test cost and high test performance at the same time, and since there are usually multiple Pareto optimal solutions for multi-objective optimization problems, finding and determining the Pareto optimal solution set becomes the key to solving multi-objective problems. Based on the above principles, in this embodiment, the Pareto genetic algorithm is used to further optimize the test stimulus set E for the test stimulus, in order to find a series of Pareto optimal solutions, thereby providing a diverse selection set, so that it can weigh cost and performance according to actual conditions and needs, and make more reasonable decisions. Figure 7 : is a flow chart of test stimulus optimization based on Pareto genetic algorithm in this embodiment. Figure 7 As shown, the specific steps of test stimulus optimization based on the Pareto genetic algorithm in this embodiment include:

[0119] S701: Determine optimization target:

[0120] Determine the optimization target of test stimulus selection according to actual needs, record the number of optimization targets as B, and set the optimization objective function g of the test stimulus selection scheme b (X), b = 1, 2, ..., B, the smaller the optimization objective function value, the better the test scheme. In this embodiment, there are two optimization objectives, including the number of test excitation vectors and the defect detection rate. The number of test excitation vectors is related to the test cost. Generally speaking, the larger the number of test excitation vectors, the higher the test cost, so it is necessary to minimize the number of test excitation vectors. The optimization objective function expression of the number of test excitation vectors is:

[0121]

[0122] Where X = [x 1 ,x 2 ,…,x D ] represents the test stimulus vector selection scheme, x d is a binary variable, xd = 0 indicates that the d-th test excitation vector is not selected in the test excitation vector selection scheme corresponding to the individual, x d = 1 indicates that the d-th test excitation vector is selected in the test scheme corresponding to the individual, where d = 1, 2, …, D, and D represents the number of test excitation vectors in the test excitation set E.

[0123] In terms of the defect detection rate, the larger the defect detection rate, the better the test excitation selection scheme. Therefore, the optimization objective function expression of the defect detection rate is:

[0124] g 2 (X) = 1 - fdr(X) (6)

[0125] Among them, fdr(X) represents the defect detection rate of the test excitation vector selection scheme. The defect coverage rate is equal to the number of detectable defects, defect, divided by the total number of injected defects, defect all , and its calculation formula is as follows:

[0126]

[0127] Therefore, the multi-objective function expression in this embodiment is as follows:

[0128]

[0129] S702: Generate the initial population.

[0130] The generation of the initial population is the primary step of the genetic algorithm, and its quality directly affects the effect of subsequent evolution. In practical applications, the initial population is usually generated by a random method. In this embodiment, H individuals X h = [x h,1 , x h,2 , …, x h,D are randomly generated, where h = 1, 2, …, H. Each individual represents a test excitation vector selection scheme. x h,d = 0 indicates that the d-th test excitation vector is not selected in the test excitation vector selection scheme corresponding to the individual, and x h,d = 1 indicates that the d-th test excitation vector is selected in the test scheme corresponding to the individual, where d = 1, 2, …, D, and D represents the number of test excitation vectors in the test excitation set E. The H randomly generated individuals form the initial population P.

[0131] S703: Set the iteration number t = 1.

[0132] S704: Generate a new population:

[0133] Perform selection, crossover, and mutation operations on the individuals in the population P to generate a new population Q.

[0134] Since each individual in this embodiment is a binary-encoded vector, single-point crossover method is adopted for individual crossover, and single-point mutation method is adopted for individual mutation.

[0135] S705: Merge populations:

[0136] Merge population P and population Q to obtain population S = P ∪ Q.

[0137] S706: Perform individual optimization selection based on Pareto optimality:

[0138] Calculate the B optimized objective function values corresponding to each individual in population S, determine the Pareto dominance relationship between any two individuals according to the optimized objective function values, count the number of times each individual is dominated, sort all individuals in ascending order of the number of times they are dominated, and select the first H individuals to form the optimized population P'.

[0139] S707: Determine whether the iteration number t < t max , t max represents the preset maximum number of iterations. If so, go to step S708; otherwise, go to step S709.

[0140] S708: Let the iteration number t = t + 1, let population P = P', and return to step S704.

[0141] S709: Obtain the optimized scheme of the test excitation vector:

[0142] Screen out the non-dominated individuals in the optimized population P' according to the Pareto dominance relationship, and select the test excitation vector selection schemes corresponding to these non-dominated individuals as an optimized scheme. It can be seen that by screening non-dominated individuals, the information required for decision-makers to make trade-offs among multiple objectives is provided.

[0143] To better illustrate the technical solution of the present invention, specific examples are used to experimentally verify the present invention. In this embodiment, the bandgap reference circuit provided by the IEEE P2427 working group is used to verify the feasibility of the present invention. Figure 8 is the structural diagram of the bandgap reference circuit in this embodiment. As Figure 8 shown, the bandgap reference circuit contains a total of 102 components, including 43 three-terminal components and 59 two-terminal components. The python scripting language and hspice simulation software are used to analyze in detail the generation of test excitations for the bandgap reference circuit.

[0144] According to the fault simulation framework described in the IEEE standard proposal, fault models were constructed for all components in the circuit. Open-circuit faults were simulated as 1 GΩ resistors in series with the faulty terminals, while short-circuit faults were modeled as 200 Ω resistors in parallel between the faulty terminals. There were a total of 376 complete faults. After redundant fault reduction, 340 faults were generated for the Bandgap circuit. After verification, 274 faults could be detected among the 340 faults using all test stimuli. That is, 66 faults were undetectable.

[0145] The IEEE bandgap reference circuit contains 3 excitation sources with a nominal value of 2.5 V, but in fact only two power supplies are actually connected to the circuit. Therefore, the voltage value range is limited to the interval [0, 2.5]. A 2D search space can be established. Using 12 MOS transistor gate nodes and 1 output node, a total of 13 nodes are used as measurement points. Table 1 shows the combined fault detection numbers corresponding to the initial points of Latin hypercube sampling and the four points of the first-round Bayesian optimization in this embodiment.

[0146]

[0147] Table 1

[0148] At this time, the historical excitation pool is empty. Therefore, the combined fault detection number is the fault detection number of the selected excitations. In this round, 8 excitations were selected, and (0, 1.9) had the most detectable faults. A total of 254 faults could be detected using these test vectors.

[0149] All the selected excitations in this round are added to the historical excitation pool. In the next round of Bayesian optimization, all excitations are combined with the excitations in the historical excitation pool and the combined fault detection number is evaluated, and so on until the expected fault detection number is reached.

[0150] In this experiment, the expected number of fault detections was 272 ( / 274). In the first round of Bayesian optimization, 8 excitations were evaluated, and a total of 254 faults were diagnosed, with a fault coverage rate of 74.7% and a detectable fault coverage rate of 92.7%. In the third round of Bayesian optimization, 16 excitations were evaluated, and a total of 256 faults were diagnosed, with a fault coverage rate of 75.3% and a detectable fault coverage rate of 93.4%. In the ninth round of Bayesian optimization, 60 excitations were evaluated, and a total of 269 faults were diagnosed, with a fault coverage rate of 79.1% and a detectable fault coverage rate of 98.2%. In the fifteenth round of Bayesian optimization, 64 excitations were evaluated, and a total of 272 faults were diagnosed, with a fault coverage rate reaching 80% and a detectable fault detection rate of 100%.

[0151] Although the above-described illustrative specific embodiments of the present invention have been described to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions made using the concept of the present invention are within the scope of protection.

Claims

1. A method for generating analog integrated circuit test stimuli based on multi-stage Bayesian optimization, characterized in that: The following steps are involved: S1: for the analog integrated circuit to be tested, all components in the circuit netlist are identified, fault models are established for all components except the power supply, and a fault list is generated, each fault model is equivalently compressed, and injected into the analog integrated circuit to be tested one by one to obtain a faulty simulated analog integrated circuit; S2: Establish an M-dimensional search space according to the number M of excitation sources of the analog integrated circuit to be tested and the voltage range of each excitation source; set the test excitation step size according to actual needs, and then discretize the search space to obtain the coordinates of each search grid point; S3: Sample D initial points start in the search space d , d = 1, 2, ..., D, in the analog integrated circuit for each initial point start d Perform fault simulation and record each initial point start d The set of detectable faults S4: Searching for a test stimulus set based on multi-stage Bayesian optimization, including the following steps: S4.1: Find D initial points start d The set of detectable faults The collection of is taken as the combined fault detection set F1, the number of detectable faults in the combined fault detection set F1 is taken as the combined fault detection number V1, and then the combined fault detection number V1 is taken as each initial point start d The objective function value of , thus obtaining the historical incentive set E1; S4.2: Set the proxy model according to actual needs and use the historical incentive set E1 to pre-train the proxy model; S4.3: Let Bayesian optimization round s = 1; S4.4: Perform the sth round of Bayesian optimization. The specific method is as follows: S4.4.1: Let search round r = 1; S4.4.2: Set the sampling function according to actual needs, in the historical stimulus set E s In the complement of s,r ; S4.4.3: Simulate the analog acquisition circuit to obtain the stimulus p s,r The detectable fault set f s,r ; Obtain the detectable fault set f s,r and the combined fault detection set F s The number of detectable faults in this collection is used as the stimulus p s,r The corresponding number of combined fault detections V s,r ; S4.4.4: Use incentive p s,r and its corresponding combined fault detection quantity V s,r Update the proxy model; S4.4.5: Determine whether r<R, where R represents the search round of each round of Bayesian optimization. If so, proceed to step S4.4.6, otherwise, this round of Bayesian optimization ends; S4.4.6: Set search round r = r + 1, and return to step S4.4.2; S4.5: Determine whether the Bayesian optimization end condition is met, if yes, proceed to step S4.6, otherwise proceed to step S4.8; S4.6: Obtain the R incentives p obtained by searching in this round of Bayesian optimization s,r The detectable fault set f s,r and the combined fault detection set F s The collection of s+1 , the number of detectable faults in this collection is taken as the combined fault detection number V s+1 ; Then the combined fault detection quantity V s+1 As the R incentives p searched in this round of Bayesian optimization s,r and historical incentive set E s The objective function value of the original incentive is obtained by s+1 ; S4.7: Let the Bayesian optimization round s = s + 1, and return to step S4.4; S4.8: Set the historical incentive set E S As the test stimulus set E for the final simulation circuit test.

2. The analog integrated circuit test stimulus generation method according to claim 1, characterized in that: In step S3, the initial point is sampled using the Latin hypercube sampling method.

3. The analog integrated circuit test stimulus generation method according to claim 1, characterized in that: The proxy model in step S4.2 adopts a Gaussian process model.

4. The analog integrated circuit test stimulus generation method according to claim 1, characterized in that: The sampling function in step S4.4.2 adopts an improved probability function.

5. The analog integrated circuit test stimulus generation method according to claim 1, characterized in that: The step S4.8 also includes the test stimulus optimization of the current test stimulus set E based on the Pareto genetic algorithm, and the specific method is: S4.8.1: Determine the optimization target of test stimulus selection according to actual needs, record the number of optimization targets as B, and set the optimization objective function g of the test stimulus selection scheme b (X), b = 1, 2, ..., B, the smaller the optimization objective function value, the better the test solution; S4.8.2: Randomly generate H individuals X h =[x h,1 ,x h,2 ,…,x h,D ], h = 1, 2, ..., H, each individual represents a test stimulus vector selection scheme, x h,d = 0 means that the dth test stimulus vector is not selected in the test stimulus vector selection scheme corresponding to the individual, x h,d =1 indicates that the dth test stimulus vector is selected in the test scheme corresponding to the individual, d=1,2,…,D, D indicates the number of test stimulus vectors in the test stimulus set E; the randomly generated H individuals constitute the initial population P; S4.8.3: Set the number of iterations t = 1; S4.8.4: Perform selection, crossover, and mutation operations on individuals in population P to generate a new population Q; S4.8.5: Merge population P and population Q to obtain population S = P ∪ Q; S4.8.6: Calculate the B optimization objective function values ​​corresponding to each individual in the population S, determine the Pareto dominance relationship between any two individuals based on the optimization objective function values, count the number of times each individual is dominated, sort all individuals from small to large according to the number of times they are dominated, and select the top H individuals to form the optimal population P′; S4.8.7: Determine whether the number of iterations t < t max , t max Indicates the preset maximum number of iterations. If yes, proceed to step S4.8.8, otherwise proceed to step S4.8.9; S4.8.8: Let the number of iterations t = t + 1, let the population P = P′, and return to step S4.8.4; S4.8.9: According to the Pareto dominance relationship, select the non-dominated individuals in the preferred population P′, and use the test excitation vector selection scheme corresponding to these non-dominated individuals as a preferred scheme.

6. The method for generating analog circuit test stimulus according to claim 5, characterized in that: The optimization objective function in step S4.8.1 includes the optimization objective function of the number of test excitation vectors and the optimization objective function of the defect detection rate, wherein the optimization objective function expression of the number of test excitation vectors is: Where X = [x1, x2, …, x D ] represents the test stimulus vector selection scheme, x d is a binary variable, x d = 0 means that the dth test stimulus vector is not selected in the test stimulus vector selection scheme corresponding to the individual, x d =1 indicates that the dth test stimulus vector is selected in the test scheme corresponding to the individual, d=1,2,…,D, D indicates the number of test stimulus vectors in the test stimulus set E; The optimization objective function expression of defect detection rate is: g2(X)=1-fdr(X) Where fdr(X) represents the defect detection rate of the test stimulus vector selection scheme.

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