A power network reserved low-layer metal wiring resource alleviating on-chip voltage drop method

Abstract

The application aims to provide a power network reserved low-layer metal wiring resource alleviating on-chip voltage drop method, which comprises the following steps: reserving a deployment area of a low-layer metal resource in a chip layout stage; correcting the deployment area; and using the metal resource in the deployment area according to chip analysis results after wiring is completed. In the layout and wiring and clock tree synthesis stages, the low-layer metal wiring resource is reserved for connecting the power supply tracks of adjacent standard cells, so that the problem of excessive voltage drop caused by excessive low-layer metal resistance can be effectively alleviated by flexibly enabling the reserved wiring resource in the late stage of chip design.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a method for relieving on-chip voltage drop by reserving low-layer metal wiring resources of a power network. BACKGROUND

[0002] In modern integrated circuit design, with the continuous increase of chip complexity and the continuous miniaturization of process technology, power integrity problems have gradually become a major challenge in design. In particular, in the late-stage full-chip voltage drop (IR drop) analysis of a chip, it is often found that the resistance of the low-layer metal wiring is large, resulting in a voltage drop exceeding the design specification. If this problem is not solved in time, it may cause performance degradation, functional failure or even failure to work normally of the chip. With the continuous development of integrated circuit technology, voltage drop has become a problem that must be considered in the design of a chip power line network. Studies have shown that a 5% voltage drop will result in more than 15% cell delay.

[0003] In the existing design process, when the low-layer metal wiring resources are exhausted and the voltage drop exceeds the standard, the methods commonly used include the following: replacing standard cell types: selecting standard cells with lower current consumption or higher driving capability. However, this method may affect other design parameters such as area and delay. Reducing standard cell density: reducing local current consumption by reducing cell density, but this will increase the chip area and affect performance. Inserting decoupling capacitors: relieving dynamic voltage drop by increasing the number and density of decoupling capacitors in critical areas, but this method is often limited by area in the original standard cell-intensive critical modules, or the decoupling capacitor itself cannot meet the demand for capacitance density. Optimizing the power network: such as thickening the high-layer metal wiring or adding additional power network resources, but often subject to process design rules, and cannot fully optimize the low-layer power wiring.

[0004] The above methods all have significant design costs, especially in the late stage of chip design, modifying these contents may require re-layout and routing and multiple iterations of verification. This not only increases the design complexity and time cost, but also may seriously affect the on-time delivery of the chip. As can be seen, in the traditional design process, due to the power integrity problem, high-cost and high-risk operations such as standard cell replacement, reduced cell density or re-layout and routing are required. The chip improvement method of the prior art is greatly limited, the yield is not high, and the design is very complex. SUMMARY

[0005] The application aims to provide a power network reserved low-layer metal wiring resource alleviating on-chip voltage drop method, which reserves low-layer metal wiring resources for connecting adjacent standard cell power tracks in the layout wiring and clock tree synthesis stage, so as to effectively alleviate the problem of excessive voltage drop caused by excessive low-layer metal resistance by flexibly enabling these reserved wiring resources in the late stage of chip design.

[0006] A power network reserved low-layer metal wiring resource alleviating on-chip voltage drop method, comprising:

[0007] Reserving a deployment area of bottom metal resources in the chip layout stage;

[0008] Correcting the deployment area;

[0009] Using the metal resources in the deployment area according to the chip analysis results after wiring completion.

[0010] Preferably, the deployment area of bottom metal resources reserved in the chip layout stage comprises:

[0011] In the chip layout stage, the chip power consumption is analyzed;

[0012] According to the analysis results, the high-voltage drop area with relatively obvious voltage drop is taken as a marked area;

[0013] In the marked area, short metals for shorting standard cell power tracks are added in the low-layer metal layer according to a preset density and arrangement mode;

[0014] The layout is subjected to physical design rule checking.

[0015] Preferably, the correction of the deployment area comprises:

[0016] In the clock tree synthesis stage, the marked area is corrected through flip rate file or global flip rate power consumption distribution analysis;

[0017] In the corrected marked area, the short metals for shorting standard cell power tracks are optimized according to the specified density and arrangement mode;

[0018] The layout is subjected to physical design rule checking to remove the parts causing physical design rule violations.

[0019] Preferably, the use of the metal resources in the deployment area according to the chip analysis results after wiring completion comprises:

[0020] After wiring completion, the chip is subjected to voltage drop analysis using a voltage drop signature tool;

[0021] According to the voltage drop analysis results, high-resistance and high-voltage drop violation points located in the metal layer and the lower metal layer of the reserved short metal are screened out.

[0022] According to the violation point search available reservation short metal, and by making a hole between the short metal and the lower standard cell power supply track to establish an actual physical connection, the local metal resistance is reduced;

[0023] After the dynamic connection is completed, a physical design rule check is performed, and the newly added violations generated in the connection process are removed.

[0024] Preferably, after the metal resources are used in the deployment area according to the chip analysis results after the routing is completed, the chip is further evaluated, specifically:

[0025] After the dynamic connection is completed, a voltage drop signature tool is run to analyze the corrected voltage drop distribution, quantify the voltage drop improvement effect, and record the specific benefits;

[0026] Supplementary repair of remaining voltage drop violations;

[0027] After all optimization steps are completed, a final voltage drop signature is performed on the whole chip to verify the stability and design reliability of the overall power network.

[0028] Preferably, the physical design rule check of the layout includes:

[0029] Defining the core area and the peripheral area of the chip;

[0030] Verifying whether the power supply planning and IO planning of the peripheral area are qualified;

[0031] Verifying whether the timing and logic of the core area are qualified;

[0032] Verifying whether the areas of the core area and the peripheral area are qualified.

[0033] Preferably, the high voltage drop area with relatively obvious voltage drop according to the current distribution is used as a marked area, including:

[0034] Calculating the voltage drop standard parameter according to the working condition of the chip;

[0035] Comparing the voltage drop of each area in the chip with the voltage drop standard parameter;

[0036] If the positive difference between the voltage drop of the area and the voltage drop standard parameter exceeds a threshold value, the current area is used as a marked area.

[0037] Preferably, the chip power consumption analysis in the chip layout stage includes:

[0038] The average power consumption of the current standard cell is calculated according to the number of input pins and output pins, the energy consumption of the input pins and output pins, the frequency of input and output signal state changes, and the capacitance of the output pins.

[0039] The average current is calculated according to the average power consumption.

[0040] A power network reserved low-layer metal routing resource alleviates on-chip voltage drop system, comprising:

[0041] A reserved area deployment module is configured to reserve a deployment area of the low-layer metal resource in a chip layout stage.

[0042] A reserved area correction module is configured to correct the deployment area.

[0043] A reserved area enabling module is configured to use the metal resource in the deployment area according to chip analysis results after routing is completed.

[0044] An electronic device, comprising a chip, a processor and a memory, the memory is configured to store computer program code, the computer program code comprises computer instructions, when the chip executes the computer instructions, the electronic device executes the power network reserved low-layer metal routing resource alleviates on-chip voltage drop method.

[0045] The beneficial effects of the present application are as follows: 1. The present application effectively reserves low-layer metal routing resources for connecting adjacent standard cells, and flexibly enables these resources according to actual voltage drop analysis results in the later stage; 2. The present application can improve the chip voltage drop problem and improve the robustness and reliability of the power supply network without changing the original design, and ensure the chip design progress; 3. The present application can avoid the high-cost and high-risk operations such as standard cell replacement, reducing cell density or re-layout and wiring due to power integrity problems in the traditional design process, effectively improve the flexibility, reliability and delivery efficiency of chip design, and reduce the risk of design iteration. BRIEF DESCRIPTION OF DRAWINGS

[0046] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the application.

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0048] Figure 1 A low-layer metal wiring resource reserved power network method flow chart for the present application;

[0049] Figure 2 A final implementation structure schematic diagram for the present application;

[0050] Figure 3 A hardware structure schematic diagram of an electronic device for the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0052] It should be noted that all directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings). If the certain posture changes, the directionality indications also change accordingly.

[0053] In addition, the descriptions involving “first”, “second” and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as “first” and “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of those skilled in the art. When the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0054] Modifying these contents in the late stage of chip design may require re-layout and multiple iteration verifications. This not only increases the design complexity and time cost, but also may seriously affect the on-time delivery of the chip. As can be seen, in the traditional design process, high-cost and high-risk operations such as standard cell replacement, reducing cell density or re-layout are required due to power integrity problems. The chip improvement method of the prior art is greatly limited, the yield is not high, and the design is very complex.

[0055] The application can effectively reserve low-layer metal wiring resources, connect the power tracks of adjacent standard cells, and flexibly enable these resources according to actual voltage drop analysis results; the application can improve the chip voltage drop problem and the robustness and reliability of the power supply network in a way of minimizing the cost without changing the original design, and ensure the chip design progress; the application can avoid the high-cost and high-risk operations such as standard cell replacement, reduced cell density or re-layout and wiring due to power integrity problems in the traditional design process, effectively improve the flexibility, reliability and delivery efficiency of chip design, and reduce the risk of design iteration.

[0056] Embodiment 1

[0057] A power network reserved low-layer metal wiring resource alleviates the on-chip voltage drop method, referring to Figure 1 , comprising:

[0058] S100, reserving a deployment area of a bottom metal resource in a chip layout stage;

[0059] The chip layout stage includes the following steps: layout planning: the designer places large functional modules in different areas of the chip, determines the connectivity, and determines which module should be placed next to. In this stage, the module has a boundary that divides the entire chip area into coarse partitions, and then places the standard cell as a defined module in each boundary. Layout: determine the physical location of each module. This step is similar to the architect converting the architectural design drawing into the actual building layout, and the engineer designs the physical structure of the chip according to the optimized circuit logic layout, including the location and connection of each logic gate. Wiring: connect the connections between modules. This step ensures that the density distribution inside the chip is reasonable, and the connection between all modules is correct. Density optimization: ensure that the density distribution inside the chip is reasonable, and avoid waste of space or poor connection. DRC / LVS check: perform physical design rule check (DRC) and layout and circuit verification (LVS) to ensure that the physical structure of the design meets the design specification and is consistent with the circuit description.

[0060] S200, correcting the deployment area;

[0061] The deployment area marked in the first step includes most of the high-voltage drop risk areas, but there will still be some high-voltage drop areas that are not identified or misidentified, so the deployment area needs to be corrected to further reduce the risk area range and save the chip area.

[0062] S300, using metal resources in the deployment area according to the chip analysis results after wiring is completed.

[0063] The embodiment of the present application provides a method for improving voltage drop in chip design process, in particular, reserving low layer metal wiring resources for connecting power supply tracks of adjacent standard cells in the layout and routing and clock tree synthesis stage, so that the voltage drop exceeding problem caused by excessive low layer metal resistance can be effectively relieved by flexibly enabling the reserved wiring resources in the late chip design stage. The method can avoid the high-cost and high-risk operations such as standard cell replacement, reducing cell density or re-layout and routing due to power integrity problems in the traditional design process, effectively improves the flexibility, reliability and delivery efficiency of chip design, and reduces the risk of design iteration.

[0064] Preferably, S100, the deployment area of the reserved low layer metal resource in the chip layout stage includes:

[0065] S110, analyzing the chip power consumption in the chip layout stage;

[0066] With the improvement of chip integration, the power supply system design becomes a challenge, and the chip with high power consumption needs more complex power supply network to stabilize the power supply, otherwise it will affect the stability and working frequency of the chip. The chip power consumption mainly includes the following two parts: static power consumption: including leakage power consumption and sub-threshold current. Leakage power consumption is the power consumption caused by non-ideal leakage current, such as the small current when the MOS tube is off; the sub-threshold current is the micro leakage current between the source and the drain of the CMOS tube in the cut-off state; dynamic power consumption: including internal power consumption and flip power consumption. Internal power consumption is the power consumption caused by the charging and discharging of the transistor load; flip power consumption is the power consumption generated by the transistor load when the signal flips. The chip power consumption can reflect the voltage drop of the current cell, so by analyzing the chip power consumption, it can be judged which area has high voltage drop risk.

[0067] In the embodiment of the present application, in the layout (Place) stage, the power consumption distribution of the whole chip is analyzed by using the flip rate file (Activity Factor File) or the set global flip rate. By analyzing the current density and the load condition of the power supply track, the area with high voltage drop is identified. These areas are usually located in the area with high cell density or high clock switching frequency, which is the potential weak point of the power supply network.

[0068] S120, according to the analysis result, the high voltage drop area with relatively obvious voltage drop is taken as a marked area;

[0069] The present application identifies the potential high voltage drop area with relatively obvious voltage drop according to the current distribution. These areas will be the key wiring areas of the reserved resources.

[0070] S130, in the marked area, short metals for shorting the power supply tracks of standard cells are added in the low layer metal layer according to the preset density and arrangement mode.

[0071] The present application adds short metals of shorted standard cell power tracks in the low layer metal in the identified focus area according to the specified density and arrangement. These short metals are designed in unconnected state for flexible adjustment in the subsequent stage.

[0072] S140, performing physical design rule check on the layout.

[0073] The present application performs physical design rule check (DRC) after the short metal arrangement is completed. For short metals that do not meet the process design rules (such as close spacing or wiring conflict), adjustment or deletion is adopted to correct them, ensuring that the layout meets the process requirements and legality.

[0074] Preferably, S200, the correction deployment area includes:

[0075] S210, in the clock tree synthesis stage, the marked area is corrected by flip rate file or global flip rate for power consumption distribution analysis;

[0076] The present application further analyzes the power consumption distribution in the clock tree synthesis (CTS) stage, and corrects the reserved area identified in the layout stage to ensure that these areas more accurately reflect the potential high voltage drop risk.

[0077] S220, in the corrected marked area, the short metal of the shorted standard cell power track is optimized according to the specified density and arrangement;

[0078] The present application supplements or optimizes the short metal of the shorted standard cell power track in the corrected area according to the specified density and arrangement, and further improves the reserved arrangement of the low layer metal resource. The present application can design the short metal connection on the low layer metal according to the identified area, and the short metal is used for shorting the adjacent standard cell power track. The short metal is arranged in a specific density and arrangement, such as regular grid or array arrangement, to ensure the coverage and uniformity of the resource. The short metal is not actually connected in the layout stage, but only serves as a reserved resource.

[0079] S230, performing physical design rule check on the layout to remove the part that causes physical design rule violation.

[0080] Again, the layout is checked by DRC, and for the newly added or adjusted short metal, the part causing the violation of physical design rules is removed to ensure the legality of the layout. Because each adjustment of the circuit or layout may bring new violations, if the physical design rule check is not performed after modification, multiple modifications may lead to errors in the entire circuit or layout that are difficult to correct by ordinary correction. If the physical design rule check is performed after each modification, not only the area of each modification is small, but also the error rate of the chip is low, and the modification is easier.

[0081] Preferably, S300, after the wiring is completed, the metal resources are used in the deployment area according to the chip analysis result, including:

[0082] S310, after the wiring is completed, the chip is analyzed by using a voltage drop signature tool;

[0083] The present application uses a voltage drop (IR Drop) signature tool to perform accurate voltage drop analysis on the chip after the wiring is completed.

[0084] S320, according to the voltage drop analysis result, a high-resistance and high-voltage drop violation point located in the metal layer and the lower metal layer of the reserved short metal is screened out;

[0085] The present application combines the analysis results of the resistance and current distribution of each layer to screen out a high-resistance and high-voltage drop violation point located in the metal layer and the lower metal layer of the reserved short metal.

[0086] S330, according to the violation point, the available reserved short metal is searched, and the actual physical connection is established by punching a via between the short metal and the lower standard cell power rail to reduce the local metal resistance;

[0087] The present application searches for the reserved short metal meeting the conditions in the area of the violation point, connects the short metal with the lower standard cell power rail in the form of a via, thereby forming an actual low-resistance power supply path to reduce the local voltage drop. And the reserved short metal closest to the violation point is preferentially selected to ensure the best effect.

[0088] S340, after the dynamic connection is completed, a physical design rule check is performed to remove the newly added violations generated in the connection process.

[0089] After the dynamic connection is completed, the DRC check is performed again to remove the short metal causing the violation in the connection to ensure the legality of the final layout.

[0090] Preferably, after the wiring is completed and the metal resources are used in the deployment area according to the chip analysis result, reference is made to Figure 2 It also includes S400, evaluating the chip, specifically:

[0091] S410, after the dynamic connection is completed, a voltage drop signature tool is run to analyze the corrected voltage drop distribution, quantify the voltage drop improvement effect, and record the specific benefits;

[0092] After the dynamic connection is completed, the voltage drop (IR Drop) signature tool is re-run to analyze the corrected voltage drop distribution, quantify the voltage drop improvement effect, and record the specific benefits. The voltage drop (IR Drop) signature tool can accurately analyze the voltage drop of the whole chip power supply network, analyze the metal resistance, current distribution and voltage drop layer by layer, and screen out the violation points related to the low layer metal resistance.

[0093] S420, supplement repair of the remaining voltage drop violations;

[0094] For the remaining voltage drop violations, other traditional methods (such as replacing standard cells or local routing optimization) are used for supplementary repair to ensure that the chip meets the design specifications.

[0095] S430, after all optimization steps are completed, the whole chip is subjected to final voltage drop signature, to verify the stability and design reliability of the overall power supply network.

[0096] After all optimization steps are completed, the whole chip is subjected to final voltage drop signature, to ensure the stability and design reliability of the overall power supply network.

[0097] Preferably, S140, the physical design rule check of the layout includes:

[0098] Physical design rules include: Layout rules: including metal line spacing, minimum feature size, transistor channel length, etc. These rules are set according to the capabilities and limitations of the manufacturing process to ensure that the circuit can be accurately manufactured. Wiring rules: involving the layout rules between metal lines and multiple layers of metal in the circuit, such as the width, spacing, and layer spacing of metal lines. These rules aim to ensure that the wiring layout of the circuit meets the requirements of signal transmission and electrical characteristics, while also taking into account the limitations of the manufacturing process. Spacing rules: refer to the spacing requirements between different elements or different metal layers to avoid accidental electrical contact or electrical short circuit between elements or metal lines in the circuit. Filling rules: refer to the filling requirements for some blank areas in the circuit layout to ensure the flatness and stability during the manufacturing process. Device rules: involving the layout and size rules of transistors, capacitors, resistors, etc. to ensure that they can work normally and can be accurately manufactured.

[0099] S141, define the core area and peripheral area of the chip;

[0100] Core area refers to the area inside the chip where basic elements such as logic gates, flip-flops, etc. are placed. It is the "brain" of the chip, responsible for performing main calculations and processing tasks. Core area usually contains central processing units (CPUs), graphics processing units (GPUs), and other key components that work together to achieve the main functions of the chip. Peripheral area is used to place auxiliary elements such as input / output (I / O) interfaces, power and ground pins, etc. These components are responsible for communication and data exchange between the chip and the outside world, ensuring that the chip can effectively interact with other devices or systems. Peripheral area usually includes I / O pads, power rings, power pads, etc.

[0101] S142, verify whether the power planning and IO planning of the peripheral area are qualified;

[0102] The main purpose of power planning is to design a uniform power supply network for the chip to ensure that all parts of the chip can obtain stable power supply. The specific steps include: power network setting: establish a power supply network, including the setting of power ring lines and power strip lines. Power ring lines surround the core area of the chip to ensure uniform distribution of current; power strip lines are distributed along the edges of the chip to provide additional current paths. Digital and analog mixed power supply: handle the power supply needs of digital circuits and analog circuits to ensure that they do not interfere with each other. Single power supply and multi-power supply: choose the appropriate power supply method according to the design requirements, and multi-power supply can provide more flexible current management. Power budget: quantitative calculation through power consumption analysis means to ensure the stability and efficiency of the power supply network.

[0103] IO planning mainly involves the layout and power supply design of input / output units (I / O units). The specific steps include: I / O unit layout: comprehensively consider the printed board wiring, packaging form, power supply situation and internal module structure to ensure that I / O units can efficiently communicate with external devices. Power supply design: the ratio of the number of I / O units supplied to the number of output signal ports is usually 1:(5~10). Pin assignment: output signal lines are connected to block pins, and connections between blocks are realized through internal pins. The pin determines the position of the pad, which is usually at the edge of the chip.

[0104] S143, verify whether the timing and logic of the core area are qualified;

[0105] S144, verify whether the area of the core area and the peripheral area is qualified.

[0106] Design rule check (DRC) is an important step in integrated circuit design to verify whether the design layout meets the requirements of manufacturing process. Physical design rules refer to a series of rules and constraints in IC design that specify circuit layout to ensure that the circuit can be accurately manufactured.

[0107] With the continuous shrinking of chip node size, a large number of complex design rules make the accuracy of DRC checking not high, in the embodiment of the application, sampling based on the neural network model optimizes the DRC checking, so that the speed of DRC checking is faster and the accuracy is higher.

[0108] In the neural network, a plurality of detection branches are set for detecting different DDRC rules. Con4_3, fc7, Con6_2, Con7_2, Con8_2 and Con9_2 are selected as multi-scale detection branches, and each detection branch is respectively outputted by a group of 3x3 convolutional networks to output classification probability and position coordinates. The ratio of the area of the detection frame under the kth detection branch to the area of the chip picture is represented as:

[0109] ;

[0110] Among them, and respectively represent the area ratio of the detection frame on the Con4_3 and Con9_2 detection branches, is 0.2, is 0.9, and m is the number of detection branches.

[0111] Suppose the input feature map size is c x h x w, the detection category is C, and the detection frame category is p. Each detection branch will output positioning information with a size of 4p x h x w and classification information with a size of C x p x h x w. The loss function is represented as:

[0112] ;

[0113] Among them, g represents the real frame, c is the confidence, represents the predicted frame, is the positioning loss, N is the number of feature maps, and x is the predicted value. is the cross-entropy loss function under multi-classification, which is represented as:

[0114] ;

[0115] Among them, is used to explain whether the detection frame i and the real frame j match successfully on the category p, when the intersection over union (IoU) is greater than 0.5, equals 1, at this time the detection frame i is a positive sample, represented as pos, otherwise is 0, the detection frame is a negative sample, represented as Neg, is the confidence of the pth category, then the confidence of the negative sample is.

[0116] Preferably, S120 includes the high-voltage drop region with relatively obvious voltage drop as a marked region according to the current distribution;

[0117] S121 calculates a standard voltage drop parameter according to the working condition of the chip;

[0118] ‌The standard voltage drop of the chip refers to the voltage loss caused by the interaction of resistance and current in the power supply network when the chip is working. Specifically, when the current flows through the power supply network with resistance, according to Ohm's law (V=I*R), voltage loss will occur, which is voltage drop.‌

[0119] S122 compares the voltage drop of each region in the chip with the standard voltage drop parameter;

[0120] The main reason for the standard voltage drop of the chip is the product effect of resistance and current in the power supply network. Inside the chip, the power supply and ground are distributed through metal layers, and each metal layer has a certain resistivity. When the current flows through these metal layers, voltage drop will occur. In the embodiment of the application, by calculating the voltage drop of each region, and then comparing the voltage drop of each region with the standard voltage drop, it can be planned which region is a high-risk high-voltage drop region.

[0121] S123, if the positive difference between the voltage drop of the region and the standard voltage drop parameter exceeds the threshold value, the current region is marked as a marked region.

[0122] The positive difference indicates that the voltage drop of the current region is greater than the standard voltage drop parameter. If the positive difference between the voltage drop of the current region and the standard voltage drop parameter exceeds the threshold value, it means that the current region is a high-voltage drop region, which has a high risk of functional failure, and the current region should be marked.

[0123] Preferably, in the chip layout stage, the power consumption of the chip is analyzed, including:

[0124] The average power consumption of the current standard unit is calculated according to the number of input pins, the number of output pins, the energy consumption of the input pins and the output pins, the frequency of input and output signal state changes, and the capacitance of the output pins;

[0125] The average power consumption is expressed as:

[0126] ;

[0127] Wherein, x is the number of input pins, y is the number of output pins; is the energy consumption corresponding to the i-th input pin, is the energy consumption corresponding to the n-th output pin; is the frequency of the i-th input signal state change, the frequency of the nth output signal state change; the capacitance of the nth output pin, VDD is the power supply voltage.

[0128] The average current is calculated according to the average power consumption.

[0129] The average current is expressed as:

[0130] ;

[0131] Embodiment 2

[0132] A power network reserved low-layer metal wiring resource alleviates on-chip voltage drop system, comprising:

[0133] The reserved area deployment module is configured to reserve a deployment area of the low-layer metal resource in a chip layout stage.

[0134] The reserved area correction module is configured to correct the deployment area.

[0135] The reserved area enabling module is configured to use the metal resource in the deployment area according to a chip analysis result after the wiring is completed.

[0136] Embodiment 3

[0137] An electronic device, comprising a chip, a processor and a memory, the memory is configured to store computer program code, the computer program code comprises computer instructions, and the electronic device executes a power network reserved low-layer metal wiring resource alleviates on-chip voltage drop method when the chip executes the computer instructions.

[0138] Reference Figure 3 The electronic device 2 comprises a processor 21, a memory 22, an input device 23 and an output device 24. The processor 21, the memory 22, the input device 23 and the output device 24 are coupled through a connector, which comprises various interfaces, transmission lines or buses, etc., and the embodiments of the present application do not make any limitation on this. It should be understood that in various embodiments of the present application, coupling means mutual contact in a specific way, including direct connection or indirect connection through other devices, for example, connection through various interfaces, transmission lines, buses, etc.

[0139] The processor 21 can be one or more graphics processing units (GPUs), and in the case that the processor 21 is a GPU, the GPU can be a single-core GPU or a multi-core GPU. Alternatively, the processor 21 can be a processor group composed of multiple GPUs, and the multiple processors are coupled with each other through one or more buses. Alternatively, the processor can also be other types of processors, etc., and the embodiments of the present application do not make any limitation on this.

[0140] The memory 22 can be used to store computer program instructions, and various kinds of computer program codes including program codes for executing the schemes of the present application. Optionally, the memory includes, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read only memory (EPROM), or a compact disc read-only memory (CD-ROM), which is used for relevant instructions and data.

[0141] The input device 23 is used for inputting data and / or signals, and the output device 24 is used for outputting data and / or signals. The output device 24 and the input device 23 can be independent devices, or can be an integral device.

[0142] The present application can effectively reserve low-layer metal wiring resources for connecting the power supply tracks of adjacent standard cells, and flexibly enable these resources according to actual voltage drop analysis results in the later stage. The present application can improve the chip voltage drop problem and enhance the robustness and reliability of the power supply network in a way of minimizing the cost without changing the original design, and ensure the chip design progress. The present application can avoid the high-cost and high-risk operations such as standard cell replacement, reducing cell density or re-layout and routing due to power integrity problems in the traditional design process, effectively improve the flexibility, reliability and delivery efficiency of chip design, and reduce the risk of design iteration.

[0143] The above description is only a specific implementation of the present application, which enables those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features applied herein.

Claims

1. A method for mitigating on-chip voltage drop by reserving low-level metallic wiring resources in a power network, characterized in that, Comprise: S1, reserving a deployment area of bottom metal resources in the chip layout stage; Specifically comprising: In the chip layout stage, analyzing the chip power consumption; According to the analysis result, taking the high voltage drop area with relatively obvious voltage drop as a marked area; In the marked area, adding short metal of short connection standard cell power supply track in the low layer metal layer according to the preset density and arrangement mode; Physical design rule checking is performed on the layout; According to the current distribution, the high voltage drop area with relatively obvious voltage drop is taken as the marked area, comprising: Calculating the voltage drop standard parameter according to the working condition of the chip; Comparing the voltage drop of each area in the chip with the voltage drop standard parameter; If the positive difference between the voltage drop of the area and the voltage drop standard parameter exceeds the threshold value, the current area is taken as the marked area; The chip power consumption is analyzed in the chip layout stage, comprising: Equivalent each standard cell to a constant current source, calculate the average power consumption of the current standard cell according to the number of input and output pins, the energy consumption of input and output pins, the frequency of input and output signal state change and the capacitance of output pin; According to the average power consumption, the average current is calculated; S2, correcting the deployment area; specifically comprising: In the clock tree synthesis stage, the marked area is corrected by power consumption distribution analysis through flip rate file or global flip rate; In the corrected marked area, the short metal of short connection standard cell power supply track is optimized according to the specified density and arrangement mode; Physical design rule checking is performed on the layout, and the part causing physical design rule violation is removed; S3, using the metal resources in the deployment area according to the chip analysis result after routing is completed.

2. The method for mitigating on-chip voltage drop by reserving low-level metallic wiring resources in a power network according to claim 1, characterized in that, The metal resources in the deployment area are used according to the chip analysis result after routing is completed, comprising: After routing is completed, voltage drop analysis is performed on the chip by using voltage drop signature tool; According to the voltage drop analysis result, high resistance and high voltage drop violation points located in the metal layer and the lower metal layer of the reserved short metal are screened out; According to the violation points, the available reserved short metal is searched, and the actual physical connection is established by punching through the via between the short metal and the lower standard cell power supply track, so as to reduce the local metal resistance; After dynamic connection is completed, physical design rule checking is performed to remove the new violations generated in the connection process.

3. The method for mitigating on-chip voltage drop by reserving low-level metallic wiring resources in a power network according to claim 1, characterized in that, After the metal resources in the deployment area are used according to the chip analysis result after routing is completed, the chip is further evaluated, specifically: After dynamic connection is completed, run the voltage drop signature tool to analyze the corrected voltage drop distribution, quantify the voltage drop improvement effect, and record the specific benefits; Supplementary repair of the remaining voltage drop violation; After completing all optimization steps, the final voltage drop signature is performed on the whole chip to verify the stability and design reliability of the overall power supply network.

4. A method for mitigating on-chip voltage drop by reserving low-level metallic wiring resources in a power network according to claim 1, characterized in that, The physical design rule checking on the layout comprises: Defining the core area and the peripheral area of the chip; Verify whether the power supply planning and IO planning of the peripheral area are qualified; Verify whether the timing and logic of the core area are qualified; Verify whether the area of the core area and the peripheral area is qualified.

5. A power network reserving low level metal routing resource alleviating on-chip voltage drop system, characterized in that, Comprise: A reserved area deployment module is configured to reserve a deployment area of underlying metal resources in a chip layout stage. A reserved area correction module is configured to correct the deployment area. A reserved area enabling module is configured to use the metal resources in the deployment area according to chip analysis results after routing is completed. The deployment area of the underlying metal resources in the chip layout stage includes: In the chip layout stage, chip power consumption is analyzed. According to the analysis results, a high-voltage-drop area with relatively obvious voltage drop is taken as a marked area. In the marked area, short metals of shorted standard cell power tracks are added in a low-level metal layer according to a preset density and arrangement manner. A layout is subjected to a physical design rule check. The correction of the deployment area includes: In a clock tree synthesis stage, a marked area is corrected through a flip rate file or global flip rate for power consumption distribution analysis. In the corrected marked area, short metals of shorted standard cell power tracks are optimized according to a specified density and arrangement manner. The layout is subjected to a physical design rule check, and parts causing physical design rule violations are removed. The high-voltage-drop area with relatively obvious voltage drop according to current distribution includes: A voltage drop standard parameter is calculated according to chip working conditions. Voltage drops of various areas in a chip are compared with the voltage drop standard parameter. If a positive difference between the voltage drop of an area and the voltage drop standard parameter exceeds a threshold value, the current area is taken as a marked area. The analysis of chip power consumption in the chip layout stage includes: Each standard cell is equivalent to a constant current source, and average power consumption of a current standard cell is calculated according to the number of input pins and output pins, energy consumption of the input pins and the output pins, frequency of input and output signal state changes, and capacitance of the output pins. Average current is calculated according to the average power consumption.

6. An electronic device, comprising: It includes: A chip, a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, when the chip executes the computer instructions, the electronic device executes a power network reserved low-level metal routing resource alleviating on-chip voltage drop method as claimed in any one of claims 1 to 4.

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