Storage health test method and memory

Abstract

The invention relates to the technical field of semiconductor testing, in particular to a storage health testing method and a memory, and the storage health testing method comprises the steps: obtaining a to-be-tested storage block; obtaining at least one address combination from the to-be-tested storage block, and selecting a target address combination from the at least one address combination; wherein each address combination comprises a plurality of test addresses, the plurality of test addresses are uniformly distributed in the storage block to be tested, and the test addresses in different address combinations are different; and performing a storage health test based on the target address combination. Test addresses are obtained in the storage block based on the address combination, and the test addresses are uniformly distributed in the storage block to ensure that a test result of a single test has accuracy; in addition, the test addresses in different address combinations are different, so that the storage block can support multiple tests of the same test item.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and particularly relates to a memory health testing method and a memory. Background Art

[0002] The purpose of Memory Health (MH) testing is to evaluate the reliability of wafer-level memory cells, mainly focusing on the service life and data reliability of the memory cells.

[0003] In memory health testing, a certain memory stress is applied to cause a corresponding degree of fatigue to detect the product performance; for memory cells, the memory stress is destructive. Therefore, memory health testing requires as many addresses as possible for different test items.

[0004] For MH testing, current MH testing includes at least six test items, and different memory banks support different test items. A full bank can only perform partial tests; in order to avoid the damage of memory stress to memory cells, when performing multiple tests on the same test item, it is necessary to replace the memory bank for execution, and the memory performance differences between different memory banks will affect the accuracy of the test results. Summary of the Invention

[0005] The main purpose of this application is to provide a memory health testing method and a memory, at least enabling a memory bank to support multiple tests of the same test item.

[0006] To achieve the above object, a first aspect of this application proposes a memory health testing method, including: obtaining a memory bank to be tested; obtaining at least one address combination in the memory bank to be tested, and selecting a target address combination from the at least one address combination; wherein, each address combination includes multiple test addresses, and the multiple test addresses are evenly distributed in the memory bank to be tested, and the test addresses in different address combinations are different; performing a memory health test based on the target address combination.

[0007] In some embodiments, the method for obtaining at least one address combination corresponding to the memory bank to be tested includes: dividing the memory bank to be tested into regions to obtain multiple address regions; obtaining at least one of the test addresses in each address region; different combinations of the test addresses in each address region form different address combinations.

[0008] In some embodiments, the address regions evenly divide the memory bank to be tested.

[0009] In some embodiments, the method of partitioning the storage block to be tested to obtain multiple address regions includes: partitioning the regions based on a preset number of word lines or bit lines in the storage block to be tested.

[0010] In some embodiments, the method of partitioning the storage block to be tested to obtain multiple address regions includes: performing a first region partitioning based on a first preset number of word lines in the storage block to be tested; performing a second region partitioning based on a second preset number of bit lines in the storage block to be tested; and obtaining the address regions based on the results of the first region partitioning and the second region partitioning.

[0011] In some embodiments, the method of obtaining at least one test address in each address region includes: obtaining a word line selection signal and a bit line selection signal; obtaining the word line address corresponding to the test address in each address region based on the result of the first region partitioning and the word line selection signal, where the word line selection signals corresponding to different results of the first region partitioning are different; and obtaining the bit line address corresponding to the test address in each address region based on the result of the second region partitioning and the bit line selection signal, where the bit line selection signals corresponding to different results of the second region partitioning are different.

[0012] In some embodiments, in any address combination, the word line positions and bit line positions of the address regions where each test address is located are different.

[0013] In some embodiments, the storage health test includes multiple sub-tests; the method of performing the storage health test based on the target address combination includes: performing the current sub-test based on the current target address combination; after completing the current sub-test, re-obtaining the target address combination and performing the next sub-test based on the re-obtained target address combination; where the target address combinations corresponding to each sub-test are different.

[0014] In some embodiments, in the target address combinations corresponding to different sub-tests, the positions of the address regions where the test addresses corresponding to the same address region are located are different.

[0015] In a second aspect, the present application also provides a memory, including: at least one storage block; an address generation module configured to obtain the target address combination based on the storage health test method provided by the first method above; and an execution module connected to the at least one storage block and the address generation module, configured to perform a storage health test based on the target address combination in response to a test command.

[0016] The memory health test method provided by this application obtains test addresses based on address combinations in a memory block, and the test addresses are evenly distributed in the memory block to ensure the accuracy of the test results for a single test. Additionally, the test addresses in different address combinations are different, enabling the memory block to support multiple tests for the same test item. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of this application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 It is a flowchart corresponding to each step in the memory health test method provided by the embodiment of this application;

[0019] Figure 2 It is a structural schematic diagram corresponding to the first address area division method provided by the embodiment of this application;

[0020] Figure 3 It is a structural schematic diagram corresponding to the second address area division method provided by the embodiment of this application;

[0021] Figure 4 It is a structural schematic diagram corresponding to the third address area division method provided by the embodiment of this application;

[0022] Figure 5 It is a structural schematic diagram corresponding to the fourth address area division method provided by the embodiment of this application;

[0023] Figure 6 It is a schematic diagram of the principle for obtaining test addresses based on word line selection signals and bit line selection signals provided by the embodiment of this application;

[0024] Figure 7 It is a flowchart corresponding to each step in multiple tests of the memory health test method provided by the embodiment of this application;

[0025] Figure 8 It is a structural schematic diagram of the memory provided by the embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] As can be seen from the background art, for memory health (MH) testing, a certain memory stress is applied to cause corresponding fatigue levels to detect product performance. For memory cells, the applied memory stress is destructive. Therefore, memory health testing requires as many addresses as possible for different test items.

[0027] In addition, the MH test includes at least six test items. To avoid damage to the storage unit caused by storage pressure, when the same test item is tested multiple times, it is necessary to replace the storage block for execution. However, the storage performance differences between different storage blocks affect the accuracy of the test results.

[0028] The embodiment of the present application provides a storage health test method. Test addresses are obtained based on address combinations in a storage block, and the test addresses are evenly distributed in the storage block to ensure the accuracy of the test results for a single test. In addition, the test addresses in different address combinations are different, enabling the storage block to support multiple tests of the same test item.

[0029] The storage health test method provided by this embodiment includes: obtaining a storage block to be tested; obtaining at least one address combination in the storage block to be tested, and selecting a target address combination from the at least one address combination; wherein, each address combination includes multiple test addresses, and the multiple test addresses are evenly distributed in the storage block to be tested, and the test addresses in different address combinations are different; performing a storage health test based on the target address combination.

[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0031] In addition, in the present application, descriptions such as "first" and "second" are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0032] Refer to Figure 1 , Figure 1It is a schematic flowchart corresponding to each step in the storage health test method provided in this embodiment. Specifically, the storage health test method provided in this embodiment is applied to storage health testing, including step 101 to step 103. Among them, in step 101, a storage block to be tested is obtained. In step 102, at least one address combination is obtained in the storage block to be tested, and a target address combination is selected from the at least one address combination. In step 103, a storage health test is performed based on the target address combination.

[0033] For a memory, the memory includes multiple storage blocks, and the test object of the storage health test is the storage block. For step 101, that is, a storage block required for the storage health test is selected from the memory as the storage block to be tested.

[0034] Based on the foregoing, different test items are included in the storage health test, and different test items correspond to different storage blocks. At this time, step 101 is used to obtain the storage block corresponding to the current test item for which the memory performs the storage health test.

[0035] For step 102, each storage block to be tested corresponds to at least one address combination, and a target address combination is selected from the at least one address combination to perform the storage health test. Among them, each address combination includes multiple test addresses, and the multiple test addresses are evenly distributed in the storage block to be tested, and the test addresses in different address combinations are different. Specifically, different storage units in the storage block may exhibit different performances due to different positions, and the test addresses are evenly distributed in the storage block to be tested, so that the test addresses can cover storage units with different performances, thereby ensuring the accuracy of a single storage health test based on a single address combination.

[0036] For step 103, that is, a storage health test is performed based on the target address combination obtained in step 102.

[0037] It should be noted that in the subsequent description of this embodiment, without specific declaration, a storage block of 16 * 32 (16 rows and 32 columns, that is, 16 word lines and 32 bit lines) is used as an example for description, which does not constitute a limitation on the storage block provided in this embodiment. In specific applications, it can be extended to storage blocks of any size.

[0038] In some embodiments, the method for obtaining at least one address combination corresponding to the storage block to be tested includes: dividing the storage block to be tested into regions to obtain multiple address regions; obtaining at least one test address in each address region; different combinations of test addresses in each address region form different address combinations. The method for obtaining address combinations in the storage block will be described in detail below with reference to the accompanying drawings, as follows.

[0039] It should be noted that the multiple address regions obtained by partitioning the storage block to be tested evenly partition the storage block to be tested, that is, the area of each address region divided based on the storage block to be tested is similar and covers the entire storage block to be tested, so that the test addresses can cover storage units with different performances, thereby ensuring the accuracy of a single storage health test based on a single address combination.

[0040] In some embodiments, refer to Figure 2 , Figure 2 which is a schematic structural diagram corresponding to the first method for partitioning address regions provided in this embodiment.

[0041] Since the drivers (row driver 201 and column driver 202) are distributed on one side of the storage block 200, there are differences in the driving capabilities of different storage units in the storage block; specifically, the driving capabilities of the storage units closer to the row driver 201 and the column driver 202 are stronger, while the driving capabilities of the storage units farther from the row driver 201 and the column driver 202 are weaker. At this time, the storage block 200 can be partitioned based on the driving capability differences of the storage units, as Figure 2 shown, to obtain three address regions, and at least one test address is obtained from each address region to form an address combination, so that the test addresses can cover storage units with different performances, thereby ensuring the accuracy of a single storage health test based on a single address combination.

[0042] It should be noted that for Figure 2 the example, the number of partitions of the address regions and the number of test addresses obtained in each address region are only for illustrative purposes and do not constitute a limitation on this embodiment.

[0043] In some embodiments, refer to Figure 3 , Figure 3 which is a schematic structural diagram corresponding to the second method for partitioning address regions provided in this embodiment. Different from the previous example, the previous embodiment partitions based on the driving capability, and this example partitions based on the word line position.

[0044] Specifically, the method for partitioning the storage block to be tested to obtain multiple address regions includes: partitioning based on a preset number of word lines in the storage block to be tested.

[0045] For a 16-row memory block, region division is performed based on every consecutive 4 row word lines (i.e., the preset number is 4). At this time, word lines 0 to 3 form an address region, word lines 4 to 7 form an address region, word lines 8 to 11 form an address region, and word lines 12 to 15 form an address region, for a total of 4 address regions. At least one test address is obtained in each address region to form an address combination, so that the test addresses can cover memory cells with different performances, thereby ensuring the accuracy of a single storage health test based on a single address combination.

[0046] It should be noted that in this example, using 4 word lines to form an address region does not limit the preset number. In practical applications, it can be reasonably allocated based on the number of word lines in the memory block and the number of address regions to be divided. Additionally, the number of word lines in different address regions can also be different.

[0047] In some embodiments, refer to Figure 4 , Figure 4 which is a schematic structural diagram corresponding to the third method of dividing address regions provided in this embodiment. Different from the previous example, the previous embodiment performed region division based on the word line position, while this example performs region division based on the bit line position.

[0048] Specifically, the method of performing region division on the memory block to be tested to obtain multiple address regions includes: performing region division based on a preset number of bit lines in the memory block to be tested.

[0049] For a 32-column memory block, region division is performed based on every consecutive 8 column bit lines (i.e., the preset number is 8). At this time, bit lines 0 to 7 form an address region, bit lines 8 to 15 form an address region, bit lines 16 to 23 form an address region, and bit lines 24 to 31 form an address region, for a total of 4 address regions. At least one test address is obtained in each address region to form an address combination, so that the test addresses can cover memory cells with different performances, thereby ensuring the accuracy of a single storage health test based on a single address combination.

[0050] It should be noted that in this example, using 4 bit lines to form an address region does not limit the preset number. In practical applications, it can be reasonably allocated based on the number of bit lines in the memory block and the number of address regions to be divided. Additionally, the number of bit lines in different address regions can also be different.

[0051] In some embodiments, refer to Figure 5 , Figure 5 which is a schematic structural diagram corresponding to the fourth method of dividing address regions provided in this embodiment. Different from the previous example, the previous embodiment performed region division based on the bit line position, while this example performs region division based on the word line position and the bit line position.

[0052] Specifically, the method for partitioning a storage block to be tested to obtain multiple address regions includes: performing a first region partition based on a first preset number of word lines in the storage block to be tested, performing a second region partition based on a second preset number of bit lines in the storage block to be tested, and obtaining address regions based on the results of the first region partition and the second region partition.

[0053] For a 16-row and 32-column storage block, every consecutive 4 rows and 4 columns are partitioned. At this time, word lines 0 to 3 and bit lines 0 to 3 form an address region, word lines 0 to 3 and bit lines 4 to 7 form an address region... word lines 4 to 7 and bit lines 0 to 3 form an address region, word lines 4 to 7 and bit lines 4 to 7 form an address region... word lines 12 to 15 and bit lines 28 to 31 form an address region, for a total of 32 address regions. At least one test address is obtained in each address region to form an address combination, so that the test addresses can cover storage units with different performances, thereby ensuring the accuracy of a single storage health test based on a single address combination.

[0054] It should be noted that in Figure 5 the example, the first preset number and the second preset number are the same, which does not constitute a limitation on this embodiment. In specific applications, the first preset number or the second preset number can be set arbitrarily, and the numbers of the two can also be different. Additionally, in Figures 3 to 5 the example, the number of test addresses selected in different address regions is the same, which does not constitute a limitation on this embodiment. In specific applications, the number of test addresses selected in each address region can also be different.

[0055] For Figure 5 the example, each address region includes 16 storage units, that is, 16 addresses; if one address is selected from each address region as a test address, there are 16 selection methods in each address region, and different address regions are independent of each other. At this time, there are 16 32 address combinations.

[0056] In some embodiments, the method for obtaining at least one test address in each address region includes: obtaining a word line selection signal and a bit line selection signal; based on the result of the first region partition and the word line selection signal, obtaining the word line address corresponding to the test address in each address region, where the word line selection signals corresponding to different results of the first region partition are different; based on the result of the second region partition and the bit line selection signal, obtaining the bit line address corresponding to the test address in each address region, where the bit line selection signals corresponding to different results of the second region partition are different.

[0057] Refer to Figure 6 , Figure 6Schematic diagram of the principle for obtaining a test address based on a word line selection signal and a bit line selection signal provided in this embodiment. In one example, for a 64 * 64 memory block, it is grouped in units of 8, denoted as WL_X_ID / BL_X_ID; where WL_X_ID includes WL_0_ID to WL_7_ID, and BL_X_ID includes BL_0_ID to BL_7_ID; WL_X_ID represents the (X + 1)-th 8-word line (Word Line, WL), and BL_X_ID represents the (X + 1)-th 8-bit line (Bit Line, BL).

[0058] Each 8-word line corresponds to a word line selection signal DCG_WL_ID. The word line selection signal DCG_WL_ID represents the number of the selected word line in the current 8-word line. The value of the word line selection signal is 0 to 7 to select the target word line in the 8-word line; similarly, each 8-bit line corresponds to a bit line selection signal DCG_BL_ID. The bit line selection signal DCG_BL_ID represents the number of the selected bit line in the current 8-bit line. The value of the bit line selection signal is 0 to 7 to select the target bit line in the 8-bit line.

[0059] In some embodiments, in any address combination, the word line position or the bit line position of the address region where each test address is located is different.

[0060] Specifically, if the word line selection signal DCG_WL_ID is 1 in the 8-word line of WL_1_ID, then the word line selection signal DCG_WL_ID in the 8-word lines of WL_2 - 8_ID is not 1; if the word line selection signal DCG_WL_ID is 2 in the 8-word line of WL_2_ID, then the word line selection signal DCG_WL_ID in the 8-word lines of WL_3 - 8_ID is not 1 and not 2, thereby further ensuring that the test addresses are evenly distributed in the memory block to be tested. At this time, since the word line selection signals of different 8-word lines are different, it is equivalent to arranging the word line selection signals 1 to 8 in 8 8-word lines, including A 8 8 types of word line selection methods. Similarly, the bit line selection signals of different 8-bit lines are different, which is equivalent to arranging the bit line selection signals 1 to 8 in 8 8-bit lines, including A 8 8 types of bit line selection methods. The combination of the two includes A 8 8 *A 8 8 types of address combinations.

[0061] Based on the foregoing, the storage health test method provided in this embodiment also supports multiple tests for the same storage block. In some embodiments, the storage health test includes multiple sub-tests; the method for performing the storage health test based on the target address combination includes: performing the current sub-test based on the current target address combination; after completing the current sub-test, reacquiring the target address combination, and performing the next sub-test based on the reacquired target address combination; wherein each sub-test corresponds to a different target address combination.

[0062] refer to Figure 7 , Figure 7 A flowchart corresponding to each step in multiple tests of the storage health test method provided in this embodiment. Figure 1 Example, Figure 7 In the example, step 103 includes steps 301 to 303 .

[0063] Step 301, perform the current sub-test based on the target address combination. Step 302, reacquire the target address combination. Step 303, perform the next sub-test based on the target address combination.

[0064] The target address combinations obtained in step 301 and step 303 are different address combinations among the multiple address combinations corresponding to the storage block. By setting different address combinations to support multiple sub-tests of the storage health test, the storage pressure of the test is distributed to different storage units, so that the storage block can support multiple tests of the same test item.

[0065] In some embodiments, in target address combinations corresponding to different sub-tests, the locations of the address regions where the test addresses corresponding to the same address region are located are different, to ensure that the same storage unit is not selected in multiple tests, to ensure that the storage pressure of the test is distributed to different storage units.

[0066] In one example, refer to Figure 6 , for a certain address region (for example, the 8*8 address region corresponding to WL_1_ID and BL_1_ID), if the word line selection signal DCG_WL_ID=1 in the first sub-test, the value of the word line selection signal DCG_WL_ID will no longer be selected as 1 in the subsequent sub-tests; accordingly, if the bit line selection signal DCG_BL_ID=2 in the first sub-test, the value of the bit line selection signal DCG_BL_ID will no longer be selected as 2 in the subsequent sub-tests. At this time, for the same address region, the word line selection signal that has appeared will no longer appear, and there are 8 different word line selection signals; accordingly, the bit line selection signal that has appeared will no longer appear, and there are 8 different bit line selection signals, that is, the current storage block can support 8 sub-tests without selecting the same word line address and bit line address.

[0067] In summary, for the storage health test method provided in this embodiment, test addresses are obtained based on address combinations in the storage block, and the test addresses are evenly distributed in the storage block to ensure the accuracy of the test results for a single test. In addition, the test addresses in different address combinations are different, enabling the storage block to support multiple tests for the same test item.

[0068] It should be noted that, without conflict, the features disclosed in the storage health test method provided in the above embodiment can be randomly combined to obtain a new embodiment of the storage health test method.

[0069] This embodiment also provides a memory for executing the storage health test method provided in the above embodiment.

[0070] Reference Figure 8 , Figure 8 is a schematic structural diagram of the memory provided in this embodiment. Referring to Figure 8 ,the memory 400 includes at least one storage block 401, an address generation module 402, and an execution module 403.

[0071] Among them, the address generation module 402 is configured to obtain a target address combination based on the storage health test method provided in the above embodiment; the execution module 403 is connected to at least one storage block 401 and the address generation module 402, and the execution module 403 is configured to execute a storage health test based on the target address combination in response to a test command.

[0072] For the address generation module 402, each storage block to be tested corresponds to at least one address combination, and a target address combination is selected from at least one address combination for executing a storage health test. Among them, each address combination includes multiple test addresses, and the multiple test addresses are evenly distributed in the storage block to be tested, and the test addresses in different address combinations are different. Specifically, different storage units in the storage block may exhibit different performances due to different positions, and the test addresses are evenly distributed in the storage block to be tested, enabling the test addresses to cover storage units with different performances, thereby ensuring the accuracy of a single storage health test based on a single address combination.

[0073] In some embodiments, the method for the address generation module 402 to obtain at least one address combination corresponding to the storage block to be tested includes: dividing the storage block to be tested into regions to obtain multiple address regions; obtaining at least one test address in each address region; and different combinations of test addresses in each address region form different address combinations.

[0074] For the execution module 403, the execution module 403 executes a storage health test based on the target address combination provided by the address generation module 402 in response to a test command.

[0075] If the storage health test includes multiple sub-tests, the execution module 403 is configured to execute the current sub-test based on the current target address combination; after completing the current sub-test, the address generation module 402 re-acquires the target address combination, and the execution module 403 executes the next sub-test based on the re-acquired target address combination; wherein the target address combination corresponding to each sub-test is different.

[0076] In some embodiments, in target address combinations corresponding to different sub-tests, the locations of the address regions where the test addresses corresponding to the same address region are located are different, to ensure that the same storage unit is not selected in multiple tests, to ensure that the storage pressure of the test is distributed to different storage units.

[0077] In some embodiments, the memory provided in this embodiment is applied to a storage system, and the storage system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0078] For the memory provided in this embodiment, the test address is obtained in the storage block based on the address combination, and the test address is evenly distributed in the storage block to ensure the accuracy of the test result of a single test; in addition, the test addresses in different address combinations are different, so that the storage block can support multiple tests of the same test item.

[0079] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0080] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0081] The above has introduced in detail a storage health test method and a memory provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A storage health test method, characterized in that: include: Get the storage block to be tested; Acquire at least one address combination in the storage block to be tested, and select a target address combination from the at least one address combination; Each of the address combinations includes a plurality of test addresses, and the plurality of test addresses are evenly distributed in the storage block to be tested, and the test addresses in different address combinations are different; A storage health test is performed based on the target address combination.

2. The storage health test method according to claim 1, characterized in that: The method for obtaining at least one address combination corresponding to the storage block to be tested comprises: Dividing the storage block to be tested into regions to obtain multiple address regions; Acquire at least one of the test addresses in each of the address regions; Different combinations of the test addresses in each of the address regions constitute different address combinations.

3. The storage health test method according to claim 2, characterized in that: The address area evenly divides the storage block to be tested.

4. The storage health test method according to claim 3, characterized in that: The method of dividing the memory block to be tested into regions to obtain a plurality of address regions includes: dividing the regions based on a preset number of word lines or bit lines in the memory block to be tested.

5. The storage health test method according to claim 3, characterized in that: The method of dividing the storage block to be tested into regions to obtain multiple address regions comprises: Performing a first area division based on a first preset number of word lines in the memory block to be tested; Performing a second area division based on a second preset number of bit lines in the memory block to be tested; The address area is acquired based on the results of the first area division and the second area division.

6. The storage health test method according to claim 5, characterized in that: The method for acquiring at least one test address in each address area comprises: Obtaining a word line selection signal and a bit line selection signal; Based on the result of the first area division and the word line selection signal, obtaining the word line address corresponding to the test address in each address area, wherein the word line selection signal corresponding to different results of the first area division is different; Based on the result of the second area division and the bit line selection signal, the bit line address corresponding to the test address in each address area is obtained, and the bit line selection signal corresponding to different results of the second area division is different.

7. The storage health test method according to claim 6, characterized in that: In any of the address combinations, the word line position and the bit line position of the address region where each of the test addresses is located are different.

8. The storage health test method according to claim 1, characterized in that: The storage health test includes multiple sub-tests; the method for performing the storage health test based on the target address combination includes: Execute the sub-test based on the current target address combination; After completing the sub-test, re-acquire the target address combination, and perform the next sub-test based on the re-acquired target address combination; The target address combination corresponding to each sub-test is different.

9. The storage health test method according to claim 8, characterized in that: In the target address combinations corresponding to different sub-tests, the test addresses corresponding to the same address area are located at different positions in the address area.

10. A memory, characterized in that: include: at least one storage block; An address generation module, configured to obtain the target address combination based on the storage health test method according to any one of claims 1 to 9; An execution module is connected to the at least one storage block and the address generation module, and is configured to, in response to a test command, perform a storage health test based on the target address combination.

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