Silicon carbide platform and fabrication thereof by silicon carbide-on-silicon epitaxy

Abstract

The invention relates to a silicon carbide platform and its fabrication by silicon carbide-on-silicon epitaxy. A method of manufacturing a silicon carbide platform includes providing a substrate including a silicon seed layer having a (001) lattice plane and a top surface parallel to the (001) lattice plane; and forming a silicon carbide epitaxial layer directly on the top surface of the silicon seed layer by epitaxial growth. In some embodiments, the silicon carbide platform may be formed using a silicon-on-insulator substrate. In some embodiments, the silicon carbide epitaxial layer may be grown on a mask layer by epitaxial lateral overgrowth. In some embodiments, the silicon carbide platform may include an additional layer, such as a III-V semiconductor layer disposed on and bonded to the silicon carbide epitaxial layer. In some embodiments, the silicon carbide epitaxial layer may be buried between two other layers.

Description

[0001] Introduction

[0002] Silicon carbide (SiC) can be used to form various semiconductor devices, including SiC-based electronic devices, optoelectronic devices, photonic integrated circuits, and microelectromechanical systems (MEMS). In recent years, the demand for such SiC-based devices has been increasing. In particular, the demand for SiC-based power devices such as power transistors (e.g., MOSFETs) has been increasing, partly due to the increasing demand for electric vehicles and renewable energy. Brief Description of the Drawings

[0003] Alone or in combination with the appended Figure 1 Together, the present disclosure can be understood from the following detailed description. These drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The drawings illustrate one or more examples of the teachings and, together with the description, explain certain principles and operations. In the drawings:

[0004] Figure 1 is a schematic cross-section of an exemplary SiC platform.

[0005] Figure 2 is a schematic cross-section of an exemplary SiC-on-SOI platform.

[0006] Figure 3 is Figure 2 a schematic cross-section of the SiC-on-SOI platform in a first manufacturing stage.

[0007] Figure 4 is Figure 2 a schematic cross-section of the SiC-on-SOI platform in a second manufacturing stage.

[0008] Figure 5 is Figure 2 a schematic cross-section of the SiC-on-SOI platform in a third manufacturing stage.

[0009] Figure 6 is a schematic cross-section of an exemplary SiC-ELOG platform.

[0010] Figure 7 is Figure 6 a schematic cross-section of the SiC-ELOG platform in a first manufacturing stage.

[0011] Figure 8 is Figure 6 a schematic cross-section of the SiC-ELOG platform in a second manufacturing stage.

[0012] Figure 9 is Figure 6Schematic cross-section of the SiC-ELOG platform in the third manufacturing stage.

[0013] Figure 10 is Figure 6 Schematic cross-section of the SiC-ELOG platform in the fourth manufacturing stage.

[0014] Figure 11 is Figure 6 Schematic cross-section of the SiC-ELOG platform in the fifth manufacturing stage.

[0015] Figure 12 is Figure 6 Schematic cross-section of the SiC-ELOG platform in the sixth manufacturing stage.

[0016] Figure 13 is a schematic cross-section of an exemplary SiC-III-V platform.

[0017] Figure 14 is Figure 13 Schematic cross-section of the first part of the SiC-III-V platform in the first manufacturing stage.

[0018] Figure 15 is Figure 13 Schematic cross-section of the first part of the SiC-III-V platform in the second manufacturing stage.

[0019] Figure 16 is Figure 13 Schematic cross-section of the second part of the SiC-III-V platform in the third manufacturing stage.

[0020] Figure 17 is Figure 13 Schematic cross-section of the SiC-III-V platform in the fourth manufacturing stage.

[0021] Figure 18 is Figure 13 Schematic cross-section of the SiC-III-V platform in the fifth manufacturing stage.

[0022] Figure 19 is Figure 13 Schematic cross-section of the SiC-III-V platform in the sixth manufacturing stage.

[0023] Figure 20 is a schematic cross-section of an exemplary buried SiC platform.

[0024] Figure 21 is according to the first manufacturing method Figure 20 Schematic cross-section of the first part of the buried SiC platform in the first manufacturing stage.

[0025] Figure 22 is the first part of a buried SiC platform according to the first manufacturing method Figure 20 in a schematic cross-section during the second manufacturing stage.

[0026] Figure 23 is the first part of a buried SiC platform according to the first manufacturing method Figure 20 in a schematic cross-section during the third manufacturing stage.

[0027] Figure 24 is the first part of a buried SiC platform according to the first manufacturing method Figure 20 in a schematic cross-section during the fourth manufacturing stage.

[0028] Figure 25 is the first part of a buried SiC platform according to the first manufacturing method Figure 20 in a schematic cross-section during the fifth manufacturing stage.

[0029] Figure 26 is the first part of a buried SiC platform according to the first manufacturing method Figure 20 in a schematic cross-section during the sixth manufacturing stage.

[0030] Figure 27 is the first part of a buried SiC platform according to the second manufacturing method Figure 20 in a schematic cross-section during the first manufacturing stage.

[0031] Figure 28 is the first part of a buried SiC platform according to the second manufacturing method Figure 20 in a schematic cross-section during the second manufacturing stage.

[0032] Figure 29 is the first part of a buried SiC platform according to the second manufacturing method Figure 20 in a schematic cross-section during the third manufacturing stage.

[0033] Figure 30 is the first part of a buried SiC platform according to the second manufacturing method Figure 20 in a schematic cross-section during the fourth manufacturing stage.

[0034] Figure 31 is the first part of a buried SiC platform according to the second manufacturing method Figure 20 in a schematic cross-section during the fifth manufacturing stage.

[0035] Figure 32 is a schematic cross-section of an III-V platform on an exemplary SiC-ELOG.

[0036] Figure 33 is Figure 32Schematic cross-section of the first part of the III-V platform on SiC-ELOG in the first manufacturing stage.

[0037] Figure 34 is Figure 32 Schematic cross-section of the second part of the III-V platform on SiC-ELOG in the second manufacturing stage.

[0038] Figure 35 is Figure 32 Schematic cross-section of the III-V platform on SiC-ELOG in the third manufacturing stage.

[0039] Figure 36 is Figure 32 Schematic cross-section of the III-V platform on SiC-ELOG in the fourth manufacturing stage.

[0040] Figure 37 is Figure 32 Schematic cross-section of the III-V platform on SiC-ELOG in the fifth manufacturing stage. Detailed implementation

[0041] As described above, the demand for SiC semiconductor devices is increasing continuously. However, it may be difficult and expensive to produce SiC wafers through existing technologies. Many technologies for SiC wafer production result in low die production due to the limited maximum wafer size (and thus, the limited number of dies per wafer) and / or due to the relatively long production time for each wafer. For example, while it takes about 8 hours to form a Si ingot, it may take about 5 - 10 days to form a SiC ingot. Additionally, due to its hardness, SiC ingots are more difficult to slice and polish into wafers than Si ingots. Moreover, in many SiC wafer production methods, the maximum value of the wafer size is often limited to about 150 mm (using some manufacturing technologies) or 200 mm (using some manufacturing technologies), and the wafers tend to be very expensive (compared to Si wafers of similar size). Therefore, in order to support the expected increase in demand for SiC devices, technologies for producing SiC platforms with higher die production (e.g., larger wafer size per wafer and / or less time spent) and lower production costs are needed.

[0042] To address these and other issues, the examples disclosed herein include various SiC platforms with relatively high production yields and relatively low production costs, and their manufacturing techniques. Each SiC platform includes a plurality of stacked material layers that at least include a Si seed layer and a SiC epitaxial layer epitaxially formed on the Si seed layer. More specifically, in some examples, the Si seed layer includes a (001) Si lattice plane, and the SiC epitaxial layer (at least initially) grows from the (001) Si lattice plane. Thus, the SiC epitaxial layer has a crystal orientation corresponding to the (001) Si seed layer. In various example platforms, one or more other layers (in addition to the Si seed layer and the SiC epitaxial layer) may also be present, such as oxide layers, III-V semiconductor layers, or other layers that will be explained in more detail below. The Si seed layer may be provided in the form of a bare Si wafer or an exposed Si layer of some other substrate, such as the silicon device layer of a silicon-on-insulator (SOI) substrate.

[0043] The SiC platforms disclosed herein (which use Si as a seed layer for epitaxial growth) can be larger than platforms formed by SiC epitaxy on a SiC seed layer because the Si seed layers used in the examples disclosed herein (e.g., Si wafers, SOI substrates, etc.) tend to be available in larger maximum sizes than SiC wafers / substrates. For example, Si wafers or SOI substrates with diameters up to 300 mm (projected 450 mm) are typically available, while the diameters of SiC wafers are often limited to 150 mm or 200 mm (depending on the process used to form these SiC wafers). This size difference can have a significant impact on die production yields - for example, a 200 mm wafer can be processed into 269 dies (each die being 100 mm 2 ), while a 300 mm wafer can be processed into 640 dies (each die being 100 mm 2 ), which is an increase of approximately 2.4 times. Additionally, forming the SiC platforms disclosed herein may be less costly than, for example, forming platforms by SiC epitaxy on a SiC seed layer because Si substrates tend to be less expensive than SiC substrates. Furthermore, forming a SiC platform by SiC epitaxy on a Si seed layer may be faster, easier, and less expensive than attempting to grow a SiC ingot and slice it into wafers. Thus, compared to the production yields and costs achievable with other methods of producing SiC wafers, the example SiC platforms disclosed herein can be produced with higher production yields and lower costs.

[0044] Turning now to the drawings, various devices, systems, and methods in accordance with aspects of the present disclosure will be described.

[0045] Figures 2 to 37Schematically illustrates cross-sections of various SiC platforms. These figures are schematic in nature and are not intended to accurately or to scale illustrate specific dimensions or other structural details, unless otherwise noted.

[0046] Turning now to Figure 1 , SiC platform 10 will be described. As Figure 1 shown therein, SiC platform 10 includes at least two material layers: Si seed layer 11 and a SiC epitaxial layer 20 formed on Si seed layer 11.

[0047] Si seed layer 11 can be provided as a standalone Si substrate (e.g., Si wafer) or as an exposed layer of some other substrate such as a SOI substrate. Si seed layer 11 can include Si having a crystal structure that is oriented such that the surface of the grown SiC epitaxial layer 20 ( Figure 1 the top surface in ) corresponds to (i.e., is parallel to) the (001) lattice plane of Si seed layer 11. Si wafers, SOI substrates, or other substrates having a Si layer (with such a crystal orientation) are widely commercially available.

[0048] SiC epitaxial layer 20 can be grown epitaxially on Si seed layer 11, specifically on a surface parallel to the (001) lattice plane (for convenience, this surface is referred to herein as the "top" surface, but this does not limit the orientation of SiC platform 10 with respect to an absolute reference frame such as the ground). Various epitaxial techniques are known in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), atomic layer epitaxy (ALE), and liquid phase epitaxy (LPE), and any such epitaxial technique can be used to form SiC epitaxial layer 20. Since these epitaxial techniques are familiar to those of ordinary skill in the art, they will not be described in more detail herein.

[0049] The SiC epitaxial layer 20 may have a cubic crystal structure, such as Si on which the epitaxial layer is grown. Further, since the SiC epitaxial layer 20 is grown on a surface corresponding to the (001) lattice plane of the Si seed layer 11, the SiC epitaxial layer 20 may have a crystal orientation similar to that of the Si seed layer 11 (e.g., the (001) lattice plane of the SiC layer 20 may be parallel to the (001) lattice plane of the Si seed layer 11). Additionally, the SiC epitaxial layer includes a 3C-SiC polytype. Many existing SiC devices (semiconductor devices, photonic devices, etc.) are formed of 4H-SiC or 6H-SiC polytypes, but generally, the 3C-SiC polytype may have material properties that are also suitable for forming similar SiC devices. In some examples, the SiC epitaxial layer 20 may be in-situ doped during growth. In other examples, the SiC epitaxial layer 20 may be undoped (high resistivity or semi-insulating).

[0050] In some examples, the SiC platform 10 may be used to form various electronic, optical, or electro-optic devices on or in the layers of the platform 10 by various known techniques such as lithography, etching, deposition (e.g., thin film deposition), implantation (e.g., ion implantation), thermal oxidation, etc. More specifically, in some examples, the SiC platform 10 includes various devices or may be processed to form various devices such as electronic devices, optoelectronic devices, photonic components or photonic integrated circuits, and microelectromechanical systems (MEMS). In some examples, such devices are formed by processing the SiC platform 10 subsequent to fabricating the platform 10, similar to how a Si wafer, SOI substrate, or SiC wafer may be processed to form various devices. In other examples, the devices may be formed partially or completely during the fabrication of the SiC platform 10 without necessarily requiring subsequent processing to form the devices. In some examples, the devices are formed at least partially in or on the SiC epitaxial layer. In some examples, the devices are formed in other layers (described in more detail below).

[0051] In some examples, the SiC platform 10 may include a wafer-like structure similar to a Si wafer or an SOI substrate. In some examples, the Si seed layer 11 may have a wafer diameter of 200 mm, and thus, the SiC layer 20 and the SiC platform 10 as a whole may also have a wafer diameter of 200 mm. In some examples, the Si seed layer 11 may have a wafer diameter greater than 200 mm (such as 300 mm or 450 mm), and thus, the SiC layer 20 and the SiC platform 10 as a whole may also have a wafer diameter greater than 200 mm (e.g., 300 mm, 450 mm, etc.). In some examples, the SiC platform 10 may include die that have been cut from a larger wafer. In some examples, the SiC platform 10 may include semiconductor devices, integrated circuits, and / or photonic integrated circuits, in which case the SiC platform 10 may include various devices and circuits formed in or on the layers 11 and 20 (or in / on other layers of the SiC platform 10, Figure 1 not shown in these other layers).

[0052] Although only two material layers are shown in Figure 1 , the SiC platform 10 may include one or more additional layers in various configurations. For example, Figure 2 , Figure 6 , Figure 13 , Figure 20 and Figure 32 illustrate multiple SiC platforms that are specific configuration examples of the SiC platform 10 in which there are additional material layers and / or that are formed by various different methods. These example configurations of the SiC platform 10 will be described in more detail below. Some components of the various SiC platforms correspond to components of the SiC platform 10 described above (i.e., are the same as, similar to, or an example implementation of it); such corresponding components are identified by using similar reference numerals with the last two digits the same (e.g., 120 and 220). Unless otherwise stated or logically contradictory, the description herein of a component for one example SiC platform applies to any corresponding component in any other SiC platform, and the repeated description of the corresponding components may be omitted.

[0053] Turning to Figure 2, a first example configuration of the SiC platform 10 will be described in the form of the SiC platform 110. The SiC platform 110 can also be referred to as the SiC platform 110 on SOI because it includes a SiC layer 120 formed on an SOI substrate 130. In some examples, the SOI substrate 130 includes a first Si layer 133 (also referred to herein as the Si handle 133), a buried oxide (BOX) layer 132 on the Si handle 133, and a second Si layer 131 (also referred to herein as the Si device layer 131) on the BOX layer 132. This is a type of commercially available SOI substrate. In some examples, the thickness of the Si device layer 131 is less than 50 nm, and its top surface is aligned with the (001) lattice plane. In some examples, the thickness of the BOX layer 132 is 0.1 - 10 μm. In some examples, the BOX layer 132 includes silicon dioxide (SiO2).

[0054] In addition, a SiC epitaxial layer 120 is epitaxially grown on the Si device layer 131 of the SOI substrate 130. In other words, the Si device layer 131 is used as a seed layer for SiC growth (i.e., the Si device layer 131 is an example implementation of the seed layer 11), and thus, the Si device layer 131 can also be referred to herein as the Si seed layer 111 or the Si seed / device layer 111, 131. The SiC epitaxial layer 120 is an example implementation of the SiC epitaxial layer 20. In some examples, the thickness of the SiC epitaxial layer 120 is about 0.05 μm to 10 μm. In the case of adding the SiC epitaxial layer 120 to the SOI substrate 130, the SiC platform 110 on SOI is formed and the SiC platform 110 on SOI has at least the following layers in order from bottom to top: the Si handle 133, the BOX layer 132, the Si seed / device layer 111, 131, and the SiC epitaxial layer 120.

[0055] In some examples, the SiC platform 110 on SOI can be particularly suitable for forming photonic integrated circuits. For example, a properly patterned SiC / Si layer 111 / 120 can form the core of an optical waveguide. The BOX layer 132 can be used as a lower cladding layer, while a SiO2 layer (not shown) grown on the top of the SiC layer 120 can be used as an upper cladding layer.

[0056] In Figure 2 The configuration of the SOI substrate 130 shown in Figure 2In [the figure], the insulator is exactly the BOX layer 132 disposed on the Si processing portion 133. However, in other examples, the Si device layer 131 may be disposed on a different insulator such as a sapphire substrate (not shown) or some other insulator. Additionally, in some examples, the Si processing portion 133 may be omitted. Regardless of the type of SOI substrate used, in each example of the platform 110, the SOI substrate has a Si device layer 131 and the SiC epitaxial layer 120 is epitaxially grown on the Si device layer 131.

[0057] Turning Figures 3 to 5 , a method of manufacturing the SiC-on-SOI platform 110 will be described. First, as Figure 3 shown in [the figure], an SOI substrate 130 is provided. In Figure 3 [the figure], it is assumed that the SOI substrate 130 includes a Si processing portion 133, a BOX layer 132, and a Si device layer 131. However, at this stage, any type of SOI substrate can be provided, as explained above. Providing the SOI substrate 130 includes obtaining possession and / or control of the SOI substrate 130, which may include, for example, manufacturing the SOI substrate 130, purchasing the SOI substrate 130, etc.

[0058] Next, as Figure 4 shown in [the figure], the SiC epitaxial layer 120 is epitaxially grown on the top surface of the Si seed / device layers 111, 131. Specifically, in some examples, the SiC epitaxial layer 120 includes a 3C-SiC polytype directly epitaxially grown on the (001) surface of the Si seed / device layers 111, 131. In some examples, the growth of the SiC epitaxial layer 120 does not require a thick buffer layer.

[0059] Next, as Figure 5 shown in [the figure], in some examples, the top surface of the SiC epitaxial layer 120 can be polished or smoothed by various known techniques such as chemical mechanical polishing (CMP), reactive ion etching (RIE), atomic layer etching (ALE), or a combination thereof. In some cases, epitaxial growth can produce a possibly rough top surface. In some applications, the roughness level may be acceptable, in which case the polishing step can be omitted. However, in some applications, a smoother surface may be desired, in which case the polishing step can be performed. In particular, in various photonics applications where photon devices are formed on or in the platform 110, a low-roughness surface of the SiC epitaxial layer 120 can improve the optical loss of the photon devices.

[0060] Turning Figure 6, a second exemplary configuration of the SiC platform 10 will be described in the form of the SiC platform 210. The SiC platform 210 may also be referred to as the SiC-ELOG platform 210 because in this example, the SiC epitaxial layer 220 is formed by epitaxial lateral overgrowth (ELOG), which will be described in more detail below. The SiC-ELOG platform 210 includes an Si substrate 211, a mask 242 formed on the Si substrate 211, and an SiC epitaxial layer 220 formed on the Si substrate 211 and extending laterally over the mask 242.

[0061] The SiC epitaxial layer 220 is epitaxially grown on the Si substrate 211. In other words, the Si substrate 211 is used as a seed layer for SiC growth (i.e., the Si substrate 211 is an exemplary embodiment of the seed layer 11), and thus, the Si substrate 211 may also be referred to herein as the Si seed layer 211 or the Si substrate / seed layer 211. The thickness of the Si substrate is not limited, although in some examples, it may be desirable to make the Si substrate thick enough to provide a desired level of physical support for the platform 210.

[0062] A mask 242 is formed on the top layer of the Si substrate 211, and the top layer corresponds to the (001) lattice plane of the Si substrate 211. For example, the mask 242 may include silicon dioxide (SiO2). One or more trenches 243 or other openings are formed in the mask 242 such that portions of the top layer of the substrate 211 are exposed from above. The term "trench" is used herein for simplicity, but it should be understood that the trench 243 may have various shapes, including but not limited to elongated trench / groove / channel shapes, circular or rectangular hole or well shapes, holes with irregular perimeters, or any desired shape. In addition, although the trench 243 is shown as having sidewalls arranged at 90 degrees (perpendicular) to the top surface of the Si substrate 211, the angle between the sidewall and the top surface (represented as α and β in Figure 8 may not be 90 degrees. For example, in some embodiments, the angles α and β between the sidewalls and the top surface of the Si substrate 211 may be between 10 degrees and 170 degrees and may include positively sloped sidewalls or negatively sloped (undercut) sidewalls. In addition, the slope of one sidewall does not need to be the same as the slope of the other sidewall (i.e., the angles α and β do not necessarily have to be equal). In some examples, the thickness of the mask layer is about 0.05 μm to 10 μm.

[0063] The SiC epitaxial layer 220 starts its growth in the trench 243 on the Si substrate / seeding layer 211, growing to fill the trench 243 and causing the mask 242 to overgrow laterally. Thus, the SiC epitaxial layer 220 includes a trench portion 221 disposed within the trench 243 and in contact with the top surface of the Si substrate / seeding layer 211, and an ELOG portion 222 that extends laterally on the mask 242 and faces / adjacent to the top surface of the mask 242. The SiC epitaxial layer 220 is an exemplary embodiment of the SiC epitaxial layer 20. In some examples, the thickness of the SiC epitaxial layer 220 is about 0.05 μm to 10 μm.

[0064] In some examples, the SiC-ELOG platform 210 can be used to form MEMS systems, such as MEMS sensors and actuators. In this case, the SiC layer can be used as the MEMS structural layer and the SiO2 mask can be used as the sacrificial release layer. In some examples, the SiC-ELOG platform 210 can be used to form quantum SiC color center integrated circuits. The SiC color centers can be formed by intentionally creating defects such as Si vacancies in the SiC layer. In some examples, the SiC-ELOG platform 210 can be used as a building block to form additional SiC platforms (such as the SiC platform 510 described below Figure 32 .

[0065] Turning Figures 7 to 12 , a method of fabricating the SiC-ELOG platform 210 will be described. For simplicity, the description of the method will focus on a single trench 243, but it should be understood that if there are multiple trenches, the same description applies to each individual trench 243. First, as Figure 7 shown, a silicon substrate 211 is provided. The silicon substrate 211 can be, for example, a Si wafer, and its top surface corresponds to the (001) lattice plane.

[0066] Next, as Figure 8 shown, a mask 242 is formed on the Si substrate 211. The mask 242 can be formed in various ways familiar to those of ordinary skill in the art, such as growing a thin film, followed by wet or dry etching to form one or more trenches 243 therein and expose a portion 244 of the top surface of the Si substrate 211 within the trenches 243.

[0067] Next, as Figure 9 shown, SiC epitaxial growth begins in the trench 243 on the exposed portion 244 of the Si substrate / seeding layer 211. Figure 9 Illustrates the initial part of the epitaxial growth process, in which only a portion 221' of the trench portion 221 has been formed in the trench 243. During this stage of the SiC epitaxial growth, the SiC mainly grows upward, as indicated by Figure 9as indicated by the arrow in []. In addition, since the epitaxial growth starts on the (001) surface of the Si substrate 211, the trench portion 221 of the SiC epitaxial layer 220 has a crystal orientation similar to that of the Si substrate 211 (i.e., the (001) lattice plane of the SiC epitaxial layer 220 can be parallel to the (001) lattice plane of the Si substrate 211).

[0068] As the epitaxial growth process continues, eventually, SiC reaches the top of the trench 243 (i.e., the trench portion 221 fills the trench 243), and then in addition to continuing to grow upward, the SiC epitaxial layer 220 starts to grow laterally outward on the mask 242, as shown by the Figure 10 arrow in []. Figure 10 shows an intermediate stage in the epitaxial growth process, in which multiple portions 222' of the ELOG portion 222 have been formed and partially extend on the mask 242. As the epitaxial growth process continues, eventually, the ELOG portion 222 of the SiC epitaxial layer 220 will grow laterally to extend on the mask 242 until the desired degree of overgrowth is achieved, as shown in Figure 11 [], and then the epitaxial growth process can be stopped. In some cases, the ELOG portion 222 of the SiC epitaxial layer 220 extends completely over the entire mask 242. When the ELOG portions 222 grow laterally from the trench portion 221, they maintain the same crystal orientation as the trench portion 221, which has the same crystal orientation as the Si substrate 211. Therefore, although the ELOG portions 222 do not directly abut the Si substrate 211 or grow directly from that Si substrate, since they are formed by ELOG from the trench portion 221 (which grows directly from the (001) surface of the substrate 211), they maintain the same crystal orientation as the Si substrate 211.

[0069] Next, as shown in Figure 12 [], in some examples, the top surface of the SiC epitaxial layer 220 can be planarized or smoothed by various known techniques such as chemical mechanical polishing (CMP), reactive ion etching (RIE), atomic layer etching (ALE), or a combination thereof. In particular, the top surface of the SiC epitaxial layer 220 may be somewhat rough not only due to normal variations that occur during epitaxy, but in the example of Figure 12 [], the top surface of the SiC epitaxial layer 220 may also specifically have a significant height difference at the boundary between the trench portion 221 and the ELOG portion 222 due to the growth pattern of the epitaxial layer 220 during the ELOG process. Therefore, in the platform 210 intended for applications that benefit from a smooth surface (such as photonics applications), a planarization step can be performed. In the platform 210 intended for applications that do not require a smooth surface (such as some MEMS applications), the planarization step can be omitted.

[0070] Turning Figure 13 , a third exemplary configuration of the SiC platform 10 will be described in the form of the SiC platform 310. The SiC platform 310 may also be referred to as the SiC-III-V platform 310 because, in this example, the III-V semiconductor layer 352 is disposed on the SiC epitaxial layer 320. The SiC-III-V platform 310 includes an Si substrate 311, an SiC epitaxial layer 320 formed on the Si substrate 311, and the III-V semiconductor layer 352 disposed on the SiC epitaxial layer 320.

[0071] The III-V semiconductor layer 352 may include any compound semiconductor that contains one or more elements from Group 13 (formerly Group III; also known as the boron group) of the periodic table of elements and one or more elements from Group 15 (formerly Group V; also known as the nitrogen group) of the periodic table of elements. In some examples, the thickness of the III-V semiconductor layer 352 is from about 0.05 μm to 20 μm.

[0072] The SiC epitaxial layer 352 is grown epitaxially from the substrate 311, and thus, the Si substrate 311 is an example embodiment of the seed layer 11. Accordingly, the Si substrate 311 may also be referred to herein as the Si substrate / seed layer 311. In some examples, the thickness of the SiC epitaxial layer 320 is from about 0.05 μm to 10 μm. The Si substrate / seed layer 311 may include a standard Si wafer having a (001) lattice plane parallel to its top surface. The thickness of the Si substrate 311 is not limited herein.

[0073] In some examples, the SiC-III-V platform 310 may be used to form high-power III-V electronic and optoelectronic devices. In some examples, due to the low refractive index of the SiC layer 320, the SiC epitaxial layer 320 may be used as a lower cladding in a III-V optical waveguide formed in the III-V layer 352.

[0074] Turning Figures 14 to 19 , a method of manufacturing the SiC-III-V platform 310 will be described. First, as Figure 14 shown, a silicon substrate 311 is provided. The silicon substrate 311 may be, for example, an Si wafer, the top surface of which corresponds to the (001) lattice plane.

[0075] Next, as Figure 15 shown, an SiC epitaxial layer 320 is grown epitaxially on the top surface of the Si substrate / seed layer 311. This results in the formation of a first intermediate platform 305.

[0076] Before, after, or simultaneously with the production of the first intermediate platform 305, a second intermediate platform 350 is provided, as Figure 16As shown. The second intermediate platform 350 includes a III-V substrate 351 and a III-V epitaxial layer 352 epitaxially formed on the III-V substrate 351. In some examples, the III-V epitaxial layer 352 and the III-V substrate 351 may include the same III-V semiconductor, but the III-V epitaxial layer 352 may have a different doping type and concentration from the III-V substrate 351. In other examples, the III-V substrate 351 may include a different III-V semiconductor material from the III-V epitaxial layer 352. In some examples, the III-V epitaxial layer 352 may be composed of a single layer or multiple layers of III-V semiconductors. In some examples, providing the second intermediate platform 350 includes forming the second intermediate platform 350 by growing a III-V epitaxial layer 352 on the III-V substrate 351 through techniques familiar to those of ordinary skill in the art. In other examples, providing the second intermediate platform 350 includes purchasing or otherwise obtaining possession and / or control of the already formed second intermediate platform 350.

[0077] Once both the first intermediate platform 305 and the second intermediate platform 350 have been provided, they can be joined together, as Figures 17 to 18 shown. More specifically, the first intermediate platform 305 and the second intermediate platform 350 are positioned such that the III-V epitaxial layer 352 and the SiC epitaxial layer 320 face each other, as Figure 17 shown, and then, they can be moved together such that the layers 352 and 320 are in contact, as Figure 18 shown. The contact surfaces of these layers 352 and 320 can be directly joined to each other without any intermediate layer, for example, by oxide-free interfacial layer bonding or by any other bonding method. Although not illustrated, in some examples, the SiC epitaxial layer 320 and / or the III-V epitaxial layer 352 may be polished / smoothed before or as part of the bonding process to facilitate better bonding.

[0078] In Figures 17 to 18 the second intermediate platform 350 is shown as inverted (flipped) and disposed on top of the first intermediate platform 305 for bonding, but in other examples, the first intermediate platform 305 may be inverted and disposed on top of the second intermediate platform 350 for bonding. In other words, the orientation of the intermediate platforms 305 and 350 relative to the ground or some other external reference frame during bonding is not restricted herein. Instead, only their orientation relative to each other during bonding is restricted as shown and described.

[0079] Next, as Figure 19As shown in, the III-V substrate layer 351 can be removed. This reveals the top surface of the III-V epitaxial layer 352 now (which was previously its bottom surface in the Figure 16 orientation). The remaining layers 311, 320, and 352 form the Si-III-V platform 310. The III-V substrate layer 351 can be removed by grinding, CMP, wet or dry etching, or a combination thereof.

[0080] Turning to Figure 20 , a fourth example configuration of the SiC platform 10 will be described in the form of the SiC platform 410. The SiC platform 410 can also be referred to as a buried SiC platform 410 because in this example, the SiC epitaxial layer 420 is buried (i.e., disposed between two other layers). The buried SiC platform 410 includes an Si substrate 415, an SiC epitaxial layer 420 stacked on the Si substrate 415, an Si device layer 431 stacked on the SiC epitaxial layer 420, and a BOX layer 432 disposed on the Si device layer 431.

[0081] In some examples, the Si device layer 431 and the BOX layer 432 can initially be part of an SOI substrate 430 for forming the platform 410 (see Figure 23 and Figure 27 ). In some examples, the SOI substrate 430 can be similar to the SOI substrate 130 described above. As described in more detail below, the processing part 433 of the SOI substrate 430 can be removed during the fabrication of the platform 410, and thus, the processing part 433 does not appear in Figure 20 .

[0082] The SiC epitaxial layer 420 is epitaxially formed on the Si seed layer 411, where, depending on the implementation of the buried SiC platform 410, the seed layer 411 is either the Si substrate 415 or the Si device layer 431. More specifically, in some implementations of the buried SiC platform 410, the SiC epitaxial layer 420 is epitaxially formed on the Si substrate 415, in which case the Si substrate 415 is the seed layer 411 and can be referred to as the Si substrate / seed layer 415, 411. In other implementations of the buried SiC platform 410, the SiC epitaxial layer 420 is epitaxially formed on the Si device layer 431, in which case the Si device layer 431 is the seed layer 411 and can be referred to as the Si device / seed layer 431, 411. The Si substrate 415 as the seed layer 411 is one example implementation of the seed layer 11, and similarly, the Si device layer 431 as the seed layer 411 is another example implementation of the seed layer 11. In some examples, the thickness of the SiC epitaxial layer 420 is about 0.05 μm to 10 μm.

[0083] In some examples, the BOX layer 432 can be used as an etch mask to subsequently pattern the Si device layer 431 by dry or wet etching, for example, to form devices in the Si device layer 431 and / or the SiC epitaxial layer 420.

[0084] In some examples, the buried SiC platform 410 can be used to form active and passive photonic integrated circuits (PICs), much like PICs formed on SOI wafers. The SiC epitaxial layer performs the same function as the BOX layer in an SOI wafer to implement the PIC. Additionally, the SiC layer has a much higher thermal conductivity than the BOX layer, and thus, heat can be more efficiently diffused away from active photonic devices such as lasers, modulators, and photodetectors.

[0085] Turning Figures 21 to 26 , a first method of fabricating the buried SiC platform 410 will be described. First, as Figure 21 shown, a silicon substrate 415 is provided. The silicon substrate 415 can be, for example, an Si wafer, and its top surface corresponds to the (001) lattice plane.

[0086] Next, as Figure 22 shown, the SiC epitaxial layer 420 is epitaxially grown from the top surface of the Si substrate 415. Thus, in this method, the Si substrate 415 serves as the seed layer 411. The result is the first intermediate platform 405.

[0087] Before, after, or simultaneously with the formation of the first intermediate platform 405, an SOI substrate 430 is provided, as shown in the figure. The SOI substrate 430 can be similar to the SOI substrate 130 described above and can include an Si processing portion 433, a BOX layer 432, and an Si device layer 431.

[0088] Once both the first intermediate platform 405 and the SOI substrate 430 have been provided, they can be bonded together, as Figures 24 to 25 shown. More specifically, the first intermediate platform 405 and the SOI substrate 430 are positioned such that the Si device layer 431 and the SiC epitaxial layer 420 face each other, as Figure 24 shown, and then, they can be moved together such that these layers 431 and 420 are in contact, as Figure 25As shown. The contact surfaces of these layers 431 and 420 can be directly bonded to each other without any intermediate layer, for example, by bonding through an oxide-free interface layer or by any other bonding method. In this way, the SiC epitaxial layer 420 is buried between the Si device layer 431 and the Si substrate 415. Although not shown, in some examples, before the bonding process or as part of the bonding process, the SiC epitaxial layer 420 and / or the Si device layer 431 can be polished / smoothed to promote better bonding.

[0089] In Figures 24 to 25 , the SOI substrate 430 is shown as inverted (flipped) and disposed on top of the first intermediate platform 405 for bonding, but in other examples, the first intermediate platform 405 can be inverted and disposed on top of the SOI substrate 430 for bonding. In other words, the orientation of the intermediate platform 405 and the SOI substrate 430 relative to the ground or some other external reference frame during bonding is not restricted herein. Instead, only their orientation relative to each other during bonding is restricted as shown and described.

[0090] Next, as Figure 26 shown, the Si processing portion 433 can be removed. This reveals the top surface of the now BOX layer 432 (which was once its bottom surface in the Figure 23 orientation). The remaining layers 415(411), 420, 431, and 432 form the buried SiC platform 410. The Si processing portion layer 433 can be removed by grinding, CMP, plasma etching, or a combination thereof. The BOX (e.g., SiO2) layer 432 can be used as an etch stop for CMP and plasma etching to remove the Si processing portion 433. The BOX layer 432 can also be referred to herein as the oxide layer after the Si processing portion 433 has been removed because in this state the layer is no longer buried.

[0091] Turning to Figures 27 to 31 , a second method of manufacturing the buried SiC platform 410 will be described. First, as Figure 27 shown, a SiC-on-SOI platform 406 is provided. The SiC-on-SOI platform 406 corresponds to the SiC-on-SOI platform 110 described above and includes an SOI substrate 430 (including the Si processing portion 433, the BOX layer 432, the SOI substrate) and a SiC epitaxial layer 420 formed by epitaxial growth on the SOI substrate 430 (specifically, on the Si device layer 431). Thus, in this method of manufacturing the buried SiC platform 410, the Si device layer 431 acts as the seed layer 411.

[0092] Before, after, or at the same time as providing the SiC platform 406 on SOI, a Si substrate 415 is provided, as Figure 28 shown in. The silicon substrate 415 can be, for example, a Si wafer.

[0093] Once both the SiC platform 406 on SOI and the Si substrate 415 have been provided, they can be bonded together, as Figures 29 to 30 shown in. More specifically, the SiC platform 406 on SOI and the Si substrate 415 are positioned such that the Si substrate 415 and the SiC epitaxial layer 420 face each other, as Figure 29 shown in, and then, they can be moved together such that these layers 415 and 420 are in contact, as Figure 30 shown in. The contact surfaces of these layers 415 and 420 can be directly bonded to each other without any intermediate layer, for example, by oxide-free interface layer bonding or by any other bonding method. In this way, the SiC epitaxial layer 420 is buried between the Si device layer 431 and the Si substrate 415. Although not shown, in some examples, the SiC epitaxial layer 420 and / or the Si substrate 415 can be polished / smoothed before or as part of the bonding process to facilitate better bonding.

[0094] In Figures 29 to 30 the Si substrate 415 is shown as being disposed on top of the SiC platform 406 on SOI for bonding, but in other examples, the SiC platform 406 on SOI can be inverted and disposed on top of the Si substrate 415 for bonding. In other words, the orientation of the SiC platform 406 on SOI and the Si substrate 415 relative to the ground or some other external reference frame during bonding is not limited herein; rather, only their orientation relative to each other during bonding is limited as shown and described.

[0095] Next, as Figure 31 shown in, the Si processing section 433 can be removed. This reveals the top surface of the now BOX layer 432 (which was its bottom surface in the Figure 29 orientation). The remaining layers 415, 420, 431(411), and 432 form the buried SiC platform 410. The Si processing section layer 433 can be removed by grinding, CMP, plasma etching, or a combination thereof. The BOX (e.g., SiO2) layer 432 can be used as an etch stop for CMP and plasma etching to remove the Si processing section 433.

[0096] Turning to Figure 32, a fifth example configuration of the SiC platform 10 will be described in the form of the SiC platform 510. The SiC platform 510 may also be referred to as the III-V platform 510 on SiC-ELOG because in this example, the III-V layer 552 is disposed on the SiC epitaxial layer 520 including the ELOG portion. In other words, the III-V platform 510 on SiC-ELOG includes a modified version of the SiC-ELOG platform 210 described above, where the III-V layer 552 has been disposed on and incorporated into the SiC epitaxial layer of the SiC-ELOG platform 210. More specifically, the SiC-ELOG platform 210 includes an Si substrate / seeding layer 511, a mask 542 formed on the Si substrate / seeding layer 511 (with trenches formed therein), an SiC epitaxial layer 520 formed from the Si substrate / seeding layer 511 (via the trenches) by ELOG and laterally extending on the mask 542, and a III-V epitaxial layer 552 disposed on the SiC epitaxial layer 520. In this example, the Si substrate / seeding layer 511 is a configuration of the seeding layer 11.

[0097] In some examples, the III-V platform 510 on SiC-ELOG can be used to form high-power lasers, modulators, and photodetectors.

[0098] Turning Figures 33 to 37 , a method of manufacturing the III-V platform 510 on SiC-ELOG will be described. First, as Figure 33 shown, the SiC-ELOG platform 507 can be provided. The SiC-ELOG platform 507 corresponds to the SiC-ELOG platform 210 described above and includes an Si substrate / seeding layer 511, a mask 542 formed on the Si substrate / seeding layer 511 (with trenches formed therein), and an SiC epitaxial layer 520 formed from the Si substrate / seeding layer 511 (via the trenches) by ELOG and laterally extending on the mask 542.

[0099] Before, after, or simultaneously with providing the SiC-ELOG platform 507, a III-V intermediate platform 550 is provided, as Figure 34 shown. The III-V intermediate platform 550 is similar to the second intermediate platform 350 described above and may include a III-V substrate 551 and a III-V epitaxial layer 552 epitaxially formed on the III-V substrate 551.

[0100] Once both the SiC-ELOG platform 507 and the III-V intermediate platform 550 have been provided, they can be bonded together, as Figures 35 to 36As shown. More specifically, the SiC-ELOG platform 507 and the III-V intermediate platform 550 are positioned such that the III-V epitaxial layer 552 and the SiC epitaxial layer 520 face each other, as Figure 35 shown, and then they can be moved together such that these layers 552 and 520 are in contact, as Figure 36 shown. The contact surfaces of these layers 552 and 520 can be directly bonded to each other without any intermediate layer, for example, by oxide-free interfacial layer bonding or by any other bonding method. Although not shown, in some examples, the SiC epitaxial layer 520 and / or the III-V epitaxial layer 552 can be polished / smoothed before or as part of the bonding process to facilitate better bonding.

[0101] In Figures 35 to 36 , the III-V intermediate platform 550 is shown as inverted and disposed on top of the SiC-ELOG platform 507 for bonding, but in other examples, the SiC-ELOG platform 507 can be inverted and disposed on top of the III-V intermediate platform 550 for bonding. In other words, the orientation of the SiC-ELOG platform 507 and the III-V intermediate platform 550 relative to the ground or some other external reference frame during bonding is not restricted herein. Instead, only their orientation relative to each other during bonding is restricted as shown and described.

[0102] Next, as Figure 37 shown, the III-V substrate 551 can be removed. This reveals the top surface of the now III-V epitaxial layer 552 (which was its bottom surface in the Figure 34 orientation). The remaining layers 511, 542, 520, and 552 form the III-V-SiC-ELOG platform 510. The III-V substrate 551 can be removed by grinding, CMP, wet or dry etching, or a combination thereof.

[0103] It should be understood that both the general description and the detailed description provide exemplary explanations in nature and are intended to provide an understanding of the present disclosure without limiting the scope of the present disclosure. Various mechanical, compositional, structural, electronic, and operational changes can be made without departing from the scope of this specification and the claims. In some instances, well-known circuits, structures, and techniques are not shown or described in detail to avoid obscuring these examples. In two or more figures, the same numbers represent the same or similar elements.

[0104] In addition, unless the context otherwise requires, the singular forms "a," "an," and "the" are intended to include the plural forms as well. Further, the terms "comprises," "comprising," "includes," and the like specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. Unless expressly stated otherwise, components described as being coupled may be directly electrically or mechanically coupled, or may be indirectly coupled via one or more intermediate components. Unless the context of the specification otherwise requires, mathematical and geometric terms need not be used in their strictest sense, since one of ordinary skill in the art will understand that, for example, substantially similar elements that function in a substantially similar manner may readily fall within the scope of a descriptive term even if that term also has a strict definition.

[0105] And / or: Occasionally, the phrase "and / or" is used in this document in conjunction with a list of enumerated items. This phrase means that any combination of the items in the list may be included - from a single item to all items, and any permutation therebetween. Thus, for example, "A, B, and / or C" means one of "{A}, {B}, {C}, {A, B}, {A, C}, {C, B}, and {A, C, B}".

[0106] Elements and their related aspects described in detail with reference to one example may, where practicable, be included in other examples in which they are not specifically shown or described. For example, if an element is described in detail with reference to one example and not described with reference to a second example, the element may still be claimed as being included in the second example.

[0107] In addition, unless otherwise specified herein or otherwise implied by the context, when approximate terms such as "substantially," "approximately," "about," "around," "roughly" are used, this is to be understood as meaning that mathematical precision is not required, but rather refers to a range of variation that includes but is not strictly limited to the stated value, characteristic, or relationship. In particular, except for any ranges (if any) expressly recited herein, the range of variation implied by the use of such approximate terms includes at least any immaterial variations and those variations that are typical for items of the type being discussed due to manufacturing tolerances or other tolerances in the relevant field. In any event, unless otherwise indicated, the range of variation may include values within at least ±1% of the recited value, characteristic, or relationship.

[0108] Given the disclosure herein, many modifications and variations will be apparent to those of ordinary skill in the art. For example, the devices and methods may include additional components or steps that are omitted from the figures and description for clarity of operation. Accordingly, this description is to be construed only as illustrative and is for the purpose of teaching those of skill in the art the general manner of carrying out the teachings. It is to be understood that the various examples shown and described herein are to be considered exemplary. Those shown and described herein may be replaced by elements and materials, and the arrangement of those elements and materials, components and processes may be reversed, and certain features of the teachings may be utilized independently, all of which will be apparent to those of skill in the art upon benefit of the description herein. Changes may be made to the elements described herein without departing from the scope of the teachings and the appended claims.

[0109] It is to be understood that the specific examples set forth herein are non-limiting and that modifications may be made to the structure, dimensions, materials, and methods without departing from the scope of the teachings.

[0110] Considering the specification and practice of the invention disclosed herein, other examples in accordance with this disclosure will be apparent to those of skill in the art. The specification and examples are to be considered only as exemplary, and the following claims are to be given their broadest scope, including equivalents under applicable law.

Claims

1. A method for manufacturing a silicon carbide platform, the method comprising: providing a substrate including a silicon seed layer, the silicon seed layer having a (001) lattice plane and a top surface parallel to the (001) lattice plane; as well as A silicon carbide epitaxial layer is formed directly on the top surface of the silicon seed layer by epitaxial growth.

2. The method according to claim 1, in, The base comprises a silicon-on-insulator (SOI) substrate, the silicon-on-insulator substrate comprising a first silicon substrate, a buried oxide (BOX) layer and a silicon device layer, and Wherein, the silicon seed layer includes the silicon device layer of the SOI substrate.

3. The method of claim 2, further comprising: An electronic device, an optical device, an optoelectronic device, an integrated circuit and / or a photonic integrated circuit is formed at least partially in the silicon carbide epitaxial layer and / or in the silicon device layer.

4. The method of claim 2, further comprising: providing a second silicon substrate; bonding the second silicon substrate to the silicon carbide epitaxial layer; as well as The first silicon substrate is removed to expose the BOX layer.

5. The method of claim 4, further comprising: An electronic device, an optical device, an optoelectronic device, an integrated circuit and / or a photonic integrated circuit is formed at least partially in the silicon carbide epitaxial layer and / or in the silicon device layer.

6. The method according to claim 1, in, The base includes a silicon substrate and a mask formed on the silicon substrate; Wherein, the silicon seed layer includes the silicon substrate; wherein one or more trenches are formed in the mask to expose portions of the top surface of the silicon substrate; and Wherein, forming the silicon carbide epitaxial layer on the silicon seed layer by epitaxial growth comprises: epitaxially growing silicon carbide on exposed portions of the top surface of the silicon substrate in the one or more trenches; and The silicon carbide is extended laterally from the one or more trenches on the mask by epitaxial lateral overgrowth to form the silicon carbide epitaxial layer, wherein one or more portions of the silicon carbide epitaxial layer are disposed on the mask.

7. The method according to claim 6, in, The mask includes a silicon dioxide layer.

8. The method of claim 6, further comprising: An electronic device, an optical device, an optoelectronic device, an integrated circuit, a photonic integrated circuit, and / or a micro-electromechanical system is formed at least partially in the silicon carbide epitaxial layer.

9. The method of claim 6, further comprising: Providing a III-V platform, the III-V platform comprising a III-V substrate and a III-V epitaxial layer on the III-V substrate; bonding the III-V epitaxial layer to the silicon carbide epitaxial layer; as well as The III-V substrate is removed to expose the III-V epitaxial layer.

10. The method of claim 9, further comprising: The silicon carbide epitaxial layer is planarized prior to bonding the III-V epitaxial layer to the silicon carbide epitaxial layer.

11. The method of claim 9, further comprising: An electronic device, an optical device, an optoelectronic device, an integrated circuit, a photonic integrated circuit and / or a micro-electromechanical system is formed at least partially in the silicon carbide epitaxial layer and / or in the III-V epitaxial layer.

12. The method of claim 1, in, The base comprises a silicon substrate; Wherein, the silicon seed layer includes the silicon substrate; and Wherein, the method further comprises: Providing a III-V platform, the III-V platform comprising a III-V substrate and a III-V epitaxial layer; bonding the III-V epitaxial layer to the silicon carbide epitaxial layer; and The III-V substrate is removed to expose the III-V epitaxial layer.

13. The method of claim 12, further comprising: An electronic device, an optical device, an optoelectronic device, an integrated circuit and / or a photonic integrated circuit is formed at least partially in the silicon carbide epitaxial layer and / or in the III-V epitaxial layer.

14. The method of claim 1, further comprising: providing a silicon-on-insulator (SOI) substrate, the silicon-on-insulator substrate comprising a first silicon substrate, a buried oxide (BOX) layer and a silicon device layer, wherein the base comprises a second silicon substrate and the silicon seed layer comprises the second silicon substrate; and Wherein, the method further comprises: bonding the silicon device layer to the silicon carbide epitaxial layer; and The first silicon substrate is removed to expose the BOX layer.

15. The method of claim 14, further comprising: Electronic devices, optical devices, optoelectronic devices, integrated circuits and / or photonic integrated circuits are formed at least partially in the silicon carbide epitaxial layer and / or in the Si device layer.

16. A silicon carbide platform, comprising: a substrate comprising a silicon seed layer having a (001) lattice plane and a top surface parallel to the (001) lattice plane; as well as A silicon carbide epitaxial layer is formed directly on the top surface of the silicon seed layer by epitaxial growth.

17. The silicon carbide platform according to claim 16, in, The base comprises a silicon-on-insulator (SOI) substrate, the silicon-on-insulator substrate comprising a first silicon substrate, a buried oxide (BOX) layer on the first silicon substrate, and a silicon device layer on the BOX layer, and Wherein, the silicon seed layer includes the silicon device layer of the SOI substrate.

18. The silicon carbide platform of claim 16, further comprising: in, The base comprises a silicon substrate, the silicon carbide epitaxial layer on the silicon substrate, a silicon device layer on the silicon carbide epitaxial layer, and an oxide layer on the silicon device layer, and Wherein, the silicon seed layer includes the silicon device layer.

19. The silicon carbide platform of claim 16, further comprising: in, The base comprises a silicon substrate, the silicon carbide epitaxial layer on the silicon substrate, a silicon device layer on the silicon carbide epitaxial layer, and an oxide layer on the silicon device layer, and Wherein, the silicon seed layer includes the silicon substrate.

20. The silicon carbide platform according to claim 16, in, The base includes a silicon substrate and a mask formed on the silicon substrate; Wherein, the silicon seed layer includes the silicon substrate; wherein one or more trenches are formed in the mask to expose portions of the top surface of the silicon substrate; and Wherein, the silicon carbide epitaxial layer comprises: a trench portion disposed in the one or more trenches on an exposed portion of the top surface of the silicon substrate and epitaxially grown from the exposed portion; and One or more portions are disposed on the mask and grown from the trench portion by epitaxial lateral overgrowth.

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