High voltage generation circuit and memory

Abstract

The invention provides a high voltage generation circuit and a memory, and the circuit comprises a voltage sampling module which is used for sampling the output voltage of a charge pump, the voltage sampling module comprises a first voltage dividing unit and a second voltage dividing unit which are connected in series between the output voltage and a reference ground, and the output node of the first voltage dividing unit and the output node of the second voltage dividing unit output a sampling voltage, the first voltage dividing unit comprises N MOS (Metal Oxide Semiconductor) tubes which are connected in series and are in diode connection, and the second voltage dividing unit comprises M MOS tubes which are connected in series and are in diode connection; the comparator is used for comparing the sampling voltage with reference voltage and outputting a comparison result; the charge pump raises the output voltage when the sampling voltage is smaller than the reference voltage; when the sampling voltage is greater than or equal to the reference voltage, the charge pump stops working, and the voltage sampling module enters a hold mode. According to the invention, sampling is realized by adopting the MOS tubes connected by diodes connected in series, so that the complexity is reduced; the inverse size is adopted, so that the area of the whole circuit is reduced; and the power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a high voltage generating circuit and a memory. Background Art

[0002] In a memory (such as a large-capacity FLASH), in order to realize the "reading", "writing" and "erasing" of information, it is usually necessary to generate a positive high voltage (ranging from a few volts to tens of volts, set according to the memory type and design requirements) as an operating voltage. As the capacity of the memory chip increases, the load capacitance of the word line decoding circuit is larger, the charging time is longer, and the requirement for the establishment time of the operating voltage is also increased. If the operating voltage is unstable, it will cause operational errors. In order to meet the accuracy of the operation and speed up the establishment speed, it is necessary to maintain the operating voltage in the standby mode at a high voltage state; at this time, the load current of the operating voltage in the standby mode is very small, so it seems that the current consumed by the circuit generating the high voltage accounts for a large proportion, which increases the power consumption in the standby state and does not meet the design requirements of low power consumption in the standby state.

[0003] Therefore, how to reduce power consumption while ensuring high voltage stable output has become one of the problems that technical personnel in this field need to solve urgently.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a high voltage generating circuit and a memory, so as to solve the problem of high power consumption of the high voltage generating circuit in the prior art.

[0006] In order to achieve the above-mentioned object and other related objects, the present invention provides a high voltage generating circuit, wherein the high voltage generating circuit at least comprises:

[0007] Voltage sampling module, comparator and charge pump;

[0008] The voltage sampling module samples the output voltage of the charge pump, and the voltage sampling module includes a first voltage dividing unit and a second voltage dividing unit connected in series between the output voltage and the reference ground, and the output nodes of the first voltage dividing unit and the second voltage dividing unit output the sampling voltage, wherein the first voltage dividing unit includes N MOS transistors connected in series with diodes, and the second voltage dividing unit includes M MOS transistors connected in series with diodes, and N and M are natural numbers greater than or equal to 1;

[0009] The comparator is connected to the output terminal of the voltage sampling module, compares the sampled voltage with a reference voltage, and outputs a comparison result;

[0010] The charge pump is connected to the output terminal of the comparator. When the sampled voltage is less than the reference voltage, it raises the output voltage; when the sampled voltage is greater than or equal to the reference voltage, the charge pump stops working and the voltage sampling module enters the hold mode.

[0011] Optionally, each MOS transistor adopts an inverse ratio size.

[0012] Optionally, the MOS transistors in the first voltage dividing unit and the second voltage dividing unit have the same size.

[0013] Optionally, the MOS transistors in the first voltage dividing unit and the second voltage dividing unit are NMOS transistors, and the gates and drains of the NMOS transistors are connected together.

[0014] Optionally, the MOS transistors in the first voltage dividing unit and the second voltage dividing unit are PMOS transistors, and the gates and drains of the PMOS transistors are connected together.

[0015] Optionally, the voltage sampling module further includes an enabling unit, and the enabling unit is connected in series with the first voltage dividing unit and the second voltage dividing unit.

[0016] More optionally, the enabling unit includes a PMOS transistor, the source is connected to the output voltage, the drain is connected to the first voltage dividing unit, and the gate receives an enabling signal.

[0017] Optionally, the charge pump includes an oscillator and a boosting unit;

[0018] The oscillator provides a clock signal;

[0019] The enabling end of the boosting unit receives the comparison result, the control end receives the clock signal, and generates a preset voltage. Optionally, the average current of the high-voltage generating circuit satisfies:

[0020] I 2 = T 1 / (T 1 + T 2 )* I 1 ;

[0021] Wherein, I 1 is the current for voltage division of the voltage sampling module, I 2 is the average current of the high-voltage generating circuit, T 1 is the working time of the charge pump, T 2 is the hold time of the voltage sampling module, and T 1 < T2 。

[0022] To achieve the above object and other related objects, the present invention further provides a memory, which at least includes the above high-voltage generating circuit, and the high-voltage generating circuit is used to provide the high voltage required for the erase and write operations for the memory array in the memory.

[0023] As described above, the high-voltage generating circuit and the memory of the present invention have the following beneficial effects:

[0024] The high-voltage generating circuit and the memory of the present invention use MOS transistors connected in series in the diode connection method to achieve sampling, reducing the complexity and ensuring the stability of the final output of the charge pump without the need for refreshing; and using an inverse ratio size, the device size is greatly reduced, thereby reducing the area of the overall circuit; in addition, the load current of the charge pump in the standby mode is small, and the power consumption of the voltage sampling module is also very low, so the power consumption of the entire high-voltage generating circuit is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is shown as a schematic structural diagram using resistor voltage division.

[0026] Figure 2 It is shown as a schematic structural diagram using capacitor voltage division.

[0027] Figure 3 It is shown as a schematic structural diagram of the high-voltage generating circuit of the present invention.

[0028] Figure 4 It is shown as a schematic structural diagram of the charge pump of the present invention.

[0029] Description of Component Labels

[0030] 1 High-voltage generating circuit

[0031] 11 Voltage sampling module

[0032] 111 First voltage division unit

[0033] 112 Second voltage division unit

[0034] 113 Enable unit

[0035] 12 Comparator

[0036] 13 Charge pump

[0037] 131 Oscillator

[0038] 132 Boosting unit DETAILED DESCRIPTION OF THE INVENTION

[0039] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please refer to Figures 1 to 4 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0041] To generate a stable high voltage, modules such as a charge pump, a sampling circuit, and a comparator are required; traditional sampling circuits are implemented through resistor voltage division or capacitor voltage division. As Figure 1 shown, the resistor voltage division method divides the input voltage Vin through two series voltage dividing resistors R1 and R2 to obtain the voltage Vout after voltage division; due to the linear characteristics of the voltage division circuit depending on the accuracy and stability of the resistors, the anti-interference ability is significantly insufficient when encountering severe voltage fluctuations or interference; in addition, although the resistor voltage division method can reduce power consumption, the resistor size is relatively large, which affects the overall area. As Figure 2 shown, the capacitor voltage division method utilizes the charge and discharge characteristics of capacitors and the law of conservation of charge to obtain the voltage Vout after voltage division by detecting the size and change value of the capacitance of the series capacitors C1 and C2; the disadvantage of capacitor voltage division is that the middle node between the two capacitors is in a floating state, and the entry of external electrons or the leakage of charge at this node will cause the capacitor voltage division circuit to not accurately divide the voltage, resulting in the final output high voltage being too high or too low.

[0042] To solve the above problems, the present invention provides a high-voltage generating circuit 1, as Figure 3 shown, the high-voltage generating circuit 1 includes: a voltage sampling module 11, a comparator 12, and a charge pump 13.

[0043] As Figure 3 shown, the voltage sampling module 11 samples the output voltage VHIGH of the charge pump.

[0044] Specifically, the voltage sampling module 11 includes a first voltage dividing unit 111 and a second voltage dividing unit 112 connected in series between the output voltage VHIGH and the reference ground GNDA. The output node of the first voltage dividing unit 111 and the second voltage dividing unit 112 outputs a sampling voltage Vcs. Among them, the first voltage dividing unit 111 includes N MOS transistors connected in series in the diode connection, and the second voltage dividing unit 112 includes M MOS transistors connected in series in the diode connection. N and M are natural numbers greater than or equal to 1; the values of N and M are determined according to the requirements of the output voltage VHIGH and the reference voltage VREF. The values of N and M can be configured to be the same or different; as an example, N is set to 4 and M is set to 1.

[0045] More specifically, as an implementation manner of the present invention, the MOS transistors in the first voltage dividing unit 111 and the second voltage dividing unit 112 are NMOS transistors, and the gates and drains of the NMOS transistors are connected together to form a diode. As Figure 3 shown, the sources and drains of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 are connected in series in turn to form the first voltage dividing unit 111, and the gates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 are respectively connected to their drains, and the substrates are connected to the reference ground GNDA; the sixth NMOS transistor N6 serves as the second voltage dividing unit 112, the drain and the gate are connected to the source of the fifth NMOS transistor N5, and the source and the substrate are connected to the reference ground GNDA.

[0046] More specifically, as another implementation manner of the present invention, the MOS transistors in the first voltage dividing unit 111 and the second voltage dividing unit 112 are PMOS transistors, and the gates and drains of the PMOS transistors are connected together to form a diode, which will not be elaborated here one by one.

[0047] Specifically, in this example, the sizes of the MOS transistors (the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6) in the first voltage dividing unit 111 and the second voltage dividing unit 112 are the same. In actual use, the sizes of the MOS transistors can be configured differently as long as the set voltage dividing effect can be achieved. In this embodiment, the MOS transistors (the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6) adopt an inverse ratio size, that is, the width-to-length ratio (W / L) of the MOS transistor is less than 1, so as to reduce the size and reduce the influence caused by the changes of the process corner and temperature, and at the same time reduce the power consumption of the voltage sampling module 11 by increasing the on-resistance.

[0048] As another implementation of the present invention, the voltage sampling module 11 further includes an enable unit 113. The enable unit 113 is connected in series with the first voltage dividing unit 111 and the second voltage dividing unit 112, and the position is not limited as long as the enabling function can be achieved. When the enable signal EN is valid, the enable unit 113 conducts, and the voltage sampling module 11 starts to work. When the enable signal EN is invalid, the enable unit 113 turns off, and the voltage sampling module 11 stops working. As an example, the enable unit 113 is implemented by a PMOS transistor P1. The source of the PMOS transistor P1 is connected to the output voltage VHIGH, the drain is connected to the first voltage dividing unit 111 (the drain of the first NMOS transistor N1), and the gate receives the enable signal EN.

[0049] As Figure 3 shown, the comparator 12 is connected to the output terminal of the voltage sampling module 11, compares the sampled voltage Vcs with the reference voltage VREF, and outputs a comparison result CP_en.

[0050] Specifically, the sampled voltage Vcs and the reference voltage VREF can be respectively set at the positive input terminal and the negative input terminal of the comparator 12 as needed. In this example, the sampled voltage Vcs is connected to the negative input terminal of the comparator 12, and the reference voltage VREF is connected to the positive input terminal of the comparator 12. When the sampled voltage Vcs is greater than the reference voltage VREF, the comparator 12 outputs a low level. When the sampled voltage Vcs is less than the reference voltage VREF, the comparator 12 outputs a high level. The comparison result CP_en serves as the enable signal of the charge pump 13. In this example, the comparison result CP_en is active high (the charge pump 13 works).

[0051] As Figure 3 shown, the charge pump 13 is connected to the output terminal of the comparator 12. When the sampled voltage Vcs is less than the reference voltage VREF, it raises the output voltage VHIGH. When the sampled voltage Vcs is greater than or equal to the reference voltage VREF, the charge pump 13 stops working, and the voltage sampling module 11 enters the hold mode.

[0052] Specifically, as Figure 4 shown, as an example, the charge pump 13 includes an oscillator 131 and a boosting unit 132. The oscillator 131 is used to provide a clock signal clk with a certain frequency. The enable terminal of the boosting unit 132 receives the comparison result CP_en, and the control terminal receives the clock signal clk. When the comparison result CP_en is valid, the switch array in the boosting unit 132 is controlled by the clock signal clk and switches according to a predetermined order and time interval, thereby realizing the boosting function and generating a preset voltage.

[0053] As Figure 3 shown, the average current I 2 of the high-voltage generating circuit 1 of the present invention satisfies:

[0054] I 2 = T 1 / (T 1 + T 2 ) * I 1 ;

[0055] Wherein, I 1 is the current divided by the voltage sampling module 11, and T 1 is the working time of the charge pump 13 (i.e., the time when the sampling voltage Vcs is less than the reference voltage VREF), and T 2 is the holding time of the voltage sampling module 11 (i.e., the time when the sampling voltage Vcs is greater than or equal to the reference voltage VREF). In the standby mode, the working time of the charge pump 13 is much less than the holding time of the voltage sampling module 11 (T 1 < T 2 ).

[0056] As Figure 3 shown, the working principle of the high-voltage generating circuit 1 of the present invention is as follows:

[0057] In the standby mode, the enable signal EN = 0. At this time, the PMOS transistor P1 is turned on, and each MOS transistor in the first voltage dividing unit 111 and the second voltage dividing unit 112 starts to work. After the output voltage VHIGH is divided by the MOS transistors connected in diode configuration, the sampling voltage Vcs is quickly generated. If the sampling voltage Vcs is lower than the reference voltage VREF, the comparator 12 outputs a high level, and the charge pump 13 works and makes the output voltage VHIGH reach the target value. When the output voltage VHIGH reaches the target value, the sampling voltage Vcs generated by dividing the voltage by the MOS transistors is higher than the reference voltage VREF. At this time, the charge pump 13 stops working, and the voltage sampling module 11 enters the holding mode.

[0058] In the standby mode, the load current of the charge pump 13 is small. At this time, if the current consumed by the voltage sampling module 11 is relatively large, the sampling voltage Vcs will quickly be lower than the reference voltage VREF, resulting in frequent charging and discharging of the charge pump 13; while the power consumption of the voltage sampling module 11 of the present invention is relatively low, and it can maintain the sampling voltage Vcs at the reference voltage VREF for a long time, avoiding frequent charging and discharging of the charge pump 13 and meeting the low-power requirement in the standby mode (the present invention greatly reduces the power consumption while ensuring that the voltage in the standby mode is the same as the actual operating voltage).

[0059] The present invention also provides a memory, which at least includes the high-voltage generating circuit 1 of the present invention. The high-voltage generating circuit 1 is used to provide the high voltage required for various operations (including but not limited to "read", "write", "erase") in the memory array of the memory. As an example, the memory also includes but is not limited to a memory array, a word line strobe unit, a bit line strobe unit, a data reading unit, a source voltage selection unit, and a well voltage selection unit, which will not be elaborated here one by one.

[0060] In summary, the present invention provides a high-voltage generating circuit and a memory, including: a voltage sampling module, a comparator, and a charge pump; the voltage sampling module samples the output voltage of the charge pump. The voltage sampling module includes a first voltage dividing unit and a second voltage dividing unit connected in series between the output voltage and the reference ground. The output nodes of the first voltage dividing unit and the second voltage dividing unit output a sampling voltage. Among them, the first voltage dividing unit includes N MOS transistors connected in series in the diode connection mode, and the second voltage dividing unit includes M MOS transistors connected in series in the diode connection mode. N and M are natural numbers greater than or equal to 1; the comparator is connected to the output end of the voltage sampling module, compares the sampling voltage with the reference voltage and outputs a comparison result; the charge pump is connected to the output end of the comparator. When the sampling voltage is less than the reference voltage, the output voltage is raised; when the sampling voltage is greater than or equal to the reference voltage, the charge pump stops working, and the voltage sampling module enters the holding mode. The high-voltage generating circuit and the memory of the present invention use MOS transistors connected in series in the diode connection mode to achieve sampling, reducing the complexity and ensuring the stability of the final output of the charge pump without the need for refreshing; and using inverse ratio dimensions, the device size is greatly reduced, thereby reducing the area of the overall circuit; in addition, the load current of the charge pump in the standby mode is small, and the power consumption of the voltage sampling module is also very low. Therefore, the power consumption of the entire high-voltage generating circuit is reduced. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0061] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A high voltage generating circuit, characterized in that: The high voltage generating circuit at least comprises: Voltage sampling module, comparator and charge pump; The voltage sampling module samples the output voltage of the charge pump, and the voltage sampling module includes a first voltage dividing unit and a second voltage dividing unit connected in series between the output voltage and the reference ground, and the output nodes of the first voltage dividing unit and the second voltage dividing unit output the sampling voltage, wherein the first voltage dividing unit includes N MOS transistors connected in series with diodes, and the second voltage dividing unit includes M MOS transistors connected in series with diodes, and N and M are natural numbers greater than or equal to 1; The comparator is connected to the output end of the voltage sampling module, compares the sampled voltage with the reference voltage and outputs the comparison result; The charge pump is connected to the output end of the comparator, and raises the output voltage when the sampling voltage is less than the reference voltage; when the sampling voltage is greater than or equal to the reference voltage, the charge pump stops working, and the voltage sampling module enters a holding mode.

2. The high voltage generating circuit according to claim 1, characterized in that: Each MOS tube adopts an inverse ratio size.

3. The high voltage generating circuit according to claim 1 or 2, characterized in that: The sizes of the MOS tubes in the first voltage dividing unit and the second voltage dividing unit are the same.

4. The high voltage generating circuit according to claim 1, characterized in that: The MOS tubes in the first voltage dividing unit and the second voltage dividing unit are NMOS tubes, and the gate and drain of each NMOS tube are connected together.

5. The high voltage generating circuit according to claim 1, characterized in that: The MOS tubes in the first voltage dividing unit and the second voltage dividing unit are PMOS tubes, and the gate and drain of each PMOS tube are connected together.

6. The high voltage generating circuit according to claim 1, characterized in that: The voltage sampling module further includes an enabling unit, and the enabling unit is connected in series with the first voltage dividing unit and the second voltage dividing unit.

7. The high voltage generating circuit according to claim 6, characterized in that: The enabling unit comprises a PMOS tube, a source of which is connected to the output voltage, a drain of which is connected to the first voltage dividing unit, and a gate of which receives an enabling signal.

8. The high voltage generating circuit according to claim 1, characterized in that: The charge pump includes an oscillator and a boost unit; The oscillator provides a clock signal; The enable terminal of the boost unit receives the comparison result, and the control terminal receives the clock signal to generate a preset voltage.

9. The high voltage generating circuit according to claim 1, characterized in that: The average current of the high voltage generating circuit satisfies: I2=T1 / (T1+T2)*I1; Among them, I1 is the current divided by the voltage sampling module, I2 is the average current of the high voltage generating circuit, T1 is the working time of the charge pump, T2 is the holding time of the voltage sampling module, and T1<T2.

10. A memory, characterized in that: The memory at least comprises the high voltage generating circuit as claimed in any one of claims 1 to 9, and the high voltage generating circuit is used to provide a storage array in the memory with high voltages required for various operations.

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