Amplification circuit

Abstract

In an amplifier circuit, the influence of parasitic capacitance on characteristics is suppressed. An amplifier circuit includes a substrate on which a first FET having a gate to which an input signal is applied, and a second FET and a third FET connected together with the first FET between a power source and a reference potential are formed, the first FET, the second FET, and the third FET are connected by being stacked in a vertical direction, and in a cross-sectional view of the substrate along a direction of the vertical stacked connection, the first FET and the second FET are stacked in the vertical direction. The gates of the first FET, the second FET, and the third FET are arranged side by side, and the amplifier circuit is provided with: an element separation unit that separates adjacent FETs from each other; and a connection section that electrically connects the source of one of the two FETs separated by the element separation section and the drain of the other of the two FETs, the element separation section being provided between adjacent FETs from the second FET to the power supply.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit. Background Art

[0002] As an amplification element of an amplifier circuit, an FET (Field Effect Transistor, hereinafter referred to as FET) is sometimes used. It is considered that in an FET, the breakdown voltage of Si is lower than that of GaAs. Therefore, a technique is known in which a plurality of FETs are connected in a vertically stacked manner (hereinafter referred to as vertical stacked connection) to divide the power supply voltage in order to cope with a high power supply voltage (for example, Patent Document 1).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2019-87992 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] As in Patent Document 1, by dividing the power supply voltage, the breakdown voltage can be increased. In the case of vertically stacking and connecting a plurality of FETs, it is necessary to separate the FET elements from each other, and then electrically connect the adjacent elements of the separated elements. In order to electrically connect the adjacent elements of the elements, it becomes necessary to provide via holes. However, if via holes are provided between the respective elements, parasitic capacitance is generated in the portions of the respective via holes. If the number of connections in the vertical stacked connection increases, there is a problem that the parasitic capacitance caused by the via holes affects the characteristics of the amplifier circuit.

[0008] The present invention has been completed in view of the above, and an object thereof is to provide an amplifier circuit capable of suppressing the influence of parasitic capacitance on characteristics.

[0009] Technical Means for Solving the Problems

[0010] To solve the above problems and achieve the object, an amplifier circuit according to a certain aspect of the present disclosure has a substrate, on which a first FET having a gate to which an input signal is applied, a second FET, and a third FET, which are connected between a power supply and a reference potential together with the first FET, are formed. The first FET, the second FET, and the third FET are stacked and connected longitudinally. In a cross-section of the substrate along the direction of the longitudinal stacking connection, the gates of the first FET, the second FET, and the third FET are arranged. The amplifier circuit has: an element isolation portion that isolates adjacent FETs from each other; and a connection portion that electrically connects the drain of one of the two FETs isolated by the element isolation portion to the source of the other. The element isolation portion is provided between adjacent FETs from the second FET to the power supply.

[0011] Advantages of the Invention

[0012] According to the present disclosure, in an amplifier circuit, the influence of parasitic capacitance on characteristics can be suppressed. Description of the Drawings

[0013] Figure 1 It is a circuit diagram showing an amplifier circuit of a comparative example.

[0014] Figure 2 It is a diagram showing an example of a layout of an amplifier circuit of a comparative example.

[0015] Figure 3 It is a partial cross-sectional view of an amplifier circuit of a comparative example.

[0016] Figure 4 It is a circuit diagram showing an amplifier circuit of the first embodiment.

[0017] Figure 5 It is a diagram showing an example of a layout of an amplifier circuit of the first embodiment.

[0018] Figure 6 It is a partial cross-sectional view of an amplifier circuit of the first embodiment.

[0019] Figure 7 It is a circuit diagram showing an amplifier circuit of the second embodiment.

[0020] Figure 8 It is a diagram showing an example of a layout of an amplifier circuit of the second embodiment.

[0021] Figure 9 It is a partial cross-sectional view of an amplifier circuit of the second embodiment.

[0022] Description of Reference Numerals

[0023] 1 Substrate

[0024] 2 Rich trap layer

[0025] 3 Oxide film

[0026] 11 - 15 FET

[0027] 31 - 35 Resistor

[0028] 40 Element isolation part

[0029] 41 - 45 Capacitor

[0030] 50a - 50g Wiring

[0031] 51, 52, 61, 62, 69 Via hole

[0032] 100, 100a, 100b Amplifier circuit

[0033] 104D, 105D Lower part

[0034] 104U, 105U Upper part

[0035] L Choke coil

[0036] MN Matching circuit

[0037] RFin Input terminal

[0038] RFout Output terminal

[0039] RL Load

[0040] SC Parasitic capacitance

[0041] T1 - T10 Electrodes. Detailed implementation manners

[0042] Hereinafter, embodiments of the present invention will be described in detail based on the accompanying drawings. In the description of the following embodiments, the same or equivalent structural parts are marked with the same reference numerals, and the description thereof is simplified or omitted. The present invention is not limited by the embodiments. In addition, among the constituent elements of the embodiments, there are constituent elements that those skilled in the art can easily replace or substantially identical constituent elements. In addition, the structures described below can be combined appropriately. In addition, omissions, replacements, or changes in the structure can be made without departing from the gist of the invention.

[0043] Hereinafter, in order to facilitate the understanding of the embodiments, a comparative example will be described first.

[0044] (Comparative example)

[0045] Figure 1This is a circuit diagram showing the amplifier circuit of the comparative example. Figure 1 This is a diagram illustrating the case of fabricating a power amplifier (PA) using a field-effect transistor, i.e., an FET. The FET is a voltage-controlled element controlled by the voltage applied to the gate. For the FET used in an SOI (Silicon on Insulator) CMOS (Complementary Metal-Oxide-Semiconductor) PA, a miniaturization process is used to improve the performance of the FET (cutoff frequency ft, transconductance gm, etc.).

[0046] Here, consider a structure in which a plurality of FETs are connected in a vertically stacked manner between the power supply Vdd and the reference potential (hereinafter referred to as vertical stacked connection). Figure 1 This is a diagram showing an example of the vertical stacked connection of a plurality of FETs. Figure 1 This is a structure obtained by a 5-stage vertical stacked connection, i.e., a 5-stage stack, based on 5 FETs. In Figure 1 , FETs 11, 12, 13, 14, and 15 are vertically stacked and connected between the reference potential and the power supply Vdd. The reference potential is, for example, the ground potential. In Figure 1 In the vertical stacked connection shown, for the continuously connected FETs, the adjacent drain and source are connected.

[0047] Resistors 31, 32, 33, 34, and 35 are connected to the respective gates of FETs 11, 12, 13, 14, and 15. In addition, capacitors 42, 43, 44, and 45 are provided between the respective gates of FETs 12, 13, 14, and 15 and the reference potential. The gate of FET 11 is connected to the input terminal RFin via capacitor 41. Capacitor 41 is provided to block the DC component of the signal to the input terminal RFin. An inductance coil L is connected between FET 15 and the power supply Vdd. An output terminal RFout is connected between FET 15 and the inductance coil L via a matching circuit MN. A load RL is connected to the output terminal RFout.

[0048] Here, the voltage between the source and drain of FET11 is set as voltage Vds1, the voltage between the source and drain of FET12 is set as voltage Vds2, the voltage between the source and drain of FET13 is set as voltage Vds3, the voltage between the source and drain of FET14 is set as voltage Vds4, and the voltage between the source and drain of FET15 is set as voltage Vds5. In order not to damage each of FETs 11, 12, 13, 14, and 15, at the maximum value of power supply Vdd, each of the voltages Vds1, Vds2, Vds3, Vds4, and Vds5 needs to be a voltage value below the breakdown voltage. Therefore, it is necessary to control the voltage values of the biases vg1, vg2, vg3, vg4, and vg5 supplied to each gate so that the voltage between each source and drain does not exceed the breakdown voltage.

[0049] Power supply Vdd is a variable power supply, and its voltage value changes rather than being a fixed value. On the power supply Vdd side of FET15, which is the closest to the power supply Vdd among FETs 11 to 15 connected in vertical stack, a choke coil L is connected between the power supply Vdd. An output terminal RFout is connected between the choke coil L and FET15 via a matching circuit MN. A load RL is connected to the output terminal RFout. Biases vg1, vg2, vg3, vg4, and vg5 are supplied to the gates of FETs 11, 12, 13, 14, and 15 via resistors 31, 32, 33, 34, and 35.

[0050] Figure 2 is a diagram showing Figure 1 an example of the layout of the amplifier circuit 100 of the comparative example shown. Figure 2 is Figure 1 a top view of the amplifier circuit 100 of the comparative example shown. Figure 3 is Figure 2 a partial cross-sectional view of the amplifier circuit 100 of the comparative example shown. Figure 3 shows a cross-section along Figure 2 section A-A in

[0051] Referring to Figure 2 , the amplifier circuit 100 of this example has blocks Tr1, Tr2, Tr3, and Tr4 of four transistors. Each block of transistors is vertically stacked and connected in five levels as described with reference to Figure 1 . That is, the amplifier circuit 100 of this example includes blocks Tr1, Tr2, Tr3, and Tr4 of transistors that are vertically stacked and connected in five levels.

[0052] Here, focusing on the block Tr1 of transistors. The block Tr1 has source S1, gate G1, drain D1, source S2, gate G2, drain D2, source S3, gate G3, drain D3, source S4, gate G4, drain D4, source S5, gate G5, and drain D5 inFigure 2 structures arranged in the Y direction. These parts arranged in the Y direction extend in the X direction. Similarly, for the transistor blocks Tr2, Tr3, and Tr4, in Figure 2 the parts arranged in the Y direction extend in the X direction. Figure 2 the Z direction orthogonal to the X direction and the Y direction corresponds to the thickness direction of the substrate of the amplifier circuit 100.

[0053] As Figure 2 shown, the drain D1 and the source S2 of two adjacent FETs among the arranged parts are common terminals, and are marked as "D1 / S2" in Figure 2 . That is, the drain D1 and the source S2 are not separate terminals but the same terminal. Similarly, the drain D2 and the source S3 of two adjacent FETs are common terminals, and are marked as "D2 / S3" in Figure 2 . Similarly, the drain D3 and the source S4 of two adjacent FETs are common terminals, and are marked as "D3 / S4" in Figure 2 . Similarly, the drain D4 and the source S5 of two adjacent FETs are common terminals, and are marked as "D4 / S5" in Figure 2 . For Figure 2 the other blocks Tr2, Tr3, and Tr4 in, similarly to the block Tr1, the parts are arranged in the Y direction, and the parts arranged in the Y direction extend in the X direction. In this example, the source S1 of the block Tr1 and the source S1 of the Tr2 are common. The source S1 of the block Tr3 and the source S1 of the Tr4 are common.

[0054] At the source S1 of the blocks Tr1 and Tr2, the connection electrodes T1 and T4 are connected. At the drain D5 of the block Tr1, the connection electrode T2 is connected. At the drain D5 of the block Tr2, the connection electrode T3 is connected. At the source S1 of the blocks Tr3 and Tr4, the connection electrode T5 is connected. At the drain D5 of the block Tr3, the connection electrodes T7 and T8 are connected. At the drain D5 of the block Tr4, the connection electrodes T6 and T9 are connected.

[0055] One end of the wiring 50a is connected to the electrode T1. One end of the wiring 50b is connected to the electrode T2. The other end of the wiring 50b is connected to the electrode T6. One end of the wiring 50e is connected to the electrode T4. The other end of the wiring 50e is connected to the electrode T5. One end of the wiring 50g is connected to the electrode T3. The other end of the wiring 50g is connected to the electrode T7. One end of the wiring 50f is connected to the electrode T8. One end of the wiring 50c is connected to the electrode T9.

[0056] Refer to Figure 3, the amplifier circuit 100 includes a substrate 1 formed of p-type silicon, a trap-rich layer 2 formed on the substrate 1, and an oxide film 3 formed on the trap-rich layer 2. On the oxide film 3, FETs 11, 12, 13, 14, and 15 are formed. Additionally, Figure 3 The upward direction of Figure 2 corresponds to the Z direction in

[0057] In Figure 3 , the FETs 11, 12, 13, 14, and 15 are arranged in the direction of the center line indicated by the chain line along the A-A section in Figure 2 . In Figure 3 , the source of the FET 11 is labeled as "S1", the gate is labeled as "G1", and the drain is labeled as "D1". The source of the FET 12 is labeled as "S2", the gate is labeled as "G2", and the drain is labeled as "D2". The source of the FET 13 is labeled as "S3", the gate is labeled as "G3", and the drain is labeled as "D3". The source of the FET 14 is labeled as "S4", the gate is labeled as "G4", and the drain is labeled as "D4". The source of the FET 15 is labeled as "S5", the gate is labeled as "G5", and the drain is labeled as "D5".

[0058] At the source S1 of the FET 11, a via 61 is connected. An electrode T1 is provided above the via 61. At the drain D5 of the FET 15, a via 62 is connected. An electrode T2 is provided above the via 62. In Figure 3 the amplifier circuit 100 shown, between each stage of the FETs 11, 12, 13, 14, and 15, no element isolation section described later is provided.

[0059] Returning to Figure 1 , the amplifier circuit 100 performs an amplification operation in sequence from the lowest-stage FET 11 to the highest-stage FET 15 among the five stages connected in vertical stack. That is, the amplifier circuit 100 sequentially performs an amplification operation of taking the amplified output of the previous stage as an input and amplifying it to output to the next stage.

[0060] Here, parasitic capacitances generated at the terminals of the FETs at each stage sometimes affect the operation of the FETs at the subsequent stage. For example, the parasitic capacitance SC caused by the common terminal of the gate of the first-stage FET11, the drain of the first-stage FET11, and the source of the second-stage FET12 sometimes affects the phase of the amplified output of the FETs after the second stage. If the phase changes due to the parasitic capacitance, the modulation accuracy deteriorates. To reduce the influence of the parasitic capacitance, component separation is considered for each stage of adjacent FETs. However, if component separation is performed for each stage, vias and wirings for electrically connecting the separated components need to be provided, and the influence of the parasitic capacitance caused by them on the characteristics of the amplifier circuit becomes a problem.

[0061] (First Embodiment)

[0062] (Circuit Structure)

[0063] Figure 4 is a circuit diagram showing the amplifier circuit 100a of the first embodiment. Refer to Figure 4 , the amplifier circuit 100a has the same structure as the amplifier circuit 100 of the comparative example, which is a structure obtained by vertically stacking FETs in five stages, that is, five-stage stacking. The amplifier circuit 100a includes a stacked lower-stage portion 105D and a stacked upper-stage portion 105U. The lower-stage portion 105D includes the first-stage FET11 and the second-stage FET12. The upper-stage portion 105U includes the third-stage FET13, the fourth-stage FET14, and the fifth-stage FET15. An element separation portion described later is provided between the lower-stage portion 105D and the upper-stage portion 105U, that is, between the second-stage FET12 and the third-stage FET13.

[0064] Here, a capacitor 42 is connected between the gate of the FET12 and the reference potential. A capacitor 43 is connected between the gate of the FET13 and the reference potential. The capacitance value of the capacitor 42 is preferably larger than that of the capacitor 43. The capacitor 42 corresponds to the first capacitor of the present disclosure. The capacitor 43 corresponds to the second capacitor of the present disclosure. In addition, the on-resistance of the upper-stage portion 105U and the on-resistance of the lower-stage portion 105D are different, and the on-resistance of the upper-stage portion 105U is smaller than that of the lower-stage portion 105D. That is, the on-resistance of the third-stage FET13 is smaller than that of the second-stage FET12.

[0065] (Layout)

[0066] Figure 5 is a diagram showing Figure 4 an example of the layout of the amplifier circuit 100a of the first embodiment shown. Figure 5 is Figure 4 a top view of the amplifier circuit 100a of the first embodiment shown. Figure 6 is Figure 5Partial cross-sectional view of the amplifier circuit 100a of the first embodiment shown. Figure 6 Shows a cross-section along Figure 5 section B-B in

[0067] In Figure 5 it is the same as the case of Figure 2 and the amplifier circuit 100a has blocks of four transistors Tr1, Tr2, Tr3, and Tr4. Each block of transistors is vertically stacked and connected in five levels as described with reference to Figure 4 That is, the amplifier circuit 100a of the present embodiment includes blocks of transistors Tr1, Tr2, Tr3, and Tr4 that are vertically stacked and connected in five levels.

[0068] In Figure 5 we focus on the block of transistors Tr1. It is the same as the case of Figure 2 and the block Tr1 has a structure in which source S1, gate G1, drain D1, source S2, gate G2, and drain D2 are arranged in the Y direction in Figure 5 and source S3, gate G3, drain D3, source S4, gate G4, drain D4, source S5, gate G5, and drain D5 are arranged in the Y direction in Figure 5 . In Figure 5 it is different from the case of Figure 2 and drain D2 and source S3 are separate terminals. The same applies to the blocks of transistors Tr2, Tr3, and Tr4, where drain D2 and source S3 are separate terminals.

[0069] In Figure 5 at the source S1 of blocks Tr1 and Tr2, connection electrode T1 is connected. At the drain D2 of block Tr1, connection electrode T2 is connected. At the source S3 of block Tr1, connection electrode T6 is connected. At the drain D5 of blocks Tr1 and Tr2, connection electrode T9 is connected. At the drain D2 of blocks Tr2 and Tr3, connection electrode T4 is connected. At the source S3 of blocks Tr2 and Tr3, connection electrode T7 is connected. At the source S1 of blocks Tr3 and Tr4, connection electrode T3 is connected. At the drain D5 of blocks Tr3 and Tr4, connection electrode T10 is connected. At the drain D2 of block Tr4, connection electrode T5 is connected. At the source S3 of block Tr4, connection electrode T8 is connected.

[0070] In Figure 5In the figure, one end of the connection wiring 50a is connected to the electrode T1. One end of the connection wiring 50b is connected to the electrode T2. The other end of the connection wiring 50b is connected to the electrode T6. One end of the connection wiring 50e is connected to the electrode T4. The other end of the connection wiring 50e is connected to the electrode T7. One end of the connection wiring 50d is connected to the electrode T3. One end of the connection wiring 50g is connected to the electrode T5. The other end of the connection wiring 50g is connected to the electrode T8. One end of the connection wiring 50c is connected to the electrode T9. One end of the connection wiring 50f is connected to the electrode T10.

[0071] Here, referring to Figure 6 , different from the case of Figure 3 , the drain D2 and the source S3 become separate terminals. An element isolation portion 40 is provided between the drain D2 and the source S3. The element isolation portion 40 is, for example, STI (Shallow Trench Isolation). By providing the element isolation portion 40, leakage current between adjacent elements, namely FET12 and FET13, can be prevented, and breakdown voltage can be ensured.

[0072] For the FET12 and FET13 separated by the element isolation portion 40, a via 51 is connected to the drain D2 of the FET12, and a via 52 is connected to the source S3 of the FET13. Moreover, the vias 51 and 52 are connected to the wiring 50b. The vias 51 and 52 are electrically connected through the wiring 50b. That is, the wiring 50b electrically connects the drain D2 of one of the two FETs separated by the element isolation portion 40 and the source S3 of the other. The wiring 50b corresponds to the connection portion of the present disclosure.

[0073] In addition, a via 61 is connected to the source S1 of the FET11. The electrode T1 is provided above the via 61. A via 69 is connected to the drain D5 of the FET15. The electrode T9 is provided above the via 69.

[0074] (Effect)

[0075] As described above, if element isolation is performed for each stage, vias and wirings for electrically connecting the separated elements need to be provided, and the influence of the parasitic capacitance caused by them on the characteristics of the amplifier circuit becomes a problem. Therefore, in the first embodiment, the element isolation portion 40 is provided only between the FET12 of the second stage and the FET13 of the third stage. Thus, compared with the case where the element isolation portion is provided between all stages, the parasitic capacitance can be reduced, and the influence of the parasitic capacitance on the characteristics of the amplifier circuit can be reduced.

[0076] Here, if it is assumed that an element isolation portion is provided between the drain of the FET11 of the first stage and the source of the FET12 of the second stage, a parasitic capacitance SC is generated (refer to Figure 4), and the influence on the characteristics of the amplifier circuit becomes a problem. In the first embodiment, since the element separation portion 40 is provided only between the FET 12 of the second stage and the FET 13 of the third stage, the parasitic capacitance SC shown by the dashed line in Figure 4 is not generated, and the parasitic capacitance can be reduced. In addition, the element separation portion may be provided between adjacent FETs other than between the drain of the FET 11 of the first stage and the source of the FET 12 of the second stage. That is, the element separation portion is provided between adjacent FETs from the FET of the second stage to the power supply Vdd.

[0077] (Second Embodiment)

[0078] (Circuit Structure)

[0079] Figure 7 is a circuit diagram showing the amplifier circuit 100b of the second embodiment. Referring to Figure 7 , the amplifier circuit 100b is different from the amplifier circuit 100 of the comparative example and the amplifier circuit 100a of the first embodiment, and is a structure obtained by vertically stacking FETs in four stages, that is, four-stage stacking. The amplifier circuit 100b includes a stacked lower-stage portion 104D and a stacked upper-stage portion 104U. The lower-stage portion 104D includes the FET 11 of the first stage and the FET 12 of the second stage. The upper-stage portion 104U includes the FET 13 of the third stage and the FET 14 of the fourth stage. An element separation portion described later is provided between the lower-stage portion 104D and the upper-stage portion 104U, that is, between the FET 12 of the second stage and the FET 13 of the third stage. In addition, the on-resistance of the upper-stage portion 104U and the on-resistance of the lower-stage portion 104D are different, and the on-resistance of the upper-stage portion 104U is smaller than that of the lower-stage portion 104D.

[0080] (Layout)

[0081] Figure 8 is a diagram showing an example of the layout of the amplifier circuit 100b of the second embodiment shown in Figure 7 . Figure 8 is Figure 7 a top view of the amplifier circuit 100b of the second embodiment shown. Figure 9 is Figure 8 a partial cross-sectional view of the amplifier circuit 100b of the second embodiment shown. Figure 9 shows a cross-section along the C-C portion in Figure 8 .

[0082] In Figure 8 , the amplifier circuit 100b has blocks Tr11, Tr12, Tr13, and Tr14 of four transistors. Each transistor block is as shown in reference to Figure 7As described above, a four - stage vertical stacked connection is made. That is, the amplifier circuit 100b of the present embodiment includes blocks Tr11, Tr12, Tr13, and Tr14 of transistors that are vertically stacked and connected in four stages.

[0083] In Figure 8 , attention is focused on the block Tr11 of transistors. In the block Tr11, the source S1, gate G1, drain D1, source S2, gate G2, and drain D2 are arranged in the Y - direction in Figure 8 , and the source S3, gate G3, drain D3, source S4, gate G4, and drain D4 are arranged in the Y - direction in Figure 8 . In Figure 8 , different from the case of Figure 2 , the drain D2 and the source S3 become separate terminals.

[0084] In Figure 8 , an electrode T1 is connected to the source S1 of the blocks Tr11 and Tr12. An electrode T2 is connected to the drain D2 of the block Tr11. An electrode T6 is connected to the source S3 of the block Tr11. An electrode T9 is connected to the drain D4 of the blocks Tr11 and Tr12. An electrode T3 is connected to the source S1 of the blocks Tr13 and Tr14. An electrode T5 is connected to the drain D2 of the block Tr14. An electrode T8 is connected to the source S3 of the block Tr14. An electrode T10 is connected to the drain D4 of the blocks Tr13 and Tr14.

[0085] In Figure 8 , one end of the wiring 50a is connected to the electrode T1. One end of the wiring 50b is connected to the electrode T2. The other end of the wiring 50b is connected to the electrode T6. One end of the wiring 50e is connected to the electrode T4. The other end of the wiring 50e is connected to the electrode T7. One end of the wiring 50d is connected to the electrode T3. One end of the wiring 50g is connected to the electrode T5. The other end of the wiring 50g is connected to the electrode T8. One end of the wiring 50c is connected to the electrode T9. One end of the wiring 50f is connected to the electrode T10.

[0086] Here, referring to Figure 9 , similar to the case of Figure 6 , the drain D2 and the source S3 become separate terminals. An element isolation portion 40 is provided between the drain D2 and the source S3. The element isolation portion 40 is, for example, STI. By providing the element isolation portion 40, leakage current between adjacent elements, that is, between FET12 and FET13, can be prevented, and breakdown voltage can be ensured.

[0087] For the FET12 and FET13 separated by the element isolation portion 40, similar to Figure 6Similarly, via 51 is connected to the drain D2 of FET12, and via 52 is connected to the source S3 of FET13. Further, vias 51 and 52 are connected to wiring 50b. Vias 51 and 52 are electrically connected via wiring 50b. Wiring 50b corresponds to the connection portion of the present disclosure.

[0088] (Effect)

[0089] As described above, when separating elements for each stage, it is necessary to provide vias and wirings for electrically connecting the separated elements, and the influence of the parasitic capacitance caused by them on the characteristics of the amplifier circuit becomes a problem. Therefore, in the second embodiment, the element separation portion 40 is provided only between the second-stage FET12 and the third-stage FET13. Thus, compared with the case where the element separation portion is provided between all stages, the parasitic capacitance can be reduced, and the influence of the parasitic capacitance on the characteristics of the amplifier circuit can be reduced.

[0090] Here, if it is assumed that an element separation portion is provided between the drain of the first-stage FET11 and the source of the second-stage FET12, a parasitic capacitance SC (see Figure 7 ) is generated, and the influence on the characteristics of the amplifier circuit becomes a problem. In the second embodiment, since the element separation portion 40 is provided only between the second-stage FET12 and the third-stage FET13, the parasitic capacitance SC shown by the dotted line in Figure 7 is not generated, and the parasitic capacitance can be reduced. In addition, the element separation portion may be provided between adjacent FETs other than between the drain of the first-stage FET11 and the source of the second-stage FET12. That is, the element separation portion is provided between adjacent FETs from the second-stage FET to the power supply Vdd.

[0091] Regarding the description of the claims, the present disclosure can take the following forms.

[0092] <1>

[0093] An amplifier circuit,

[0094] having a substrate on which a first FET having a gate to which an input signal is applied, a second FET, and a third FET connected together between a power supply and a reference potential are formed,

[0095] wherein the first FET, the second FET, and the third FET are longitudinally stacked and connected,

[0096] in a cross-section of the substrate along the direction of the longitudinal stacking connection, the gates of the first FET, the second FET, and the third FET are arranged and configured,

[0097] The amplifier circuit has: a component separation section that separates adjacent FETs from each other; and a connection section that electrically connects the source of one of the two FETs separated by the component separation section to the drain of the other.

[0098] The component separation section is provided between the second FET and the power supply.

[0099] <2>

[0100] The amplifier circuit according to <1>, wherein

[0101] The drain of one of the two adjacent FETs and the source of the other become a common terminal.

[0102] <3>

[0103] The amplifier circuit according to <1> or <2>, wherein

[0104] The component separation section is provided between the second FET and the third FET to separate the second FET and the third FET.

[0105] <4>

[0106] The amplifier circuit according to any one of <1> to <3>, wherein

[0107] The amplifier circuit further has:

[0108] A first capacitor connected between the gate of the second FET and the reference potential; and

[0109] A second capacitor connected between the gate of the third FET and the reference potential,

[0110] The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

[0111] <5>

[0112] The amplifier circuit according to any one of <1> to <4>, wherein

[0113] The on-resistance of the third FET is less than the on-resistance of the second FET.

Claims

1. An amplifier circuit, A substrate is provided on which a first FET having a gate to which an input signal is applied, and a second FET and a third FET connected between a power supply and a reference potential together with the first FET are formed. The first FET, the second FET, and the third FET are stacked and connected vertically, In a cross-sectional view of the substrate along the longitudinal stacking connection direction, the gates of the first FET, the second FET, and the third FET are arranged in an arrangement, The amplifier circuit includes: an element separation portion that separates adjacent FETs from each other; and a connection portion that electrically connects a drain of one of the two FETs separated by the element separation portion and a source of the other. The element separation section is provided between adjacent FETs from the second FET to the power source.

2. The amplifier circuit according to claim 1, wherein: The drain of one of two adjacent FETs and the source of the other serve as a common terminal.

3. The amplifier circuit according to claim 1 or claim 2, wherein: The element separation unit is provided between the second FET and the third FET, and separates the second FET from the third FET.

4. The amplifier circuit according to any one of claims 1 to 3, wherein: The amplifier circuit also has: a first capacitor connected between the gate of the second FET and the reference potential; and a second capacitor connected between the gate of the third FET and the reference potential; The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

5. The amplifier circuit according to any one of claims 1 to 4, wherein: The on-resistance of the third FET is smaller than the on-resistance of the second FET.

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