Digital delay chain switching method and digital delay chain

Abstract

The invention relates to the technical field of integrated circuits and provides a digital delay chain switching method and a digital delay chain. The switching method includes: in response to switching from a first code value to a second code value, determining an expected level on an output node of each of the plurality of inverters based on the first code value and a level of an input signal; then, through the respective sub-circuits of the plurality of inverters, the levels on the respective output nodes of the plurality of inverters are controllable levels controlled by the respective associated sub-circuits of the plurality of inverters, and the levels on the respective output nodes of the plurality of inverters are controlled by the respective associated sub-circuits of the plurality of inverters. Such that the controllable level controlled by the sub-circuit associated with each of the plurality of inverters is the determined expected level on the output node of each of the plurality of inverters. Thus, the time required for switching the control logic of the digital delay chain is shortened, the use efficiency of the digital delay chain is improved, the calibration efficiency is improved, and the time sequence adjustment requirement under the higher interface rate is met.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technologies, and particularly to a switching method for a digital delay line and a digital delay line. Background Art

[0002] In application fields such as high-speed interfaces and high-speed digital signal processing, a digital delay line (DDL) is often used to adjust the phases of clock signals and data signals so as to meet various timing requirements. With the improvement of data transmission rates and interface rates, a digital delay line is required to provide high-precision and wide-range timing adjustment functions. The basic principle of a digital delay line is to provide delay through inverters and to achieve different degrees of delay by controlling the number of turned-on inverters. However, affected by factors such as process conditions, power supply voltage, and temperature, the delays of each inverter may vary, and moreover, the states of the inverters in the digital delay line may also be unstable. Therefore, when calibrating or switching the control logic of the digital delay line, it is necessary to consider the output signal glitches caused by factors such as the unstable states of the inverters and signal deviations. In the prior art, in order to avoid the glitches in the output signal from disturbing the timing, when switching the control logic, the input signal is made to bypass the digital delay line and instead pass through another stable path, thereby shielding the glitches in the output signal that may be generated due to the switching logic. However, the switching scheme and calibration scheme of the digital delay line in the prior art may require multiple calibrations for one unit interval (UI), and each time of switching, it is necessary to shield the influence of the glitches through the stable path, which is not conducive to improving the overall efficiency and meeting the timing adjustment requirements at higher interface rates. Therefore, the present application provides a switching method for a digital delay line and a digital delay line to address the technical problems in the prior art. Summary of the Invention

[0003] In a first aspect, the present application provides a method for switching a digital delay chain. The digital delay chain includes a plurality of inverters and sub-circuits respectively associated with the plurality of inverters. The sub-circuits are configured to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit or a level determined by the inverter associated with the sub-circuit. The switching method includes: in response to the control code of the digital delay chain switching from a first code value to a second code value, determining the expected levels on the output nodes of the plurality of inverters based on the first code value and the level of the input signal; then, through the sub-circuits of the plurality of inverters respectively, making the levels on the output nodes of the plurality of inverters be controllable levels controlled by the sub-circuits respectively associated with the plurality of inverters, and making the controllable levels controlled by the sub-circuits respectively associated with the plurality of inverters be the determined expected levels on the output nodes of the plurality of inverters.

[0004] Through the first aspect of the present application, when switching the control code, regardless of whether the inverters or delay units in the digital delay chain are turned on or off, it can ensure that the signal states on each node in the digital delay chain are in a determined state, thereby avoiding the generation of glitch phenomena. That is, by pulling the uncertain state to a determined level before switching the control code according to the state of the input signal, the generation of glitch phenomena is avoided. In this way, the time required for switching the control logic of the digital delay chain is shortened, which helps to improve the usage efficiency of the digital delay chain, is beneficial to improving the calibration efficiency, and meets the timing adjustment requirements at higher interface rates.

[0005] In a possible implementation manner of the first aspect of the present application, the control code of the digital delay chain is used to control each of the plurality of inverters in an on state or an off state. The inverters in the on state among the plurality of inverters together form a delay path in the digital delay chain, and the input signal of the digital delay chain passes through the delay path and then serves as the output signal of the digital delay chain.

[0006] In a possible implementation manner of the first aspect of the present application, the sub-circuits respectively associated with the plurality of inverters are configured to make the levels on the output nodes of the plurality of inverters be determined by the plurality of inverters respectively when the control code of the digital delay chain is not switched.

[0007] In a possible implementation manner of the first aspect of the present application, determining the expected levels on the output nodes of the plurality of inverters based on the first code value and the level of the input signal includes: determining the inverters in the off state among the plurality of inverters based on the first code value, and then determining the expected levels on the output nodes of the inverters in the off state among the plurality of inverters based on the level of the input signal.

[0008] In a possible implementation of the first aspect of the present application, determining the expected level on the output node of each of the plurality of inverters based on the first code value and the level of the input signal includes: determining the inverters in the on state among the plurality of inverters based on the first code value, and then determining the expected level on the output node of each of the inverters in the on state among the plurality of inverters based on the level of the input signal.

[0009] In a possible implementation of the first aspect of the present application, the switching method further includes: after the control code of the digital delay chain is switched from the first code value to the second code value, making the level on the output node of each of the plurality of inverters be determined by each of the plurality of inverters through the respective sub-circuits of the plurality of inverters.

[0010] In a possible implementation of the first aspect of the present application, the sub-circuit associated with each of the plurality of inverters is a tri-state gate circuit, and the tri-state gate circuit switches between a high-impedance state, a high-level output state, and a low-level output state. When the tri-state gate circuit is in the high-impedance state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be determined by the inverter associated with the sub-circuit.

[0011] In a possible implementation of the first aspect of the present application, when the tri-state gate circuit is in the high-level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a high level.

[0012] In a possible implementation of the first aspect of the present application, when the tri-state gate circuit is in the low-level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a low level.

[0013] In a possible implementation of the first aspect of the present application, the switching method is used for the calibration mode or the normal mode of the digital delay chain.

[0014] Second aspect, the embodiments of the present application further provide a digital delay chain. The digital delay chain includes a plurality of inverters and sub-circuits respectively associated with the plurality of inverters. The sub-circuits are configured to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit or a level determined by the inverter associated with the sub-circuit. The process of switching the control code of the digital delay chain from the first code value to the second code value includes: determining the expected levels on the output nodes of the plurality of inverters based on the first code value and the level of the input signal; then, through the sub-circuits of the plurality of inverters respectively, making the levels on the output nodes of the plurality of inverters respectively be controllable levels controlled by the sub-circuits respectively associated with the plurality of inverters, and making the controllable levels controlled by the sub-circuits respectively associated with the plurality of inverters be the determined expected levels on the output nodes of the plurality of inverters.

[0015] Through the second aspect of the present application, when switching the control code, regardless of whether the inverters or the delay units in the digital delay chain are turned on or off, it can be ensured that the signal states on each node in the digital delay chain are in a determined state, thus avoiding the generation of glitch phenomena. That is, by pulling the uncertain state to a determined level before switching the control code according to the state of the input signal, the generation of glitch phenomena is avoided. In this way, the time required to switch the control logic of the digital delay chain is shortened, which helps to improve the usage efficiency of the digital delay chain, is beneficial to improving the calibration efficiency and meeting the timing adjustment requirements at higher interface rates.

[0016] In a possible implementation manner of the second aspect of the present application, the control code of the digital delay chain is used to control each of the plurality of inverters to be in an on state or an off state. The inverters in the on state among the plurality of inverters together form a delay path in the digital delay chain. The input signal of the digital delay chain passes through the delay path and then serves as the output signal of the digital delay chain.

[0017] In a possible implementation manner of the second aspect of the present application, the sub-circuits respectively associated with the plurality of inverters are configured to make the levels on the output nodes of the plurality of inverters respectively be determined by the plurality of inverters themselves when the control code of the digital delay chain is not switched.

[0018] In a possible implementation manner of the second aspect of the present application, after the control code of the digital delay chain is switched from the first code value to the second code value, through the sub-circuits of the plurality of inverters respectively, making the levels on the output nodes of the plurality of inverters respectively be determined by the plurality of inverters themselves.

[0019] In a possible implementation of the second aspect of the present application, the sub-circuits associated with the multiple inverters are tri-state gate circuits, and the tri-state gate circuits switch between a high-impedance state, a high-level output state, and a low-level output state. When the tri-state gate circuit is in the high-impedance state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be determined by the inverter associated with the sub-circuit.

[0020] In a possible implementation of the second aspect of the present application, when the tri-state gate circuit is in the high-level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a high level.

[0021] In a possible implementation of the second aspect of the present application, when the tri-state gate circuit is in the low-level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a low level. Description of the Drawings

[0022] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 It is a schematic flowchart of a switching method for a digital delay chain provided by an embodiment of the present application; Figure 2 It is a schematic diagram of the internal node states of the digital delay chain in the first implementation manner provided by an embodiment of the present application; Figure 3 It is a schematic diagram of the internal node states of the digital delay chain in the second implementation manner provided by an embodiment of the present application; Figure 4 It is a schematic diagram of a delay unit sub-module including an inverter and an associated sub-circuit in a digital delay chain provided by an embodiment of the present application. Detailed Embodiments

[0024] The following will further describe the embodiments of the present application in detail with reference to the drawings.

[0025] It should be understood that in the description of the present application, "at least one" means one or more, and "a plurality" means two or more. In addition, words such as "first" and "second" are only used for the purpose of distinguishing descriptions unless otherwise specified, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0026] Figure 1 It is a schematic flowchart of a switching method for a digital delay chain provided by an embodiment of the present application. The digital delay chain includes a plurality of inverters and sub-circuits respectively associated with the plurality of inverters. The sub-circuits are used to make the level on the output node of the inverter associated with the sub-circuit be a controllable level controlled by the sub-circuit or be determined by the inverter associated with the sub-circuit. As Figure 1 shown, the switching method includes the following steps.

[0027] Step S101: In response to the control code of the digital delay chain switching from a first code value to a second code value, determine the expected levels on the output nodes of the plurality of inverters based on the first code value and the level of the input signal.

[0028] Step S103: Then, through the sub-circuits of the plurality of inverters respectively, make the levels on the output nodes of the plurality of inverters be controllable levels controlled by the sub-circuits respectively associated with the plurality of inverters, and make the controllable levels controlled by the sub-circuits respectively associated with the plurality of inverters be the expected levels on the output nodes of the determined plurality of inverters.

[0029] Figure 1The switching method shown can be used to solve the technical problems existing in the switching scheme and calibration scheme of the Digital Delay Line (DDL) in the prior art. In the switching scheme and calibration scheme of the prior art, multiple calibrations are performed for one Unit Interval (UI). Each time of switching, the influence of the glitch phenomenon needs to be shielded through the stable path, which is not conducive to improving the overall efficiency and meeting the timing adjustment requirements under higher interface rates. Here, when switching the digital delay line, it is necessary to maintain a bypass mode for a period of time, that is, during the duration of the bypass mode, the signal output by the digital delay line is skipped, and instead, the signal of the stable path is switched to. This is because the digital delay line includes multiple inverters, and through the control logic, the opening and closing of these inverters can be controlled, so that the signal input to the digital delay line is output after passing through the delay path composed of the opened inverters, and thus has a controllable delay. The specific degree of the delay is determined by the number of opened and closed inverters determined by the control logic, that is, the specific composition of the delay path is determined by the control logic. However, as a delay unit, the inverter is affected by PVT factors, namely process, power supply voltage, and temperature. Devices such as logic gates in it may have different delay performances, such as rising period and falling period, etc., resulting in that a single inverter may be within a certain delay variation range. Therefore, it is necessary to use a calibration circuit to judge how many codes are required to use the digital delay line to provide a delay of one unit interval, that is, a single clock cycle, by changing the number of inverter switches, that is, switching the control logic, that is, the control code (code). In other words, 1 unit interval UI corresponds to a single clock cycle, which is determined by the application scenario. For example, 1 UI can correspond to 20 milliseconds or 100 milliseconds. Through the calibration circuit, it can be judged how many inverters need to be opened at least, that is, the minimum value of the control code, to provide a delay equal to 1 UI through the DDL. For example, opening 3 inverters can provide a delay of 20 milliseconds, and opening 10 inverters can provide a delay of 100 milliseconds. When using the calibration circuit for calibration, that is, in the calibration mode, because it is necessary to switch the control logic, for example, gradually increase the control code from small to large, that is, gradually increase the number of opened inverters one by one, this means that the state of the inverters in the digital delay line may be unstable at this time. Switching the control code may cause glitches in the output signal, which is caused by the inversion of the output of the inverter. In addition, in addition to the need to frequently switch the control logic in the calibration mode, in some application scenarios, it is necessary to output multiple different delays through the digital delay line, such as link congestion testing, clock signal alignment, etc. Therefore, similar to the need to gradually increase the control code from small to large in the calibration mode, in this case, it is also necessary to gradually increase the number of opened inverters one by one, which also involves frequently switching the control logic in a short time.In the solutions of the prior art, in the face of the need to frequently switch control logic in the calibration mode or certain application scenarios, the signal output by the digital delay chain is skipped by maintaining the high level of the skip mode, that is, the signal switched to the stable path. Therefore, by shortening the duration of the calibration mode, that is, shortening the duration of the high level of the skip mode, it is beneficial to improve the overall calibration efficiency. Each time the control logic of the digital delay chain is changed, from the issuance of a new control signal to the entire digital delay chain completing the switch and entering the stable state, the time taken for this process is the duration for which the skip mode high level needs to be maintained, and it is also the time taken for a single switch in the calibration mode. Here, the entire time for the digital delay chain to complete a single switch consists of three parts. The first part is the time required for the control signal to reach each sub-module inside the digital delay chain. The second part is the time for each sub-module inside the digital delay chain to decode the control signal and send it to each inverter after receiving the control signal. The third part is the time for the delay chain to generate glitch propagation when switching the control logic, that is, the control code. The time of the third part is usually close to one clock cycle and accounts for the largest proportion in the entire time.

[0030] Refer to Figure 1 , as mentioned above, the entire time for the digital delay chain to complete a single switch consists of three parts. Among them, the first part and the second part are affected by line delay, that is, the delay caused by electronic components on the signal transmission path, such as capacitors and inductors. The first part and the second part are relatively fixed delays. The largest proportion in the entire time for the digital delay chain to complete a single switch is the third part of the time, that is, the time for the delay chain to generate glitch propagation when switching the control logic, that is, the control code. The reason behind the glitch phenomenon is that when switching the control logic, it is difficult to determine whether each inverter in the digital delay chain is open or closed. Therefore, the signal states of each node in the digital delay chain are in an uncertain state. In other words, before switching the control logic, that is, the control code, that is, before the new control signal is decoded and sent to each inverter, the states of each inverter are uncertain, that is, it is uncertain whether it is open or closed; and even after receiving the new control signal, whether each inverter performs a state switch and the time taken for the state switch may also be inconsistent. Therefore, the internal nodes of the digital delay chain may flip, which causes the signal output by the digital delay chain to have glitches, that is, abnormal signal fluctuations. In order to overcome the influence caused by the glitch phenomenon, Figure 1 The switching method shown in

[0031] Continue to refer to Figure 1 The digital delay chain includes a plurality of inverters and sub - circuits associated with each of the plurality of inverters. The sub - circuits are configured to make the level on the output node of the inverter associated with the sub - circuit a controllable level controlled by the sub - circuit or a level determined by the inverter associated with the sub - circuit. Here, the sub - circuit associated with each inverter switches between two modes. In the first mode, the sub - circuit is configured to make the level on the output node of the inverter associated with the sub - circuit a controllable level controlled by the sub - circuit, which means that in the first mode, the level on the output node of the inverter is a controllable level controlled by the sub - circuit and is independent of the output of the inverter itself, that is, it is not determined by the output of the inverter itself. In the second mode, the sub - circuit is configured to make the level on the output node of the inverter associated with the sub - circuit a level determined by the inverter associated with the sub - circuit, which means that in the second mode, the level on the output node of the inverter is determined by the output of the inverter itself. For example, the inverter may be turned off, that is, not in the delay path, or the inverter may be turned on, that is, the logical information on the input node of the inverter is inverted and then output. Based on the optimized design of the circuit structure of the sub - circuit, the optimized switching method includes: in response to the control code of the digital delay chain switching from the first code value to the second code value, determining the expected level on the output node of each of the plurality of inverters based on the first code value and the level of the input signal; then, through the sub - circuits of each of the plurality of inverters, making the level on the output node of each of the plurality of inverters a controllable level controlled by the sub - circuits associated with each of the plurality of inverters, and making the controllable level controlled by the sub - circuits associated with each of the plurality of inverters the determined expected level on the output node of each of the plurality of inverters. Thus, when the control code of the digital delay chain switches from the first code value to the second code value, the level of the input signal may be in the high - level state, that is, corresponding to digital logic "1", or the level of the input signal may be in the low - level state, that is, corresponding to digital logic "0". The first code value, that is, the control logic of the digital delay chain before switching, determines which inverters in the digital delay chain are turned on and which are turned off before switching. Therefore, determining the expected level on the output node of each of the plurality of inverters based on the first code value and the level of the input signal, based on the high - level or low - level state of the input signal, determines that the expected state of each internal node of the digital delay chain should be in the low - level state or the high - level state, that is, determines the expected level on the output node of each of the plurality of inverters for reference in subsequent steps.

[0032] Refer to Figure 2 , Figure 2Schematic diagram of the internal node states of the first implementation of the digital delay chain provided by the embodiments of the present application. Figure 2 It is shown that the digital delay chain includes a plurality of inverters, namely inverter A210, inverter B211, inverter C212, inverter D213, inverter E214, inverter F215, inverter G216, inverter H217, inverter I218, inverter J219, inverter K220, and inverter L221. Among them, the turned-on inverters constitute the delay path in the digital delay chain. As mentioned above, the first code value, that is, the control logic of the digital delay chain before switching, determines which inverters in the digital delay chain are turned on and which are turned off before switching. Here, for illustrative purposes only, the delay path, that is, the turned-on inverters, includes inverter A210, inverter B211, inverter C212, inverter H217, inverter I218, inverter J219, and inverter K220. Thus, based on the first code value and the level of the input signal, the expected levels on the output nodes of the respective inverters are determined. In this way, based on the high-level state or low-level state of the input signal, it is determined that the expected states of the internal nodes of the digital delay chain should be in the low-level state or high-level state, that is, the expected levels on the output nodes of the respective inverters are determined. Figure 2 The input signal A201 in is a high level "1", so the expected levels on the output nodes of the inverters in can be determined in combination with the first code value. Figure 2 In, "1" means that the expected level is in the high-level state, and "0" means that the expected level is in the low-level state. Finally, the output signal A203 of the digital delay chain is a low level "0".

[0033] Figure 3 Schematic diagram of the internal node states of the second implementation of the digital delay chain provided by the embodiments of the present application.

[0034] Figure 3As shown, the digital delay chain includes a plurality of inverters, namely inverter M310, inverter N311, inverter O312, inverter P313, inverter Q314, inverter R315, inverter S316, inverter T317, inverter U318, inverter V319, inverter W320, and inverter X321. Among them, the turned-on inverters constitute the delay path in the digital delay chain. As mentioned above, the first code value, that is, the control logic of the digital delay chain before switching, determines which inverters in the digital delay chain are turned on and which are turned off before switching. Here, for illustrative purposes only, the delay path, that is, the turned-on inverters, includes inverter M310, inverter N311, inverter O312, inverter T317, inverter U318, inverter V319, and inverter W320. Thus, based on the first code value and the level of the input signal, the expected level on the output node of each of the plurality of inverters is determined. In this way, based on the high-level state or low-level state of the input signal, it is determined that the expected state of each internal node of the digital delay chain should be in the low-level state or high-level state, that is, the expected level on the output node of each of the plurality of inverters is determined. Figure 3 The input signal B301 in is at a low level "0", so combined with the first code value, it can be determined Figure 3 the expected level on the output node of the inverter in, where "1" means the expected level is in the high-level state and "0" means the expected level is in the low-level state. Finally, the output signal B303 of the digital delay chain is at a high level "1".

[0035] Refer to Figure 1 、 Figure 2 and Figure 3 , according to the state of the input signal of the digital delay chain before switching (switching control code when the input signal is at a low level or a high level), the signal state on each node in the digital delay chain is determined. For example, the state of the turned-on inverter or the delay unit is determined by the state of the input signal of the digital delay chain. The state of the turned-off inverter, that is, the inverter or delay unit that is not turned on, is pulled high or low according to the input signal state. Thus, when switching the control code, whether the inverter or the delay unit in the digital delay chain is turned on or off, it can be ensured that the signal state on each node in the digital delay chain is a definite state, thus avoiding the generation of glitch phenomena. That is, by pulling the uncertain state to a definite level before switching the control code according to the state of the input signal, the generation of glitch phenomena is avoided. In this way, the time required to switch the control logic of the digital delay chain is shortened, which helps to improve the utilization efficiency of the digital delay chain, is beneficial to improving the calibration efficiency and meeting the timing adjustment requirements at higher interface rates.

[0036] Refer toFigure 1 , Figure 2 and Figure 3 , in a possible implementation, the control code of the digital delay chain is used to control each of the plurality of inverters to be in an on state or an off state. The inverters in the on state among the plurality of inverters together form a delay path in the digital delay chain, and the input signal of the digital delay chain passes through the delay path and is used as the output signal of the digital delay chain. In this way, through the circuit structure design of the optimized sub-circuit and the optimized switching method, it is ensured that the state of the internal nodes of the digital delay chain is determined when the control code is switched, regardless of whether the inverter is turned on or off. In this way, the generation of glitch phenomena is effectively avoided, and the overall time for the digital delay chain to complete a single switch can be significantly shortened, which is beneficial to improving the calibration efficiency and meeting the timing adjustment requirements at higher interface rates.

[0037] In a possible implementation, the sub-circuits associated with the plurality of inverters are used to make the levels on the output nodes of the plurality of inverters determined by the plurality of inverters themselves when the control code of the digital delay chain is not switched. In this way, it is ensured that the digital delay chain can perform controllable delay processing normally when the control code is not switched. When a switch is required, that is, when the control code is switched, it is ensured that the state of the internal nodes of the digital delay chain is determined, regardless of whether the inverter is turned on or off. In this way, the generation of glitch phenomena is effectively avoided, and the overall time for the digital delay chain to complete a single switch can be significantly shortened, which is beneficial to improving the calibration efficiency and meeting the timing adjustment requirements at higher interface rates.

[0038] In a possible implementation, determining the expected levels on the output nodes of the plurality of inverters based on the first code value and the level of the input signal includes: determining the inverters in the off state among the plurality of inverters based on the first code value, and then determining the expected levels on the output nodes of the inverters in the off state among the plurality of inverters based on the level of the input signal. In this way, the expected levels on the output nodes of the plurality of inverters are determined based on the first code value and the level of the input signal. In this way, based on the high level state or the low level state of the input signal, it is determined that the expected states of the internal nodes of the digital delay chain should be in the low level state or the high level state, that is, the expected levels on the output nodes of the plurality of inverters are determined. Furthermore, when the uncertain state is pulled to the determined level before switching the control code according to the state of the input signal, the generation of glitch phenomena can be avoided.

[0039] In a possible implementation, determining the expected levels on the output nodes of the plurality of inverters based on the first code value and the level of the input signal includes: determining the inverters in the on state among the plurality of inverters based on the first code value, and then determining the expected levels on the output nodes of the inverters in the on state among the plurality of inverters based on the level of the input signal. In this way, the expected levels on the output nodes of the plurality of inverters are determined based on the first code value and the level of the input signal. Based on the high-level state or low-level state of the input signal, it is determined that the expected states of the internal nodes of the digital delay chain should be in the low-level state or high-level state, that is, the expected levels on the output nodes of the plurality of inverters are determined. Furthermore, when the uncertain state is pulled to a definite level before the switching control code according to the state of the input signal, the generation of glitches can be avoided.

[0040] In a possible implementation, the switching method further includes: after the control code of the digital delay chain is switched from the first code value to the second code value, through the respective sub-circuits of the plurality of inverters, the levels on the output nodes of the plurality of inverters are determined by the respective plurality of inverters. In this way, after the switching is completed, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be determined by the inverter associated with the sub-circuit, which means that the level on the output node of the inverter is determined by the output situation of the inverter itself. For example, the inverter may be turned off, that is, not on the delay path, or the inverter may be turned on, that is, the logical information of the input node of the inverter is inverted and then output. In this way, it helps to ensure that the digital delay chain can perform controllable delay processing normally after the switching is completed.

[0041] In a possible implementation, the sub-circuits associated with the plurality of inverters are tri-state gate circuits, and the tri-state gate circuits switch between a high-impedance state, a high-level output state, and a low-level output state. When the tri-state gate circuit is in the high-impedance state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be determined by the inverter associated with the sub-circuit. The characteristic of the tri-state gate circuit is that it can switch between a high-impedance state, a high-level output state, and a low-level output state, that is, it can be in a high-impedance state or a cut-off state, and can also output a high level or a low level. Thus, the characteristic of the tri-state gate circuit can be utilized. When the tri-state gate circuit is in the high-impedance state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be determined by the inverter associated with the sub-circuit. Thus, the high-impedance state of the tri-state gate circuit corresponds to the situation where no switching control code is required. For example, in the case of the normal use of the digital delay chain, in this case, the tri-state gate circuit is in the high-impedance state, that is, the cut-off state, and the level on the output node of the inverter associated with the sub-circuit is determined by the inverter associated with the sub-circuit. Therefore, when the tri-state gate circuit is in the high-impedance state, the level on the output node of the inverter is determined by the output situation of the inverter itself. For example, the inverter may be turned off, that is, not on the delay path, or the inverter may be turned on, that is, the logical information on the input node of the inverter is inverted and then output. Thus, the circuit structure design of the optimized sub-circuit is realized by using the principle of the tri-state gate circuit. When switching the control code, regardless of whether the inverters or the delay units in the digital delay chain are turned on or off, the signal states on each node in the digital delay chain can be ensured to be in a definite state, thereby avoiding the generation of glitch phenomena. That is, by pulling the uncertain state to a definite level before switching the control code according to the state of the input signal, the generation of glitch phenomena is avoided.

[0042] In some embodiments, when the tri-state gate circuit is in the high-level output state, the sub-circuit is configured to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a high level. The characteristic of the tri-state gate circuit is that it can switch between the high-impedance state, the high-level output state, and the low-level output state, that is, it can be in the high-impedance state or the isolation state, and can also output a high level or a low level. Thus, the characteristic of the tri-state gate circuit can be utilized. When the tri-state gate circuit is in the high-impedance state, the sub-circuit is configured to make the level on the output node of the inverter associated with the sub-circuit be determined by the inverter associated with the sub-circuit. Thus, the high-impedance state of the tri-state gate circuit corresponds to the situation where no control code needs to be switched. For example, in the case of the conventional use of the digital delay chain, in this case, the tri-state gate circuit is in the high-impedance state, that is, the isolation state, and the level on the output node of the inverter associated with the sub-circuit is determined by the inverter associated with the sub-circuit. Therefore, when the tri-state gate circuit is in the high-impedance state, the level on the output node of the inverter is determined by the output situation of the inverter itself. For example, the inverter may be turned off, that is, not on the delay path, or the inverter may be turned on, that is, the logical information on the input node of the inverter is inverted and then output. Further, the high-level output state of the tri-state gate circuit corresponds to the situation where the controllable level is a high level. In this case, the tri-state gate circuit is in the high-level output state, and the level on the output node of the inverter associated with the sub-circuit is a controllable level controlled by the sub-circuit. Therefore, when the tri-state gate circuit is in the high-level output state, the level on the output node of the inverter is a controllable level controlled by the sub-circuit and is independent of the output of the inverter itself, that is, not determined by the output situation of the inverter itself; and the controllable level is a high level, which means that the high level is pulled to the stable state. Thus, the circuit structure design of the optimized sub-circuit is realized by using the principle of the tri-state gate circuit. When switching the control code, regardless of whether the inverter or the delay unit in the digital delay chain is turned on or off, it can ensure that the signal states on each node in the digital delay chain are in a determined state, thereby avoiding the generation of glitch phenomena, that is, by pulling the uncertain state to the determined level before switching the control code according to the state of the input signal, thereby avoiding the generation of glitch phenomena.

[0043] In some embodiments, when the tri-state gate circuit is in the low-level output state, the sub-circuit is configured to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is the low level. The characteristic of the tri-state gate circuit is that it can switch between the high-impedance state, the high-level output state, and the low-level output state, that is, it can be in the high-impedance state or the isolation state, and can also output a high level or a low level. Thus, taking advantage of the characteristics of the tri-state gate circuit, when the tri-state gate circuit is in the high-impedance state, the sub-circuit is configured to make the level on the output node of the inverter associated with the sub-circuit be determined by the inverter associated with the sub-circuit. Thus, the high-impedance state of the tri-state gate circuit corresponds to the situation where no control code needs to be switched. For example, in the normal use of the digital delay chain, in this case, the tri-state gate circuit is in the high-impedance state, that is, the isolation state, and the level on the output node of the inverter associated with the sub-circuit is determined by the inverter associated with the sub-circuit. Therefore, when the tri-state gate circuit is in the high-impedance state, the level on the output node of the inverter is determined by the output condition of the inverter itself. For example, the inverter may be turned off, that is, not on the delay path, or the inverter may be turned on, that is, the logical information on the input node of the inverter is inverted and then output. Further, the low-level output state of the tri-state gate circuit corresponds to the situation where the controllable level is the low level. In this case, the tri-state gate circuit is in the low-level output state, and the level on the output node of the inverter associated with the sub-circuit is the controllable level controlled by the sub-circuit. Therefore, when the tri-state gate circuit is in the low-level output state, the level on the output node of the inverter is the controllable level controlled by the sub-circuit and is independent of the output of the inverter itself, that is, not determined by the output condition of the inverter itself; and the controllable level is the low level, which means pulling down the level to a stable state. Thus, using the principle of the tri-state gate circuit, the circuit structure design of the optimized sub-circuit is realized. When switching the control code, regardless of whether the inverter or the delay unit in the digital delay chain is turned on or off, it can be ensured that the signal states on each node in the digital delay chain are in a determined state, thereby avoiding the generation of glitch phenomena. That is, by pulling the uncertain state to a determined level before switching the control code according to the state of the input signal, the generation of glitch phenomena is avoided.

[0044] In a possible implementation manner, the switching method is used for the calibration mode or the normal mode of the digital delay chain. When calibrating by using a calibration circuit, that is, in the calibration mode, since the switching control logic needs to be switched, for example, the control code is gradually increased from small to large, that is, the number of inverters to be turned on is increased one by one. This means that the states of the inverters in the digital delay chain may be unstable at this time. When switching the control code, it may cause glitches in the output signal, which is caused by the output of the inverter being reversed. In addition, in addition to the need to frequently switch the control logic in the calibration mode, in some application scenarios, multiple different delays need to be output through the digital delay chain, such as link congestion testing, clock signal alignment, etc. Therefore, similar to the need to gradually increase the control code from small to large in the calibration mode, in this case, the number of inverters to be turned on also needs to be increased one by one, which involves frequently switching the control logic in a short time. Thus, through the circuit structure design of the sub-circuit with optimized design and the switching method with optimized design, it is ensured that the states of the internal nodes of the digital delay chain are determined when the control code is switched, regardless of whether the inverter is turned on or off. In this way, the generation of glitch phenomena is effectively avoided, and the entire time for the digital delay chain to complete a single switch can be significantly shortened, which is beneficial to improving the calibration efficiency and meeting the timing adjustment requirements under higher interface rates.

[0045] Figure 4 FIG. is a schematic diagram of a delay unit sub-module including an inverter and an associated sub-circuit in a digital delay chain provided by an embodiment of the present application. The digital delay chain includes a plurality of inverters and sub-circuits respectively associated with the plurality of inverters. The sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit or a level determined by the inverter associated with the sub-circuit. The switching process of the control code of the digital delay chain from the first code value to the second code value includes: determining the expected levels on the output nodes of the plurality of inverters respectively based on the first code value and the level of the input signal; then, through the sub-circuits of the plurality of inverters respectively, making the levels on the output nodes of the plurality of inverters respectively be controllable levels controlled by the sub-circuits respectively associated with the plurality of inverters, and making the controllable levels controlled by the sub-circuits respectively associated with the plurality of inverters be the determined expected levels on the output nodes of the plurality of inverters respectively. Figure 4 For example, the digital delay chain includes a plurality of delay unit sub-modules, and each delay unit sub-module is composed of an inverter and a sub-circuit associated with the inverter. Figure 4It is schematically shown that the inverter is composed of transistor M2 and transistor M3. When the inverter is turned on, it is used to process the input signal 401 to obtain the corresponding inverted logic signal, and transmit it to the subsequent circuit through the output node 405. The sub-circuit includes transistor M1, transistor M4, transistor M5 and transistor M6. Among them, the power supply voltage 403 is used to supply power to the delay unit sub-module. It should be understood that Figure 4 The specific circuit elements and connection relationships shown in are illustrative rather than restrictive. As long as it conforms to the switching method of the digital delay chain and the principle of the digital delay chain provided in the embodiments of the present application, any suitable specific circuit design structure can be used to implement the relevant characteristics and functions.

[0046] Figure 4 The shown delay unit sub-module, including the inverter and the associated sub-circuit therein, can be used to form a digital delay chain. Through the circuit structure design of the optimized sub-circuit and the optimized switching method, it is realized that when the control code is switched, the states of the internal nodes of the digital delay chain are determined, regardless of whether the inverter is turned on or off. In this way, the generation of glitch phenomena is effectively avoided, and the entire time for the digital delay chain to complete a single switch can be significantly shortened, which is beneficial to improving the calibration efficiency and meeting the timing adjustment requirements at higher interface rates. Specifically, according to the state of the input signal before the digital delay chain is switched (switching the control code when the input signal is low or high), the signal states at each node in the digital delay chain are determined. For example, the state of the turned-on inverter or the delay unit is determined by the state of the input signal of the digital delay chain. The state of the turned-off inverter, that is, the inverter or the delay unit that is not turned on, is pulled high or low according to the input signal state. In this way, when the control code is switched, regardless of whether the inverter or the delay unit in the digital delay chain is turned on or off, it can be ensured that the signal states at each node in the digital delay chain are in a determined state, thus avoiding the generation of glitch phenomena. That is, by pulling the uncertain state to a determined level before switching the control code according to the state of the input signal, the generation of glitch phenomena is avoided. In this way, the time required to switch the control logic of the digital delay chain is shortened, which helps to improve the usage efficiency of the digital delay chain and is beneficial to improving the calibration efficiency and meeting the timing adjustment requirements at higher interface rates.

[0047] Refer to Figure 4 , Figure 4The delay unit sub-module including an inverter and associated sub-circuits as shown adopts the design principle of a tri-state gate circuit. The tri-state gate circuit switches between a high-impedance state, a high-level output state, and a low-level output state. When the tri-state gate circuit is in the high-impedance state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be determined by the inverter associated with the sub-circuit. When the tri-state gate circuit is in the high-level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a high level. When the tri-state gate circuit is in the low-level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a low level. Figure 4 The delay unit sub-module of Figure 4 is connected to the power supply voltage 403. When both transistor M1 and transistor M4 are turned on, at this time both transistor M5 and transistor M6 are turned off, and this circuit is equivalent to the function of an inverter, that is, an inverter composed of transistor M2 and transistor M3 is used to perform an inverse logic process on the input signal 401 and then output it to the output node 405. Therefore, when transistor M1, transistor M2, transistor M3, and transistor M4 are all turned on, transistor M2 and transistor M3 form an inverter, for example Figure 2 any inverter included in the digital delay chain shown in Figure 2 , such as inverter A210. Therefore, by the control signal A410 and the control signal B412, it is possible to turn on or turn off transistor M1 and transistor M4 simultaneously. For example, the control signal B412 can be made an inverse signal relative to the control signal A410 through inverse code processing. Here, when both transistor M1 and transistor M4 are turned on, it corresponds to the situation where the control code of the digital delay chain does not need to be switched. In this case, the control signal C414 and the control signal D416 can be used to turn off transistor M5 and transistor M6 simultaneously, so that Figure 4The delay unit sub-module shown is equivalent to an inverter, and the voltage on output node 405 is determined by the inverter (formed by transistors M2 and M3). Thus, when the tri-state gate circuit is in the high-impedance state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit be determined by the inverter associated with the sub-circuit. Therefore, when the tri-state gate circuit is in the high-impedance state, the level on the output node of the inverter is determined by the output condition of the inverter itself. For example, the inverter may be turned off, i.e., not on the delay path, or the inverter may be turned on, i.e., the logical information on the input node of the inverter is inverted and then output. In this way, the circuit structure design of the optimized sub-circuit is realized by using the principle of the tri-state gate circuit. When switching the control code, regardless of whether the inverters or delay units in the digital delay chain are turned on or off, it can ensure that the signal states on each node in the digital delay chain are in a determined state, thus avoiding the generation of glitch phenomena. That is, by pulling the uncertain state to a determined level before switching the control code according to the state of the input signal, the generation of glitch phenomena is avoided.

[0048] Continue to refer to Figure 4, when both transistor M1 and transistor M4 are turned off, in this case, transistor M5 is selectively turned on while transistor M6 is turned off, or transistor M5 is turned off while transistor M6 is turned on. Thus, control signal A410 and control signal B412 can turn off transistor M1 and transistor M4 simultaneously. Through control signal C414 and control signal D416, transistor M5 can be turned on while transistor M6 is turned off, which means the voltage on output node 405 is pulled up to a stable state under the influence of power supply voltage 403. On the contrary, through control signal A410 and control signal B412, transistor M1 and transistor M4 can be turned off simultaneously. Through control signal C414 and control signal D416, transistor M5 can be turned off while transistor M6 is turned on, which means the voltage on output node 405 is pulled down to a stable state under the influence of the ground terminal. In this way, it is realized that the sub - circuit is used to make the level on the output node of the inverter associated with the sub - circuit a controllable level controlled by the sub - circuit. The control of control signal C414 and control signal D416 is to determine the internal node state of the digital delay chain according to the state of the input signal. Among them, when transistor M5 is turned on while transistor M6 is turned off, it means the voltage on output node 405 is pulled up to a stable state under the influence of power supply voltage 403, which corresponds to the high - level output state of the tri - state gate circuit, that is, the controllable level is high. When transistor M5 is turned off while transistor M6 is turned on, it means the voltage on output node 405 is pulled down to a stable state under the influence of the ground terminal, which corresponds to the low - level output state of the tri - state gate circuit, that is, the controllable level is low. In this way, the circuit structure design of the optimized sub - circuit is realized by using the principle of the tri - state gate circuit. When switching the control code, no matter whether the inverters or delay units in the digital delay chain are turned on or off, it can ensure that the signal states on each node in the digital delay chain are in a definite state, thus avoiding the generation of glitch phenomena. That is, by pulling the uncertain state to a definite level before switching the control code according to the state of the input signal, the generation of glitch phenomena is avoided.

[0049] Refer to Figure 1 , Figure 2 , Figure 3 And Figure 4, before switching the control code, the states of each node inside the delay chain can be determined according to whether the input signal is at a low level or a high level. Then, based on the control code, it can be determined which delay units are turned on, that is, included in the delay path, and which delay units are turned off, that is, not included in the delay path. For the turned-on delay units among them, by turning on transistor M1, transistor M4 and turning off transistor M5 and transistor M6, they act as an inverter, that is, the state of the delay unit is determined by the state of the input signal of the digital delay chain. For the turned-off delay units among them, transistor M1 and transistor M4 are turned off, and it is judged whether to pull high or pull low according to the determined states of each node, so as to selectively turn on transistor M5 while turning off transistor M6, or turn off transistor M5 while turning on transistor M6. In this way, through the circuit structure design of the optimized sub-circuit and the optimized switching method, it is realized that the states of the internal nodes of the digital delay chain are determined when the control code is switched, regardless of whether the inverter is turned on or off. In this way, the generation of glitch phenomena is effectively avoided, the overall time for the digital delay chain to complete a single switch can be significantly shortened, which is beneficial to improving the calibration efficiency and meeting the timing adjustment requirements at higher interface rates. It should be understood that Figure 4 The design principle of the tri-state gate circuit shown in

[0050] Refer to Figure 4 , in a possible implementation manner, the control code of the digital delay chain is used to control each inverter in the plurality of inverters to be in an on state or an off state. The inverters in the on state in the plurality of inverters together constitute the delay path in the digital delay chain. The input signal of the digital delay chain passes through the delay path and then serves as the output signal of the digital delay chain. In this way, through the circuit structure design of the optimized sub-circuit and the optimized switching method, it is realized that the states of the internal nodes of the digital delay chain are determined when the control code is switched, regardless of whether the inverter is turned on or off. In this way, the generation of glitch phenomena is effectively avoided, the overall time for the digital delay chain to complete a single switch can be significantly shortened, which is beneficial to improving the calibration efficiency and meeting the timing adjustment requirements at higher interface rates.

[0051] In a possible implementation, the sub-circuits associated with the plurality of inverters are used to make the levels on the output nodes of the plurality of inverters determined by the plurality of inverters themselves when the control code of the digital delay chain does not switch. In this way, it is ensured that the digital delay chain can perform controllable delay processing normally when the control code does not switch. When a switch is required, that is, when the control code switches, it is ensured that the states of the internal nodes of the digital delay chain are determined, regardless of whether the inverter is turned on or off, effectively avoiding the generation of glitch phenomena, significantly shortening the entire time for the digital delay chain to complete a single switch, and being beneficial to improving the calibration efficiency and meeting the timing adjustment requirements at higher interface rates.

[0052] In a possible implementation, after the control code of the digital delay chain completes the switch from the first code value to the second code value, the sub-circuits associated with the plurality of inverters are used to make the levels on the output nodes of the plurality of inverters determined by the plurality of inverters themselves. In this way, after the switch is completed, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit determined by the inverter associated with the sub-circuit, which means that the level on the output node of the inverter is determined by the output situation of the inverter itself. For example, the inverter may be turned off, that is, not on the delay path, or the inverter may be turned on, that is, the logical information of the input node of the inverter is inverted and then output. In this way, it helps to ensure that the digital delay chain can perform controllable delay processing normally after the switch is completed.

[0053] In a possible implementation, the sub-circuits associated with the plurality of inverters are tri-state gate circuits, and the tri-state gate circuits switch between a high-impedance state, a high-level output state, and a low-level output state. When the tri-state gate circuit is in the high-impedance state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit determined by the inverter associated with the sub-circuit.

[0054] In some embodiments, when the tri-state gate circuit is in the high-level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a high level. In this way, the circuit structure design of the optimized sub-circuit is realized by using the principle of the tri-state gate circuit. When switching the control code, regardless of whether the inverters or delay units in the digital delay chain are turned on or off, it can be ensured that the signal states on each node in the digital delay chain are in a determined state, thus avoiding the generation of glitch phenomena, that is, by pulling the uncertain state to a determined level before switching the control code according to the state of the input signal, thus avoiding the generation of glitch phenomena.

[0055] In some embodiments, when the tri-state gate circuit is in the low-level output state, the sub-circuit is configured to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a low level. In this way, the circuit structure design of the optimized sub-circuit is realized by using the principle of the tri-state gate circuit. When switching the control code, regardless of whether the inverters or delay units in the digital delay chain are turned on or off, it can be ensured that the signal states on each node in the digital delay chain are in a definite state, thus avoiding the generation of glitch phenomena. That is, by pulling the indefinite state to a definite level before switching the control code according to the state of the input signal, the generation of glitch phenomena is avoided.

[0056] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles for the method and device to solve problems are similar, the embodiments, implementation manners, examples or implementation modes of the method and device can be referred to each other, and the repeated parts will not be described again. The embodiments of the present application further provide a system, which includes a plurality of computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that the system can implement can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described again here.

[0057] The embodiments of the present application further provide a computer-readable storage medium, in which computer instructions are stored. When the computer instructions run on a computer device (such as one or more processors), the method steps in the above method embodiments can be implemented. The specific implementation of the processor of the computer-readable storage medium when executing the above method steps can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described again here.

[0058] Those skilled in the art should understand that the embodiments of this application can be provided as a method, a system, or a computer program product. This application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. The embodiments of this application can be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. This application can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in the embodiments of this application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center containing one or more collections of available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium, or a semiconductor medium. The semiconductor medium can be a solid-state drive, or a random access memory, a flash memory, a read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, a register, or any other suitable form of storage medium.

[0059] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of this application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks. These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in Figure 1One process or multiple processes and / or boxes Figure 1 The functions specified in one box or multiple boxes. These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the process Figure 1 One process or multiple processes and / or boxes Figure 1 The steps of the functions specified in one box or multiple boxes.

[0060] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method embodiments of the present application can be adjusted, combined or deleted according to actual needs; the modules in the system embodiments of the present application can be divided, combined or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and variations.

Claims

1. A method for switching a digital delay chain, characterized in that: The digital delay chain includes a plurality of inverters and sub-circuits associated with the plurality of inverters, wherein the sub-circuits are used to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit or determined by the inverter associated with the sub-circuit, and the switching method includes: In response to a control code of the digital delay chain switching from a first code value to a second code value, determining an expected level at an output node of each of the plurality of inverters based on the first code value and a level of an input signal; Then, through the respective sub-circuits of the multiple inverters, the levels on the respective output nodes of the multiple inverters are controllable levels controlled by the respective sub-circuits associated with the multiple inverters, and the controllable levels controlled by the respective sub-circuits associated with the multiple inverters are the determined expected levels on the respective output nodes of the multiple inverters.

2. The switching method according to claim 1, characterized in that: The control code of the digital delay chain is used to control each of the multiple inverters to be in an on state or an off state. The inverters in the on state of the multiple inverters together constitute a delay path in the digital delay chain. The input signal of the digital delay chain passes through the delay path and serves as the output signal of the digital delay chain.

3. The switching method according to claim 1, characterized in that: The sub-circuits associated with each of the plurality of inverters are used to ensure that the levels on the output nodes of each of the plurality of inverters are determined by each of the plurality of inverters when the control code of the digital delay chain is not switched.

4. The switching method according to claim 1, characterized in that: Determining expected levels on the output nodes of each of the plurality of inverters based on the first code value and the level of the input signal, comprising: determining an inverter in a closed state among the plurality of inverters based on the first code value, and then determining expected levels on the output nodes of each of the inverters in a closed state among the plurality of inverters based on the level of the input signal.

5. The switching method according to claim 1, characterized in that: Determining expected levels on the output nodes of each of the plurality of inverters based on the first code value and the level of the input signal, comprising: determining an inverter in an on state among the plurality of inverters based on the first code value, and then determining expected levels on the output nodes of each of the inverters in an on state among the plurality of inverters based on the level of the input signal.

6. The switching method according to claim 1, characterized in that: The switching method also includes: after the control code of the digital delay chain completes switching from the first code value to the second code value, through the respective sub-circuits of the plurality of inverters, so that the levels on the respective output nodes of the plurality of inverters are determined by the respective plurality of inverters.

7. The switching method according to claim 1, characterized in that: The sub-circuit associated with each of the multiple inverters is a three-state gate circuit, which switches between a high-impedance state, a high-level output state, and a low-level output state. When the three-state gate circuit is in the high-impedance state, the sub-circuit is used to ensure that the level on the output node of the inverter associated with the sub-circuit is determined by the inverter associated with the sub-circuit.

8. The switching method according to claim 7, characterized in that: When the tri-state gate circuit is in a high level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a high level.

9. The switching method according to claim 7, characterized in that: When the tri-state gate circuit is in a low level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a low level.

10. The switching method according to claim 1, characterized in that: The switching method is used in a calibration mode or a normal mode of the digital delay chain.

11. A digital delay chain, characterized in that: The digital delay chain includes a plurality of inverters and sub-circuits associated with each of the plurality of inverters, wherein the sub-circuits are used to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit or determined by the inverter associated with the sub-circuit, and the switching process of the control code of the digital delay chain from a first code value to a second code value includes: determining the expected level on the output nodes of each of the plurality of inverters based on the first code value and the level of the input signal; then, through the sub-circuits of each of the plurality of inverters, making the level on the output nodes of each of the plurality of inverters a controllable level controlled by the sub-circuit associated with each of the plurality of inverters, and making the controllable level controlled by the sub-circuit associated with each of the plurality of inverters the determined expected level on the output nodes of each of the plurality of inverters.

12. The digital delay chain according to claim 11, characterized in that: The control code of the digital delay chain is used to control each of the multiple inverters to be in an on state or an off state. The inverters in the on state of the multiple inverters together constitute a delay path in the digital delay chain. The input signal of the digital delay chain passes through the delay path and serves as the output signal of the digital delay chain.

13. The digital delay chain according to claim 11, characterized in that: The sub-circuits associated with each of the plurality of inverters are used to ensure that the levels on the output nodes of each of the plurality of inverters are determined by each of the plurality of inverters when the control code of the digital delay chain is not switched.

14. The digital delay chain according to claim 11, characterized in that: After the control code of the digital delay chain is switched from the first code value to the second code value, the levels on the output nodes of the inverters are determined by the inverters through their respective sub-circuits.

15. The digital delay chain according to claim 11, characterized in that: The sub-circuit associated with each of the multiple inverters is a three-state gate circuit, which switches between a high-impedance state, a high-level output state, and a low-level output state. When the three-state gate circuit is in the high-impedance state, the sub-circuit is used to ensure that the level on the output node of the inverter associated with the sub-circuit is determined by the inverter associated with the sub-circuit.

16. The digital delay chain according to claim 15, characterized in that: When the tri-state gate circuit is in a high level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a high level.

17. The digital delay chain according to claim 15, characterized in that: When the tri-state gate circuit is in a low level output state, the sub-circuit is used to make the level on the output node of the inverter associated with the sub-circuit a controllable level controlled by the sub-circuit, and the controllable level controlled by the sub-circuit is a low level.

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