Comparator with low power consumption, high speed and high precision
By designing an improved "two-tail" dynamic comparator and preamplifier in a high-precision ADC, combined with offset storage technology, the problems of dynamic comparator noise and offset voltage are solved, achieving low power consumption, high speed and high precision comparator effects.
Patent Information
- Application Number
- CN202510046764.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2025-06-10
AI Technical Summary
The dynamic comparator in high-precision ADC has high noise and high offset voltage, making it difficult to apply, and the preamplifier has high power consumption and parasitic capacitance has a great impact on signal voltage division.
A low-power high-speed and high-precision comparator is designed, using an improved "two-tail" dynamic comparator and preamplifier, combining output offset storage and input offset storage technology, and reducing noise and offset effects through the combination of static amplifier and dynamic comparator.
It realizes reduced power consumption, increased speed and accuracy in high-precision ADCs, reduces the complexity of the circuit structure, and enables rapid amplification of tiny input signals and avoids dynamic comparator noise and offset effects.
Smart Images
Figure CN120128148A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of voltage comparators, and in particular relates to a low-power, high-speed and high-precision comparator. Background Art
[0002] The high-precision comparator in the high-precision SAR ADC greater than 14 bits is the key to whether the SAR ADC can achieve high-precision ADC. SAR ADC has obvious power consumption and area advantages in medium and low precision and low power consumption, so it is widely used in many scenarios such as industrial control and biomedicine. Today's low-power technology relies on dynamic comparators. "Strong-arm" dynamic comparators and "double-tail" dynamic comparators are common structures in low-power ADCs. Dynamic comparators have no static current and only work under clock control. Because they have no static power consumption and work at a fast speed, they are generally widely used in SAR ADCs below 12 bits. Although dynamic comparators have low power consumption and high speed, they are difficult to use in high-precision ADCs due to their high noise and high offset voltage caused by device mismatch. In general, the rms (root mean square) of the dynamic comparator noise may reach the mV level, and the offset voltage may be as high as more than ten mV. In addition to the above shortcomings, the interference of the dynamic comparator "kick-back noise" on the input signal is also a difficult problem to solve.
[0003] In order to solve the above-mentioned shortcomings of the dynamic comparator, people add a preamplifier in front of the dynamic comparator to overcome the offset voltage and noise of the dynamic comparator. The preamplifier plus the dynamic comparator is a commonly used overall comparator structure in high-precision ADCs. The offset voltage of the preamplifier can be eliminated by using output offset storage (OOS) or input offset storage (IOS) technology. Using certain ADC calibration algorithms can also better remove the influence of the preamplifier offset voltage. In addition, the equivalent input noise of the preamplifier is much smaller than that of the dynamic comparator. Usually, the rms (root mean square) value of the equivalent input noise of the preamplifier can reach the uV level. If multiple comparisons are performed on each bit of the ADC, the influence of noise can be further suppressed. Although the combination of the preamplifier plus the dynamic comparator has many advantages, the preamplifier consumes huge power consumption and is difficult to be used in low-power scenarios. In the preamplifier using offset storage technology, the voltage division of the signal by parasitic capacitance and offset storage capacitance is also a disadvantage. Therefore, the gain of the preamplifier in the high-precision ADC is usually 60-70dB, and the bandwidth is also tens or even hundreds of MHz. The comparator consumes most of the power consumption of the entire ADC.
[0004] In addition to adding a preamplifier in front of the dynamic comparator, there are also trimming means to directly eliminate the offset voltage of the dynamic comparator. However, usually additional hardware overhead is required, and even after trimming, it still cannot be directly applied to high-precision ADCs. Therefore, the preamplifier is an indispensable part of high-precision voltage comparators. Therefore, how to reduce the power consumption of high-precision voltage comparators and improve the speed of high-precision voltage comparators has become a problem to be solved. Summary of the Invention
[0005] The object of the present invention is to provide a low-power, high-speed and high-precision comparator to solve the above technical problems.
[0006] To solve the technical problems in high-precision comparators that too much power is consumed due to high bandwidth, and the parasitic capacitance of the preamplifier and the offset storage capacitance have an impact on the voltage division of the amplified signal, the specific technical solution of a low-power, high-speed and high-precision comparator of the present invention is as follows: A low-power, high-speed and high-precision comparator includes a preamplifier, an improved "dual-tail type" dynamic comparator latch, offset storage capacitors C1 and switches S1~S3. The preamplifier includes a first-stage static amplifier opm1 and a second-stage static amplifier opm2. Among them, vip and vin are the differential voltage input signals of the comparator, and VCM is the common-mode voltage connected to the input end of the comparator during offset storage. One of the two switches S1 is connected to the positive input end of the first-stage static amplifier opm1 and the common-mode voltage VCM, and the other switch S1 is connected to the negative input end of the first-stage static amplifier opm1 and the common-mode voltage VCM; one of the two switches S2 is connected to the positive input end and the negative output end of the second-stage static amplifier opm2, and the other S2 switch is connected to the negative input end and the positive output end of the second-stage static amplifier opm2. One end of the two switches S2 is also respectively connected to the positive input end and the negative input end of the dynamic comparator latch; one of the two switches S3 is connected to the input signal Vip and the positive input end of the first-stage static amplifier opm1, and the other switch S3 is connected to the input signal Vin and the negative input end of the first-stage static amplifier opm1; one of the two offset storage capacitors C1 is connected to the negative output end of the first-stage static amplifier opm1 and the positive input end of the second-stage static amplifier opm2, and the other offset storage capacitor C1 is connected to the positive output end of the first-stage static amplifier opm1 and the negative input end of the second-stage static amplifier opm2; CLK_latch is the control signal for the normal operation of the dynamic comparator latch, and out is the output signal port of the dynamic comparator latch and also the signal output port of the entire comparator.
[0007] Further, after the ADC is normally powered on, the offset voltage cancellation process of the preamplifier is first carried out. During this process, switches S1 to S2 are closed and S3 is opened. The first-stage static amplifier opm1 adopts the output offset storage technology OOS, and the second-stage static amplifier opm2 adopts the input offset storage technology IOS to prevent the entire preamplifier from output saturation. Under the above switch state, the offset voltages of the first-stage static amplifier opm1 and the second-stage static amplifier opm2 are stored on the capacitor C1.
[0008] Further, the first-stage static amplifier opm1 is an amplifier with a current source and a diode-connected MOS as the load, including MOS transistors M1-M6, where M1 is the tail current source, M2 and M3 are the input differential pair transistors, M4 and M5 are the diode-connected loads, and M3 and M6 are the current source loads; the sources of the PMOS transistors M3, M4, M5, and M6 are connected together and also connected to the power supply voltage VDD. The gate and drain of the PMOS transistor M4 are connected to each other and are simultaneously connected to the drain of the PMOS transistor M3 and the drain of the NMOS transistor M2; the gate and drain of the PMOS transistor M5 are connected to each other and are simultaneously connected to the drain of the PMOS transistor M6 and the drain of the NMOS transistor M3; the gates of the NMOS transistors M2 and M3 are respectively connected to the positive and negative input signals of this stage, and the source ends are connected together and simultaneously connected to the drain of the NMOS transistor M1; BP is the gate bias voltage of the PMOS transistors M3 and M6, and BIAS1 is the gate bias voltage of the NMOS transistor M1; Vip and Vin are the input signals of this stage.
[0009] Further, the second-stage static amplifier opm2 includes MOS transistors M7 to M17, where M7 is a tail current source transistor, M8 and M9 are input pair transistors, M14 and M17 are MOS transistors connected in diode configuration as loads, and M15 and M16 are cross-coupled MOS transistors; the gates and drains of PMOS transistors M14 and M17 are each shorted together; the gate of PMOS transistor M15 is connected to the drain of PMOS transistor M16, and the gate of PMOS transistor M16 is connected to the drain of PMOS transistor M15 to form a cross-coupled structure and are respectively connected to the drains of PMOS transistors M14 and M17 with their gates and drains shorted. The sources of PMOS transistors M14, M15, M16, and M17 are connected together and connected to VDD; the source, drain, and substrate of PMOS transistor M10 are shorted together while the gate forms a two-terminal device at the other end. PMOS transistors M11, M12, and M13 are connected in the same way as M10. M10 and M11 are connected end to end to form a new two-port structure, where one end is connected to the gate of NMOS transistor M8 and the other end is connected to the drain of M16 and the drain of NMOS transistor M9; the structure formed by M12 and M13 is the same as the structure formed by M10 and M11, where one end is connected to the gate of NMOS transistor M9 and the other end is connected to the drain of M15 and the drain of NMOS transistor M8; the sources of NMOS transistors M8 and M9 are connected together and connected to the drain of NMOS transistor M7, and BIAS2 is the gate bias voltage of M7; Vip and Vin in the figure represent the input signals of this stage.
[0010] Further, the equivalent load capacitance of input pair transistors M2 and M3 on the gate is Ceq1 = Cgs1+(1+A1)*Cgd1. Here, the subscript "1" only indicates for the first-stage static amplifier opm1. From the above expression, it can be seen that due to the "Miller effect" of the capacitance, the parasitic capacitance Cgd1 between the gates and drains of input pair transistors M2 and M3 is amplified by 1+A1 times, where A1 is the gain of the first-stage static amplifier, and Cgs1 is the parasitic capacitance between the gate and source of transistor M2. However, since the equivalent gate capacitance of the input transistor of the first-stage static amplifier is driven by the capacitive digital-to-analog converter of the previous stage, the equivalent gate capacitance of the input transistor of the first-stage static amplifier does not directly affect the speed of the entire pre-stage static amplifier. However, the size of the equivalent gate capacitance of the input transistors in the second-stage static amplifier directly affects the response speed of the entire pre-amplifier.
[0011] Furthermore, M10 to M13 are all MOS capacitors with the source, drain, and substrate segments shorted together. M10 and M11, as well as M12 and M13, are connected end to end. This end-to-end connection of MOS capacitors ensures that a certain capacitance value can still be maintained when the voltage difference across the two ends is close to 0. One end of the MOS capacitor formed by M10 and M11 is connected to the gate of M8, and the other end is connected to the drain of M9. When performing small-signal amplification, the small-signal gain from the gate of M8 to the drain of M9 is in-phase amplified by A2 times. Here, A2 is the gain of the second-stage static amplifier. Therefore, the equivalent load capacitance at the gates of the input pair transistors of the second-stage static amplifier is Ceq2 = Cgs2 + (1 + A2) * Cgd2 + (1 - A2) * Cp. Here, Cp is the capacitance value of the MOS capacitor formed by M10 and M11, Cgs2 is the parasitic capacitance between the gate and source of M8, and Cgd2 is the parasitic capacitance between the gate and drain of M8.
[0012] Furthermore, by increasing the MOS capacitance, the equivalent load capacitance at the gates of the input pair transistors is reduced. During the actual circuit design process, the size of the MOS capacitance is carefully adjusted through simulation to achieve the best capacitance cancellation effect.
[0013] Furthermore, the "double-tail type" dynamic voltage comparator latch includes MOS transistors M18 - M31. Among them, NMOS transistors M19 and M20 are the input pair transistors. The sources of NMOS transistors M19 and M20 are connected together and connected to the drain of NMOS transistor M18. PMOS transistors M22 and M23 form a cross-coupled structure. The gates of PMOS transistors M21 and M23 are both connected to the clock CLK, and the drains are respectively connected to nodes fn and fp, that is, respectively connected to the gates of M23 and M22. PMOS transistor M29 and NMOS transistor M27 form inverter one, and PMOS transistor M30 and NMOS transistor M28 also form inverter two. These two inverters are connected end to end to form a latch. The drain of PMOS transistor M31 is connected to the sources of M29 and M30, and the gate is connected to the inverted clock CLKN. The gates of NMOS transistors M25 and M26 are respectively connected to nodes fn and fp, and the drains of M25 and M26 are respectively connected to the inputs of inverter one and inverter two. Vip and Vin represent the input signals of this stage.
[0014] Furthermore, when the dynamic comparator is turned off, CLK is at a low level, and nodes fn and fp are charged to VDD by M21 and M24. During normal operation, M19 and M20 discharge nodes fn and fp. As long as the voltage of one of the nodes is less than VDD + Vthp, where Vthp is the threshold voltage of the PMOS and is negative, M22 and M23 can start to work normally. At this time, M18 to M23 are equivalent to a static amplifier.
[0015] A low-power, high-speed, and high-precision comparator of the present invention has the following advantages: By using the voltage comparator proposed in the present invention, certain improvements can be achieved in terms of power consumption, speed, and area. Compared with the use of calibration algorithms, trimming means, etc., the complexity of the circuit structure is greatly reduced. In addition, through the combination of an improved dynamic comparator and a preamplifier, small input signals can be quickly amplified while avoiding the influence of dynamic comparator noise and offset. Therefore, it can also be used as a comparator in high-precision ADCs. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a schematic structural diagram of the low-power, high-speed, and high-precision voltage comparator proposed by the present invention.
[0017] Figure 2 It is a circuit structure diagram of the first-stage static amplifier proposed by the present invention.
[0018] Figure 3 It is a circuit structure diagram of the second-stage static amplifier proposed by the present invention.
[0019] Figure 4 It is the improved "dual-tail type" dynamic comparator of the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0020] In order to better understand the purpose, structure, and function of the present invention, the following further describes in detail a low-power, high-speed, and high-precision comparator of the present invention with reference to the accompanying drawings.
[0021] As Figure 1As shown in the figure, a low-power high-speed high-precision comparator of the present invention includes a preamplifier, an improved "dual-tail type" dynamic comparator latch, offset storage capacitors C1 and switches S1 to S3. The preamplifier includes two stages of static amplifiers, namely the first-stage static amplifier opm1 and the second-stage static amplifier opm2. Among them, vip and vin are the differential voltage input signals of the comparator, and VCM is the common-mode voltage connected to the input end of the comparator during offset storage. One of the two switches S1 is connected to the positive input end of the first-stage static amplifier opm1 and the common-mode voltage VCM, and the other switch S1 is connected to the negative input end of the first-stage static amplifier opm1 and the common-mode voltage VCM; one of the two switches S2 is connected to the positive input end and the negative output end of the second-stage static amplifier opm2, and the other S2 switch is connected to the negative input end and the positive output end of the second-stage static amplifier opm2. One end of the two switches S2 is also respectively connected to the positive input end and the negative input end of the dynamic comparator latch; one of the two switches S3 is connected to the input signal Vip and the positive input end of the first-stage static amplifier opm1, and the other switch S3 is connected to the input signal Vin and the negative input end of the first-stage static amplifier opm1; one of the two offset storage capacitors C1 is connected to the negative output end of the first-stage static amplifier opm1 and the positive input end of the second-stage static amplifier opm2, and the other offset storage capacitor C1 is connected to the positive output end of the first-stage static amplifier opm1 and the negative input end of the second-stage static amplifier opm2; CLK_latch is the control signal for the normal operation of the dynamic comparator latch, and out is the output signal port of the dynamic comparator latch and also the signal output port of the entire comparator.
[0022] The working principle of the proposed low-power high-speed high-precision voltage comparator is as follows: After the ADC is normally powered on, the offset voltage elimination process of the preamplifier is first performed to prevent errors during the normal conversion process. During this process, switches S1 to S2 are closed and S3 is open. The first-stage static amplifier opm1 in the preamplifier of the present invention adopts the output offset storage technology (OOS), and the second-stage static amplifier opm2 adopts the input offset storage technology (IOS) to prevent the entire preamplifier from output saturation. Under the above switch states, the offset voltages of the first-stage static amplifier opm1 and the second-stage static amplifier opm2 are stored on the capacitor C1.
[0023] The circuit of the first-stage static amplifier opm1 is as Figure 2As shown. The first-stage static amplifier opm1 is a commonly used amplifier with a current source and diode-connected MOS as the load, including MOS transistors M1 - M6, where M1 is the tail current source, M2 and M3 are the input differential pair transistors, M4 and M5 are the diode-connected loads, and M3 and M6 are the current source loads. Among them, the sources (S) of PMOS transistors M3, M4, M5, and M6 are connected together and also connected to the power supply voltage VDD. The gate (G) and drain (D) of PMOS transistor M4 are connected to each other and are simultaneously connected to the drain (D) of PMOS transistor M3 and the drain (D) of NMOS transistor M2; the gate (G) and drain (D) of PMOS transistor M5 are connected to each other and are simultaneously connected to the drain (D) of PMOS transistor M6 and the drain (D) of NMOS transistor M3; the gates (G) of NMOS transistors M2 and M3 are respectively connected to the positive and negative input signals of this stage, and the source terminals (S) are connected together and also connected to the drain (D) of NMOS transistor M1; BP is the gate bias voltage of PMOS transistors M3 and M6, BIAS1 is the gate bias voltage of NMOS transistor M1; Vip and Vin in the figure represent the input signals of this stage.
[0024] The circuit of the second-stage static amplifier opm2 is as Figure 3As shown. The second-stage static amplifier opm2 includes MOS transistors M7 to M17, where M7 is the tail current source transistor, M8 and M9 are the input pair transistors, M14 and M17 are MOS transistors connected as diodes for the load, and M15 and M16 are cross-coupled MOS transistors. Among them, the gates (G) and drains (D) of PMOS transistors M14 and M17 are each shorted together; the gate (G) of PMOS transistor M15 is connected to the drain (D) of PMOS transistor M16, and the gate (G) of PMOS transistor M16 is connected to the drain (D) of PMOS transistor M15 to form a cross-coupled structure and are respectively connected to the drains of PMOS transistors M14 and M17 with their gates and drains shorted. The sources (S) of PMOS transistors M14, M15, M16, and M17 are connected together and connected to VDD; the source (S), drain (D), and substrate (B) of PMOS transistor M10 are shorted together and the gate is separate as the other end to form a two-terminal device. The connection methods of PMOS transistors M11, M12, and M13 are exactly the same as that of M10. M10 and M11 are connected end to end to form a new two-port structure, where one end is connected to the gate of NMOS transistor M8 and the other end is connected to the drain (D) of M16 and the drain (D) of NMOS transistor M9; the structure formed by M12 and M13 is exactly the same as the structure formed by M10 and M11, where one end is connected to the gate of NMOS transistor M9 and the other end is connected to the drain (D) of M15 and the drain (D) of NMOS transistor M8; the sources (S) of NMOS transistors M8 and M9 are connected together and connected to the drain of NMOS transistor M7, and BIAS2 is the gate bias voltage of M7; Vip and Vin in the figure represent the input signals of this stage. The circuit of this structure can provide a large voltage gain and is often used in the gain stage. M10 to M13 are the circuit structures proposed in the present invention to increase the response speed and reduce the load capacitance, and their principles will be described in detail in the subsequent part. The equivalent load capacitance of the input pair transistors M2 and M3 on the gate is Ceq1 = Cgs1+(1+A1)*Cgd1 (the subscript "1" here only represents for the first-stage static amplifier opm1). It can be seen from the above expression that due to the "Miller effect" of the capacitance, the parasitic capacitance Cgd1 between the gates and drains of the input pair transistors M2 and M3 is amplified by (1+A1) times, where A1 is the gain of the first-stage static amplifier and Cgs1 is the parasitic capacitance between the gate and source of transistor M2. However, since the equivalent gate capacitance of the input transistor of the first-stage static amplifier is driven by the previous-stage CDA (capacitive digital-to-analog converter), the equivalent gate capacitance of the input transistor of the first-stage static amplifier does not directly affect the speed of the entire pre-stage static amplifier. However, the size of the equivalent gate capacitance of the input transistors in the second-stage static amplifier directly affects the response speed of the entire pre-amplifier. In the second-stage static amplifier given in the present invention, M10 to M13 are the key to reducing the parasitic capacitance and increasing the bandwidth.The principle is as follows: M10 to M13 are all MOS capacitors with the source, drain, and substrate segments shorted together. Connecting M10 and M11, as well as M12 and M13, end to end can better reflect their capacitance characteristics. This end-to-end connected MOS capacitor ensures that a certain capacitance value can still be maintained when the voltage difference across both ends is close to 0. One end of the MOS capacitor formed by M10 and M11 is connected to the gate of M8, and the other end is connected to the drain of M9. When performing small-signal amplification, the small-signal gain from the gate of M8 to the drain of M9 is in-phase amplified by A2 times. Here, A2 is the gain of the second-stage static amplifier. Therefore, the equivalent load capacitance at the gate of the input pair transistors of the second-stage static amplifier is Ceq2 = Cgs2 + (1 + A2) * Cgd2 + (1 - A2) * Cp. Here, Cp is the capacitance value of the MOS capacitor formed by M10 and M11, Cgs2 is the parasitic capacitance between the gate and source of M8 transistor, and Cgd2 is the parasitic capacitance between the gate and drain of M8 transistor.
[0025] It can be seen that by increasing the MOS capacitor, the equivalent load capacitance at the gate of the input pair transistors can be reduced. In the actual circuit design process, the size of the MOS capacitor can be carefully adjusted through simulation to achieve the best capacitance cancellation effect. The increased MOS capacitor can significantly reduce the gate parasitic capacitance of the second-stage static circuit, thereby reducing the equivalent load capacitance of the first-stage static amplifier, thus significantly improving the bandwidth of the overall preamplifier and increasing the response speed. The second benefit of increasing the MOS capacitor is that it can reduce the size of the offset storage capacitor. Assuming that the output voltage of the first-stage static amplifier is Vo1 and the input voltage of the second-stage static amplifier is Vi, then due to the voltage division between the offset storage capacitor C1 and the equivalent load capacitance Ceq2 at the gate of the second-stage static amplifier, we can get Vi = C1 / (C1 + Ceq2) * Vo1. In the traditional offset storage circuit, in order to reduce the adverse effects brought by the capacitance voltage division, usually C1 is made much larger than Ceq2, generally C1 is more than ten times that of Ceq2. Therefore, the overly large C1 occupies a very large area on the layout, increasing the production cost. In the static amplifier of the present invention, by increasing the MOS capacitor, the capacitance value of Ceq2 is greatly reduced, thereby the capacitance value of the offset storage capacitor C1 can also be greatly reduced, saving the layout area and reducing the production cost. At the same time, since the load capacitance of the first-stage static amplifier is significantly reduced, the static current consumed by it can also be significantly reduced, saving the static power consumption.
[0026] Figure 4It is the improved "double-tail type" dynamic voltage comparator latch proposed by the present invention, including MOS transistors M18 - M31. Among them, NMOS transistors M19 and M20 are input pair transistors. The sources (S) of NMOS transistors M19 and M20 are connected together and connected to the drain (D) of NMOS transistor M18. PMOS transistors M22 and M23 are the cross-coupled structures described above and will not be elaborated here. The gates (G) of PMOS transistors M21 and M23 are both connected to the clock CLK, and the drains are respectively connected to nodes fn and fp, that is, connected to the gates of M23 and M22 respectively. PMOS transistor M29 and NMOS transistor M27 form inverter one, and PMOS transistor M30 and NMOS transistor M28 also form inverter two. These two inverters are connected end to end to form a latch. The drain of PMOS transistor M31 is connected to the sources of M29 and M30, and the gate is connected to the inverted clock CLKN. The gates of NMOS transistors M25 and M26 are respectively connected to nodes fn and fp, and the drains of M25 and M26 are respectively connected to the inputs of inverter one and inverter two. Vip and Vin represent the input signals of this stage. In the traditional "double-tail type" dynamic comparator, the PMOS transistors at M22 and M33 are controlled by the clock. Therefore, during the comparison process, only the following input pair transistors discharge the fn and fp nodes under the action of the input voltage. In the improved dynamic comparator proposed by the present invention, M22 and M23 are used to form a cross-coupled structure as the load of M19 and M20. When the dynamic comparator is turned off (CLK is at a low level), the fn and fp nodes are charged to VDD by M21 and M24. During normal operation, M19 and M20 discharge the fn and fp nodes. As long as the voltage of one of the nodes is less than VDD + Vthp (Vthp is the threshold voltage of the PMOS and is negative), M22 and M23 can start to work normally. At this time, M18 ~ M23 is equivalent to a static amplifier. Therefore, compared with the traditional "double-tail type" dynamic amplifier, its response speed is further improved.
[0027] Adopting the voltage comparator proposed by the present invention can achieve certain improvements in terms of power consumption, speed, and area, greatly reducing the complexity of the circuit structure compared with methods such as using calibration algorithms and trimming means. In addition, through the combination of the improved dynamic comparator and the preamplifier, it can quickly amplify small input signals and avoid the influence of the noise and offset of the dynamic comparator. Therefore, it can also be used as a comparator in high-precision ADCs.
[0028] It will be understood that the present invention is described by way of some embodiments, and those skilled in the art will be aware that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Additionally, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the scope protected by the present invention.
Claims
1. A low-power, high-speed, high-precision comparator, comprising a preamplifier, an improved "double-tail" dynamic comparator latch, an offset storage capacitor C1 and switches S1-S3, characterized in that: The preamplifier includes a first-stage static amplifier opm1 and a second-stage static amplifier opm2, wherein vip and vin are differential voltage input signals of the comparator, VCM is the common-mode voltage connected to the input terminal of the comparator when offset storage is performed, one of the two switches S1 connects the common-mode voltage VCM and the positive input terminal of the first-stage static amplifier opm1, and the other switch S1 connects the common-mode voltage VCM and the negative input terminal of the first-stage static amplifier opm1; one of the two switches S2 connects the positive input terminal and the negative output terminal of the second-stage static amplifier opm2, and the other S2 switch connects the negative input terminal and the positive output terminal of the second-stage static amplifier opm2, and one end of the two switches S2 is also connected to the positive input terminal and the negative input terminal of the dynamic comparator latch respectively; one of the two switches S3 connects the input signal Vip and the first-stage static amplifier op m1, another switch S3 connects the input signal Vin and the negative input of the first-stage static amplifier opm1; one of the two offset storage capacitors C1 is connected to the negative output of the first-stage static amplifier opm1 and the positive input of the second-stage static amplifier opm2, and the other offset storage capacitor C1 is connected to the positive output of the first-stage static amplifier opm1 and the negative input of the second-stage static amplifier opm2; CLK_latch is the control signal for the normal operation of the dynamic comparator latch, out is the dynamic comparator latch output signal port, and it is also the signal output port of the entire comparator.
2. The low-power, high-speed and high-precision comparator according to claim 1, characterized in that: After the ADC is powered on normally, the offset voltage elimination process of the preamplifier is first performed. In this process, switches S1~S2 are closed and S3 is opened. The first-stage static amplifier opm1 adopts the output offset storage technology OOS, and the second-stage static amplifier opm2 adopts the input offset storage technology IOS to prevent the output saturation of the entire preamplifier. In the above switching state, the offset voltages of the first-stage static amplifier opm1 and the second-stage static amplifier opm2 are stored on the capacitor C1.
3. The low-power, high-speed and high-precision comparator according to claim 1, characterized in that: The first-stage static amplifier opm1 is an amplifier with a current source and a diode-connected MOS as a load, including MOS tubes M1-M6, wherein M1 is a tail current source, M2 and M3 are input differential pair tubes, M4 and M5 are diode-connected loads, and M3 and M6 are current source loads; wherein the sources of the PMOS tubes M3, M4, M5 and M6 are connected together and also connected to the power supply voltage VDD, the gate and drain of the PMOS tube M4 are connected to each other and are also connected to the drain of the PMOS tube M3 and the drain of the NMOS tube M2; the gate and drain of the PMOS tube M5 are connected to each other and are also connected to the drain of the PMOS tube M6 and the drain of the NMOS tube M3; the gates of the NMOS tubes M2 and M3 are respectively connected to the positive and negative input signals of this stage, and the source ends are connected together and are also connected to the drain of the NMOS tube M1; BP is the gate bias voltage of the PMOS tubes M3 and M6, BIAS1 is the gate bias voltage of the NMOS tube M1; Vip and Vin are the input signals of this stage.
4. The low-power, high-speed and high-precision comparator according to claim 1, characterized in that: The second-stage static amplifier opm2 includes MOS tubes M7 to M17, wherein M7 is a tail current source tube, M8 and M9 are input pair tubes, M14 and M17 are MOS tubes connected by diodes as loads, and M15 and M16 are cross-coupled MOS tubes; wherein the gates and drains of the PMOS tubes M14 and M17 are short-circuited together; the gate of the PMOS tube M15 is connected to the drain of the PMOS tube M16, and the gate of the PMOS tube M16 is connected to the drain of the PMOS tube M15 to form a cross-coupled structure and are respectively connected to the drains of the PMOS tubes M14 and M17 with gates and drains short-circuited, and the sources of the PMOS tubes M14, M15, M16 and M17 are connected together and connected to VDD; the source, drain and The substrates are short-circuited together and the gate is used alone as the other end to form a two-terminal device. The connection methods of the PMOS tubes M11, M12, and M13 are exactly the same as those of M10. M10 and M11 are connected end to end to form a new two-port structure, one end of which is connected to the gate of the NMOS tube M8 and the other end is connected to the drain of M16 and the drain of the NMOS tube M9; the structure formed by M12 and M13 is exactly the same as that formed by M10 and M11, one end of which is connected to the gate of the NMOS tube M9 and the other end is connected to the drain of M15 and the drain of the NMOS tube M8; the sources of the NMOS tubes M8 and M9 are connected together and connected to the drain of the NMOS tube M7, and BIAS2 is the gate bias voltage of M7; Vip and Vin in the figure represent the input signals of this stage.
5. The low-power, high-speed and high-precision comparator according to claim 1, characterized in that: The equivalent load capacitance of the input pair tubes M2 and M3 on the gate is Ceq1 = Cgs1+(1+A1)*Cgd1, where the subscript "1" only refers to the first-stage static amplifier opm1. From the above expression, it can be seen that due to the "Maitreya effect" of the capacitor, the parasitic capacitance Cgd1 between the gate and drain of the input pair tubes M2 and M3 is amplified by 1+A1 times, where A1 is the gain of the first-stage static amplifier, and Cgs1 is the parasitic capacitance of the gate and source of the M2 tube. However, since the equivalent gate capacitance of the input tube of the first-stage static amplifier is driven by the capacitive digital-to-analog converter of the previous stage, the equivalent gate capacitance of the input tube of the first-stage static amplifier does not directly affect the speed of the entire pre-static amplifier, but the gate equivalent capacitance of the input tube in the second-stage static amplifier directly affects the response speed of the entire pre-amplifier.
6. The low-power, high-speed and high-precision comparator according to claim 4, characterized in that: M10~M13 are MOS capacitors with source, drain and substrate segments short-circuited together. M10 and M11 as well as M12 and M13 are connected end to end respectively. This MOS capacitor connected end to end ensures that a certain capacitance value can be maintained when the voltage difference between the two ends is close to 0. The MOS capacitor formed by M10 and M11 is connected to the gate of M8 at one end and to the drain of M9 at the other end. When amplifying small signals, the small signal gain from the gate of M8 to the drain of M9 is amplified by A2 times in phase. Here A2 is the gain of the second-stage static amplifier. Therefore, the equivalent load capacitance of the input to the gate of the tube at the second-stage static amplifier is Ceq2=Cgs2+(1+A2)*Cgd2+(1-A2)*Cp. Here Cp is the MOS capacitance value formed by M10 and M11, Cgs2 is the parasitic capacitance of the gate and source of M8 tube, and Cgd2 is the parasitic capacitance of the gate and drain of M8 tube.
7. The low-power, high-speed, high-precision comparator according to claim 6, characterized in that: By increasing the MOS capacitor, the equivalent load capacitance of the input to the gate of the tube is reduced. In the actual circuit design process, the size of the MOS capacitor is carefully adjusted through simulation to achieve the best capacitance elimination effect.
8. The low-power, high-speed, high-precision comparator according to claim 1, characterized in that: The "double-tail" dynamic voltage comparator latch includes MOS tubes M18-M31, wherein NMOS tubes M19 and M20 are input pairs, the sources of NMOS tubes M19 and M20 are connected and connected to the drain of NMOS tube M18, and PMOS tubes M22 and M23 are cross-coupled structures; the gates of PMOS tubes M21 and M23 are connected to the clock CLK, and the drains are respectively connected to nodes fn and fp, that is, respectively connected to the gates of M23 and M22; PMOS tube M29 and NMOS tube M27 constitute an inverter. The PMOS tube M30 and the NMOS tube M28 also constitute the inverter 2, and the two inverters are connected end to end to form a latch; the drain of the PMOS tube M31 is connected to the source of M29 and M30, and the gate is connected to the inverted clock CLKN; the gates of the NMOS tubes M25 and M26 are connected to the nodes fn and fp respectively, and the drains of M25 and M26 are connected to the inputs of the inverter 1 and the inverter 2 respectively; Vip and Vin represent the input signals of this stage.
9. The low-power, high-speed and high-precision comparator according to claim 8, characterized in that: When the dynamic comparator is turned off, CLK is at a low level, and the fn and fp nodes are charged to VDD by M21 and M24; during normal operation, M19 and M20 discharge the fn and fp nodes. As long as the voltage of one of the nodes is less than VDD+Vthp, Vthp is the threshold voltage of PMOS and is negative, M22 and M23 can start working normally. At this time, M18~M23 is equivalent to a static amplifier.