Floating tap selection circuit

Abstract

The invention belongs to the technical field of electronics, and relates to a floating tap selection circuit. The floating tap selection circuit comprises an adder, a comparator, n D triggers, a selector and an adjustable gain amplifier unit, wherein n is an integer greater than or equal to 2; the n D triggers respectively carry out sampling at the rising edges of the sampling clocks CK1, CK2,... CKn to obtain to-be-selected data signals L [1], L [2], L [3], L [4],... L [n]; by changing the address signal SEL, the selector selects one path from the n paths of data signals to be selected; the adjustable gain amplifier unit converts the data signal selected by the selector into an analog signal and feeds the analog signal back to the main data path. A trigger working at a low speed is used, and a trigger working at a full speed is not used, so that the power consumption of the circuit is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and particularly to the field of high-speed interface integrated circuits, and relates to a floating tap selection circuit. Background Art

[0002] In high-speed serial communication, the non-ideal characteristics of the channel will cause inter-symbol interference. The high-speed receiver needs to equalize the signal to obtain the correct data. Decision Feedback Equalization (DFE) feeds back the previously judged symbols to the current moment with a certain proportional coefficient to eliminate the postcursor inter-symbol interference without introducing noise. DFE plays an important role in application scenarios such as back-to-back, copper cable, and optical link.

[0003] The floating tap DFE can effectively eliminate the postcursor inter-symbol interference far from the main tap position. Compared with the fixed tap DFE, it can achieve a better equalization effect while saving circuit resources. The floating tap selection circuit stores and floatingly selects the tap data and sends it to the DFE.

[0004] The existing floating tap selection circuit is as Figure 1 shown, and includes an adder 101, a comparator 102, a D flip-flop 103, a selector 104, and an adjustable gain amplifier unit 105. Taking the four-tap floating tap selection circuit as an example, the 4 D flip-flops 103 delay the decision data signal DATA by 1, 2, 3, and 4 UIs (Unit Interval) respectively to obtain the data signals to be selected L[1], L[2], L[3], and L[4]. By changing the address signal SEL[1:0], the selector 104 selects one path from the four paths of data signals to be selected. The adjustable gain amplifier unit 105 converts the data signal into an analog signal and feeds it back to the main data path.

[0005] The schematic diagram of the existing floating tap selection principle is as Figure 2As shown in the figure. At the rising edge 201 of the clock signal CK, DATA sends the data symbol D4 into L[1]. At the rising edge 202 of the clock signal CK, DATA sends the data symbol D3 into L[1], and L[1] sends the data symbol D4 into L[2]. At the rising edge 203 of the clock signal CK, DATA sends the data symbol D2 into L[1], L[1] sends the data symbol D3 into L[2], and L[2] sends the data symbol D4 into L[3]. At the rising edge 204 of the clock signal CK, DATA sends the data symbol D1 into L[1], L[1] sends the data symbol D2 into L[2], L[2] sends the data symbol D3 into L[3], and L[3] sends the data symbol D4 into L[4]. When the data symbol of DATA is D0, the data symbols of L[1], L[2], L[3], and L[4] are D1, D2, D3, and D4 respectively, corresponding to the tap data of POST1, POST2, POST3, and POST4 respectively.

[0006] In the prior art solution, the D flip-flop needs to be triggered once per UI, resulting in high dynamic power consumption of the circuit. In the floating tap DFE with a large floating range, the floating tap selection circuit needs to use a large number of D flip-flops operating at full speed, which will increase the power consumption of the receiver. Summary of the Invention

[0007] In order to reduce the power consumption of the circuit, the present invention proposes a floating tap selection circuit.

[0008] The technical solution adopted by the present invention is as follows:

[0009] A floating tap selection circuit includes an adder, a comparator, n D flip-flops, a selector, and an adjustable gain amplifier unit, where n is an integer greater than or equal to 2; the first input end of the adder is connected to an input signal, and the output end of the adder is connected to the input end of the comparator; the input ends of the n D flip-flops are connected to the output end of the comparator, and the output ends of the n D flip-flops are connected to the input end of the selector; the input end of the adjustable gain amplifier unit is connected to the output end of the selector, and the output end of the adjustable gain amplifier unit is connected to the second input end of the adder.

[0010] Further, the n D flip-flops sample at the rising edges of the sampling clocks CK1, CK2,..., CKn respectively to obtain the data signals to be selected L[1], L[2], L[3], L[4],..., L[n]; by changing the address signal SEL, the selector selects one path from the n paths of data signals to be selected; the adjustable gain amplifier unit converts the data signal selected by the selector into an analog signal and feeds it back to the main data path.

[0011] A floating tap selection circuit with an m-way interleaving structure includes m floating tap selection circuits. Each floating tap selection circuit includes n D flip-flops, and the D flip-flops of the m floating tap selection circuits are connected to the same selector. The inputs of the m floating tap selection circuits are m decision data signals DATA1, DATA2,..., DATAm. The n D flip-flops of each floating tap selection circuit sample at the rising edge of the sampling clocks CK1, CK2,..., CKn respectively, and the m floating tap selection circuits obtain m * n data signals to be selected. By changing the address signal SEL, the selector selects one or more paths from the m * n data signals to be selected.

[0012] Further, the duty cycle of the sampling clock can be not only 50%, but also any other value.

[0013] Further, the D flip-flop can be a latch (such as an SR latch) or other circuits.

[0014] Further, the number of floating taps of the floating tap selection circuit can be one or more.

[0015] Further, the range of the floating taps of the floating tap selection circuit can start from the first or a larger post-label tap position.

[0016] The beneficial effects of the present invention are as follows:

[0017] A floating tap selection circuit proposed by the present invention uses flip-flops operating at a low speed, avoiding the use of flip-flops operating at full speed and reducing the power consumption of the circuit. Description of the Drawings

[0018] Figure 1 is a floating tap selection circuit of the prior art.

[0019] Figure 2 is a schematic diagram of the floating tap selection principle of the prior art.

[0020] Figure 3 is a floating tap selection circuit proposed by the present invention.

[0021] Figure 4 is a schematic diagram of the floating tap selection principle proposed by the present invention.

[0022] Figure 5 is a floating tap selection circuit proposed by the present invention when applied to an m-way interleaving structure.

[0023] Figure 6 is a schematic diagram of the floating tap selection principle proposed by the present invention when applied to a four-way interleaving structure.

[0024] Description of the Main Component Symbols:

[0025] 100: Prior art floating tap selection circuit

[0026] 101, 301: Adder

[0027] 102, 302: Comparator

[0028] 103, 303, 501: D flip-flop

[0029] 104, 304, 502: Selector

[0030] 105, 305: Tunable gain amplifier unit

[0031] 201, 202, 203, 204, 401, 402, 403, 404: Rising clock edge

[0032] 300: A floating tap selection circuit proposed by the present invention

[0033] 500: A four-channel time-interleaved floating tap selection circuit proposed by the present invention

[0034] CK: Full-speed clock signal

[0035] CK1, CK2,... CKn: Clock signals DIN: Input signal

[0036] DATA, DATA1, DATA2,... DATAm: Decision data signals

[0037] L[1], L[2], L[3], L[4], L[5], L[6], L[7], L[8], L[9], L

[10] , L

[11] , L

[12] , L

[13] , L

[14] , L

[15] , L

[16] , L

[17] , L

[18] , L

[19] : Data signals to be selected

[0038] SEL[1:0], SEL: Address signals

[0039] D8, D7, D6, D5, D4, D3, D2, D1, D0: Data symbols Detailed implementation manners

[0040] In combination with the accompanying drawings, the present invention will be further described below.

[0041] The present invention proposes a floating tap selection circuit, as Figure 3As shown in the figure, it consists of an adder 301, a comparator 302, a D flip-flop 303, a selector 304, and an adjustable gain amplifier unit 305. Let the number of taps, that is, the number of D flip-flops, be n, where n is an integer greater than or equal to 2. Then the connection relationships of each part are as follows: The first input terminal of the adder 301 is connected to the input signal DIN, and the output terminal is connected to the input terminal of the comparator 302; the input terminals of n D flip-flops 303 are connected to the output terminal DATA of the comparator 302 and sample at the rising edges of the sampling clocks CK1, CK2, …… CKn respectively to obtain the data signals to be selected L[1], L[2], L[3], L[4], …… L[n]. The output terminals of n D flip-flops 303 are connected to the input terminals of the selector 304. By changing the address signal SEL, the selector 304 selects one path from n paths of data signals to be selected. The input terminal of the adjustable gain amplifier unit 305 is connected to the output terminal of the selector 304. The adjustable gain amplifier unit 305 converts the data signal selected by the selector 304 into an analog signal and feeds it back to the main data path, and the output terminal of the adjustable gain amplifier unit 305 is connected to the second input terminal of the adder 301.

[0042] Taking the four-tap floating tap selection circuit as an example, 4 D flip-flops 303 sample and judge the data signal DATA at the rising edges of the sampling clocks CK1, CK2, CK3, and CK4 respectively to obtain the data signals to be selected L[1], L[2], L[3], and L[4]. By changing the address signal SEL, the selector 304 selects one path from the four paths of data signals to be selected. The adjustable gain amplifier unit 305 converts the data signal into an analog signal and feeds it back to the main data path.

[0043] A schematic diagram of the floating tap selection principle proposed by the present invention is as Figure 4 shown. CK1, CK2, CK3, and CK4 are four-phase quarter-rate clock signals, with a clock period of 4UI for all, and a phase difference of 1UI between adjacent two-phase clocks. At the rising edge 401 of the clock signal CK1, DATA sends the data symbol D4 into L[4]. At the rising edge 402 of the clock signal CK2, DATA sends the data symbol D3 into L[3]. At the rising edge 403 of the clock signal CK3, DATA sends the data symbol D2 into L[2]. At the rising edge 404 of the clock signal CK4, DATA sends the data symbol D1 into L[1]. When the data symbol of DATA is D0, the data symbols of L[1], L[2], L[3], and L[4] are D1, D2, D3, and D4 respectively, corresponding to the data of the 1st, 2nd, 3rd, and 4th post-label taps.

[0044] When applied to a four-way interleaved structure, a floating tap selection circuit proposed by the present invention includes a D flip-flop 501 and a selector 502. Taking a four-way time-interleaved sixteen-tap floating tap selection circuit as an example, 4 D flip-flops 501 sample the decision data signal DATA1 of the first path at the rising edges of the sampling clocks CK1, CK2, CK3, and CK4 respectively, to obtain the data signals to be selected L[4], L[8], L

[12] , and L

[16] . Similarly, sampling the decision data signal DATA2 of the second path obtains L[5], L[9], L

[13] , and L

[17] , sampling the decision data signal DATA3 of the third path obtains L[6], L

[10] , L

[14] , and L

[18] , and sampling the decision data signal DATA4 of the fourth path obtains L[7], L

[11] , L

[15] , and L

[19] . By changing the address signal SEL, the selector 502 selects one or more paths from the sixteen data signals to be selected.

[0045] Correspondingly, when applied to an m-way interleaved structure, where m is an integer greater than or equal to 2, a floating tap selection circuit proposed by the present invention is as Figure 5 shown, and includes a D flip-flop 501 and a selector 502. DATA1, DATA2,..., DATAm are m decision data signals, which are respectively connected to the floating tap selection circuits of m paths. Taking the first path as an example, n D flip-flops 501 sample at the rising edges of the sampling clocks CK1, CK2,..., CKn respectively, to obtain the data signals to be selected L[m], L[2*m],..., L[n*m]. The data of m paths altogether obtain m*n data signals to be selected from L[m] to L[m*(n + 1)-1]. By changing the address signal SEL, the selector 502 selects one or more paths from the m*n data signals to be selected.

[0046] Figure 6When applied to a four-way interleaving structure, the following is a schematic diagram of the floating tap selection principle proposed by the present invention. CK1, CK2, CK3, and CK4 are four-phase one-sixteenth rate clock signals, each with a clock period of 16 UI and a phase difference of 4 UI between adjacent phases. At the rising edge 601 of the clock signal CK1, DATA1 sends the data symbol D16 to L

[16] . At the rising edge 602 of the clock signal CK2, DATA1 sends the data symbol D12 to L

[12] . At the rising edge 603 of the clock signal CK3, DATA1 sends the data symbol D8 to L[8]. At the rising edge 604 of the clock signal CK4, DATA1 sends the data symbol D4 to L[4]. When the data symbol of DATA1 is D0, the data symbols of L[4], L[8], L

[12] , and L

[16] are D4, D8, D12, and D16 respectively, corresponding to the tap data of the 4th, 8th, 12th, and 16th post-labeled taps. Similarly, for the other three paths, the data symbols of L[4] to L

[19] are D4 to D19, corresponding to the data of the 4th to 19th post-labeled taps respectively.

[0047] Correspondingly, when applied to an m-way interleaving structure, the floating tap selection principle proposed by the present invention is: taking the first path as an example, when the data symbol of DATA1 is D0, the data symbols of L[m], L[2*m], …… L[n*m] correspond to the data of the mth, 2*mth, …… n*mth post-labeled taps respectively. Similarly, for the remaining m - 1 paths. It can correspond to the data of the mth to m*(n + 1) - 1th post-labeled taps.

[0048] Furthermore, the duty cycle of the sampling clock can be not only 50%, but also any other value.

[0049] Furthermore, the D flip-flop 501 can be a latch (such as an SR latch) or other circuits.

[0050] The above four-way interleaving floating tap selection circuit is a variant of the floating tap selection circuit proposed by the present invention when applied to a four-way interleaving structure. Based on the same principle, a floating tap selection circuit proposed by the present invention can also be extended to more interleaving channels, such as an eight-way interleaving structure, a sixteen-way interleaving structure, etc.

[0051] The specific embodiments of the present invention disclosed above are intended to help understand the content of the present invention and implement it accordingly. Those of ordinary skill in the art can understand that various substitutions, changes, and modifications are possible without departing from the spirit and scope of the present invention. The present invention should not be limited to the content disclosed in the embodiments of this specification, and the protection scope of the present invention shall be defined by the scope defined in the claims.

Claims

1. A floating tap selection circuit, characterized in that: The invention comprises an adder, a comparator, n D flip-flops, a selector and an adjustable gain amplifier unit, wherein n is an integer greater than or equal to 2; the first input end of the adder is connected to an input signal, and the output end of the adder is connected to an input end of the comparator; the input ends of the n D flip-flops are connected to the output ends of the comparator, and the output ends of the n D flip-flops are connected to the input end of the selector; the input end of the adjustable gain amplifier unit is connected to the output end of the selector, and the output end of the adjustable gain amplifier unit is connected to the second input end of the adder.

2. The floating tap selection circuit according to claim 1, characterized in that: The n D flip-flops sample at the rising edges of the sampling clocks CK1, CK2, ... CKn, respectively, to obtain the data signals to be selected L[1], L[2], L[3], L[4], ... L[n]; by changing the address signal SEL, the selector selects one path from the n data signals to be selected; the adjustable gain amplifier unit converts the data signal selected by the selector into an analog signal and feeds it back to the main data path.

3. The floating tap selection circuit according to claim 1, characterized in that: The duty cycle of the sampling clock is 50% or other arbitrary values.

4. The floating tap selection circuit according to claim 1, characterized in that: The floating tap selection circuit has one or more floating taps.

5. The floating tap selection circuit according to claim 1, characterized in that: The floating tap range of the floating tap selection circuit starts from the first or greater post-marked tap position.

6. A floating tap selection circuit with an m-way interleaved structure, characterized in that: The invention comprises m-way floating tap selection circuits, each of which comprises n D flip-flops, and the D flip-flops of the m-way floating tap selection circuits are connected to the same selector; the input of the m-way floating tap selection circuits is m-way judgment data signals DATA1, DATA2, ... DATAm; the n D flip-flops of each floating tap selection circuit are sampled at the rising edge of the sampling clocks CK1, CK2, ... CKn respectively, and the m-way floating tap selection circuits obtain m*n-way data signals to be selected; by changing the address signal SEL, the selector selects one or more ways from the m*n-way data signals to be selected.

7. The floating tap selection circuit according to claim 6, characterized in that: The duty cycle of the sampling clock is 50% or other arbitrary values.

8. The floating tap selection circuit according to claim 6, characterized in that: The floating tap selection circuit has one or more floating taps.

9. The floating tap selection circuit according to claim 6, characterized in that: The floating tap range of the floating tap selection circuit starts from the first or greater post-marked tap position.

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