Printed circuit board and method for manufacturing printed circuit board

Abstract

The invention provides a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a first insulating layer; the first wiring layer is embedded in the first insulating layer; the first solder mask layer is located on the first insulating layer; and a cavity formed through the first solder resist layer in a height direction and through a portion of the first insulating layer, in which a second depth of an edge portion of the cavity in the height direction may be greater than a first depth of a center portion of the cavity in the height direction.

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board and a method of manufacturing the printed circuit board. Background Art

[0002] A printed circuit board has a circuit pattern formed of a conductive material (such as copper) on an insulating material. As electronic devices (including mobile phones) in the information technology (IT) field have become smaller, a method of forming a cavity in a printed circuit board and mounting an electronic component (such as an IC (integrated circuit), an active element, or a passive element) in the cavity has been proposed.

[0003] The deeper the cavity of the printed circuit board, the more parts of the electronic component can be mounted in the cavity. The wider the cavity, the larger the bonding surface area between the molding material that fills the cavity and fixes the electronic component and the cavity. Therefore, the adhesion of the molding material can be increased, and when injecting the molding material, the molding material can be easily moved and voids and the like can be prevented.

[0004] However, when the cavity is made wider, the area occupied by the wiring formed in the printed circuit board may become narrower. Summary of the Invention

[0005] The present disclosure provides a printed circuit board and a method of manufacturing the same. The printed circuit board includes a cavity having a sufficient area in which an electronic component can be mounted, and the molding characteristics can be improved by increasing the bonding surface area between the molding material and the cavity.

[0006] However, the problems to be solved by the embodiments are not limited to the above problems, and various extensions can be made within the scope of the technical concept included in the present disclosure.

[0007] According to some embodiments of the present disclosure, a printed circuit board may include: a first insulating layer; a first wiring layer embedded in the first insulating layer; a first solder resist layer located on the first insulating layer; and a cavity penetrating the first solder resist layer along a height direction and penetrating a part of the first insulating layer, wherein a first depth of a central portion of the cavity along the height direction may be less than a second depth of an edge portion of the cavity along the height direction.

[0008] The cavity may include a first part in the part of the first insulating layer, a second part in the edge portion of the cavity, and a third part in the first solder resist layer.

[0009] A corner portion where a side wall and a bottom surface of the second part of the cavity intersect may have a rounded shape.

[0010] Side walls of the first part and the second part may be aligned with each other along the height direction.

[0011] The width of the first part in the planar direction, the width of the second part in the planar direction, and the width of the third part in the planar direction may be different from each other, and the planar direction is perpendicular to the height direction.

[0012] The width of the second part may be less than the width of the first part and the width of the third part.

[0013] The width of the third part may be greater than the width of the first part.

[0014] The printed circuit board may further include: a first via hole located in a first via hole in the first insulating layer and connected to the first wiring layer, wherein the depth of the first part may be substantially equal to the first thickness of the first wiring layer, and the depth of the second part may be less than the second thickness of the first via hole.

[0015] The depth of the third part may be substantially equal to the third thickness of the first solder mask layer.

[0016] According to another embodiment of the present disclosure, a method of manufacturing a printed circuit board may include: forming a first wiring layer and a first sacrificial layer; stacking a first insulating layer on the first wiring layer and the first sacrificial layer, the first insulating layer burying the first wiring layer and the first sacrificial layer therein; forming a first via hole in the first insulating layer that overlaps with the first wiring layer; forming a first via hole in the first via hole of the first insulating layer; removing the first sacrificial layer by a first etching to form a preliminary cavity; and removing a part of the side wall and the bottom of the edge portion of the preliminary cavity by a second etching to form a cavity, in which the depth of the central portion of the cavity in the height direction may be less than the depth of the edge portion of the cavity in the height direction.

[0017] The manufacturing method may further include forming a solder mask layer on the first insulating layer, the solder mask layer having an opening exposing the preliminary cavity.

[0018] According to some embodiments of the present disclosure, a printed circuit board and a method of manufacturing the same may be provided, the printed circuit board including a cavity having a sufficient area in which an electronic component can be mounted, and the molding characteristics can be improved by increasing the bonding surface area between the molding material and the cavity.

[0019] However, it is easy to understand that the effects of the embodiments are not limited to the above effects, and various expansions can be made without departing from the spirit and scope of the present disclosure. Description of the Drawings

[0020] Figure 1 is a cross-sectional view of a printed circuit board according to an embodiment.

[0021] Figure 2 It is an enlarged view of a part of a printed circuit board according to an embodiment.

[0022] Figures 3 to 13 It is a cross-sectional view of a method for manufacturing a printed circuit board according to an embodiment.

[0023] Figure 14 It is a schematic cross-sectional view of a semiconductor device including a printed circuit board according to an embodiment. Detailed Description of Embodiments

[0024] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily practice the present disclosure. However, the present disclosure can be implemented in various different forms and is not limited to the embodiments provided herein.

[0025] Parts irrelevant to the description will be omitted to describe some embodiments of the present disclosure in an easy-to-understand manner, and the same components will be denoted by the same reference numerals throughout the specification.

[0026] In addition, it should be understood that the accompanying drawings are provided only to allow for easy understanding of the embodiments of the present disclosure, and the spirit of the present disclosure is not limited by the drawings but includes all modifications, equivalents, and alternatives included in the spirit and scope of the present disclosure.

[0027] In addition, for ease of description, the dimensions (e.g., thickness) of each component in the drawings are arbitrarily shown, and the present disclosure does not necessarily have to be limited to the shown dimensions (e.g., thickness). In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In addition, in the drawings, the thicknesses of some layers and regions are exaggerated for ease of explanation.

[0028] In addition, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be an intermediate element. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. In addition, when an element is referred to as being "on" a reference element, it can be positioned on or below the reference element and is not necessarily positioned on the reference element in the direction opposite to the direction of gravity.

[0029] In addition, unless explicitly described to the contrary, the word "comprising" and variations such as "comprises" or "containing" will be understood to imply including the stated elements but not excluding any other elements.

[0030] In addition, throughout the specification, the word "planar view" refers to a view when observing an object from the top, and the word "cross-sectional view" refers to a view when observing a cross-section of an object taken vertically from the side.

[0031] In addition, throughout the specification, when referred to as "connected", this not only means that two or more components can be directly connected, but also means that two or more components can be indirectly connected through another component, two or more components are physically and / or electrically connected, or two or more components are referred to by different names according to their positions or functions, but are integrated.

[0032] Hereinafter, various embodiments and modifications will be described in detail with reference to the accompanying drawings.

[0033] Referring to Figure 1 and Figure 2 , a printed circuit board according to an embodiment will be described. Figure 1 is a cross-sectional view of a printed circuit board according to an embodiment. Figure 2 is an enlarged view of a part of a printed circuit board according to an embodiment.

[0034] Referring to Figure 1 , the printed circuit board 100 according to the present embodiment may include: a plurality of stacked insulating layers IL; a plurality of vias MV located in a plurality of via holes VA of a plurality of wiring layers ML buried in the plurality of insulating layers IL; a plurality of pad layers MP; a solder resist layer PL; and a cavity CV formed in a part of the plurality of insulating layers IL.

[0035] The plurality of insulating layers IL may include a first insulating layer IL1 and a second insulating layer IL2 located below the first insulating layer IL1 along the height direction DRH.

[0036] The plurality of wiring layers ML may include: a first wiring layer ML1 buried in the first insulating layer IL1; and a second wiring layer ML2 and a third wiring layer ML22 buried in the second insulating layer IL2.

[0037] The plurality of vias MV may include: a first via MV1 located in a first via hole VA1 formed in the first insulating layer IL1; a second via MV2 located in a second via hole VA2 formed in the second insulating layer IL2; and a third via MV22 located in a third via hole VA22 formed in the second insulating layer IL2.

[0038] The plurality of pad layers MP may include: a first pad layer MP1 located on the first insulating layer IL1 along the height direction DRH; and a second pad layer MP2 and a third pad layer MP3 located below the second insulating layer IL2 along the height direction DRH.

[0039] A part of the first wiring layer ML1 and a part of the second wiring layer ML2 can be connected through the first via MV1, and a part of the second wiring layer ML2 and a part of the second pad layer MP2 can be connected through the second via MV2. Thus, the first pad layer MP1 can be connected to the first wiring layer ML1. Additionally, a part of the third wiring layer ML22 and a part of the third pad layer MP3 can be connected to each other through the third via MV22.

[0040] The solder mask layer PL can include: a first solder mask layer PL1, located on the first insulating layer IL1 and exposing a part of the first pad layer MP1 through the second opening OP2; and a second solder mask layer PL2, located below the second insulating layer IL2 and exposing a part of the second pad layer MP2 through the third opening OP3A and exposing a part of the third pad layer MP3 through the fourth opening OP3B.

[0041] The cavity CV can include: a first part CV1 and a second part CV2, formed in the first insulating layer IL1 and having different widths and heights; and a third part CV3, formed in the first solder mask layer PL1.

[0042] The first part CV1 of the cavity CV is located at the side surface of the first wiring layer ML1, the second part CV2 of the cavity CV is located at the side surface of the first via MV1, and the third part CV3 of the cavity CV is located at the side surface of the first solder mask layer PL1.

[0043] Along the height direction DRH, the first part CV1 of the cavity CV can be located above the second part CV2 of the cavity CV, and the third part CV3 of the cavity CV can be located above the first part CV1 of the cavity CV.

[0044] Along the plane direction DRW perpendicular to the height direction DRH, the second part CV2 of the cavity CV can be located at the edge of the bottom surface of the cavity CV.

[0045] Along the height direction DRH, the depth of the first part CV1 of the cavity CV can be substantially equal to the first thickness D1 of the first wiring layer ML1 embedded in the first insulating layer IL1, the depth of the second part CV2 of the cavity CV can be less than the second thickness D2 of the first via MV1 located in the first via hole VA1 formed in the first insulating layer IL1, and the depth of the third part CV3 of the cavity CV can be substantially equal to the third thickness D3 of the first solder mask layer PL1.

[0046] Along the height direction DRH, the central portion of the cavity CV may include a part of the first portion CV1 and a part of the third portion CV3. The central portion of the cavity CV may have a first depth H1, and the first depth H1 may be the sum of the first thickness D1 and the third thickness D3. The edge portion of the cavity CV may include another part of the first portion CV1, another part of the third portion CV3, and the second portion CV2, and the edge portion of the cavity CV may have a second depth H2. The second depth H2 may be the sum of the first thickness D1, a part of the second thickness D2 (corresponding to the height difference HD described later), and the third thickness D3. The second depth H2 may be greater than the first depth H1.

[0047] Referring Figure 1 and Figure 2 , as described above, along the height direction DRH, the central portion of the cavity CV may include a part of the first portion CV1 and a part of the third portion CV3. The central portion of the cavity CV may have a first depth H1, and the edge portion of the cavity CV may include another part of the first portion CV1, another part of the third portion CV3, and the second portion CV2. The edge portion of the cavity CV may have a second depth H2. The second depth H2 may be greater than the first depth H1. Therefore, there may be a height difference HD between the bottom surface of the central portion of the cavity CV and the bottom surface of the edge portion of the cavity CV.

[0048] Along the plane direction DRW perpendicular to the height direction DRH, the first portion CV1 of the cavity CV formed in the first insulating layer IL1 may have a first width W1, the second portion CV2 of the cavity CV formed in the first insulating layer IL1 may have a second width W2, and the third portion CV3 of the cavity CV formed in a part of the first solder resist layer PL1 may have a third width W3.

[0049] The first width W1 of the first portion CV1 of the cavity CV may be different from the second width W2 of the second portion CV2 of the cavity CV. The first width W1 of the first portion CV1 of the cavity CV may be greater than the second width W2 of the second portion CV2 of the cavity CV.

[0050] The second portion CV2 of the cavity CV may be stacked with the first portion CV1 of the cavity CV along the height direction DRH.

[0051] The third width W3 of the third portion CV3 of the cavity CV may be greater than the first width W1 of the first portion CV1 of the cavity CV.

[0052] The side walls of the first portion CV1 and the second portion CV2 of the cavity CV may be aligned along the height direction DRH.

[0053] The printed circuit board according to some embodiments of the present disclosure may further include a second portion CV2 of the cavity CV, which is formed in a part of the first insulating layer IL1, at the edge of the bottom of the cavity CV, and has a depth greater than the depth of the first portion CV1 of the cavity CV (e.g., referring to Figure 1 , the bottom surface of the second portion CV2 of the cavity CV is lower than the bottom surface of the first portion CV1), so as to maintain a sufficient bottom surface on which electronic components can be mounted and increase the surface area of the bottom of the cavity CV. Therefore, during the manufacturing process, the molding characteristics can be improved by increasing the bonding surface area between the molding material injected into the cavity CV and the cavity, and when injecting the molding material, it is easy to move the molding material to the edge portion of the cavity, and the occurrence of voids and the like can be prevented.

[0054] Referring to Figure 2 , according to some embodiments of the present disclosure, the bottom of the second portion CV2 of the cavity CV located at the edge of the bottom surface of the cavity CV may include a corner portion CP, and the corner portion CP has a curved and rounded shape at the portion connected to the side wall of the cavity CV. When the corner where the side wall of the cavity CV intersects the bottom does not have a curved form, when injecting the molding material into the cavity, the molding material is not filled into the corner of the cavity, so defects such as voids may be caused. However, according to some embodiments of the present disclosure, the corner portion CP where the bottom surface of the second portion CV2 of the cavity CV located at the edge of the bottom surface of the cavity CV intersects the side wall has a curved and rounded shape, so the molding material can be well filled into the corner portion, thereby preventing the occurrence of defects such as voids.

[0055] According to an embodiment, the first portion CV1 of the cavity CV is located in a part of the first insulating layer IL1, but according to another embodiment, in addition to the first insulating layer IL1, the first portion CV1 of the cavity CV may also be formed within an additional insulating layer.

[0056] Reference will be made to Figures 3 to 13 and Figure 1 to describe a method of manufacturing a printed circuit board according to some embodiments. Figures 3 to 13 is a cross-sectional view showing a method of manufacturing a printed circuit board according to an embodiment.

[0057] Referring to Figure 3 , a first copper foil layer TC1 and a first wiring layer ML1 may be formed on a carrier substrate CS, and the carrier substrate CS includes a core portion CL and thin metal layers MS stacked on both sides of the core portion CL. In this case, a first sacrificial layer SF1 may be formed together at the position where the cavity CV will be formed. Since the first sacrificial layer SF1 is formed together with the first wiring layer ML1, the first sacrificial layer SF1 may be made of the same material as the first wiring layer ML1 and have a thickness substantially equal to the first thickness D1 of the first wiring layer ML1.

[0058] As shown Figure 4 in the figure, a first insulating layer IL1 may be formed on the first wiring layer ML1 and the first sacrificial layer SF1 to bury the first wiring layer ML1 and the first sacrificial layer SF1 with the first insulating layer IL1. A first via hole VA1 stacked with the first wiring layer ML1 may be formed in the first insulating layer IL1. A first via MV1 may be formed in the first via hole VA1. A second wiring layer ML2 stacked with the first via MV1 may be formed on the first insulating layer IL1, and a third wiring layer ML22 may be formed on the first insulating layer IL1.

[0059] Referring to Figure 5 the figure, a second insulating layer IL2 and a second copper foil layer TC2 are formed on the second wiring layer ML2 and the third wiring layer ML22 such that the second wiring layer ML2 and the third wiring layer ML22 are buried in the second insulating layer IL2.

[0060] Referring to Figure 6 the figure, a second via hole VA2 stacked with the second wiring layer ML2 and a third via hole VA22 stacked with the third wiring layer ML22 may be formed in the second insulating layer IL2. A second via MV2 may be formed in the second via hole VA2 and a third via MV22 may be formed in the third via hole VA22. A second pad layer MP2 connected to the second wiring layer ML2 through the second via MV2 and a third pad layer MP3 connected to the third wiring layer ML22 through the third via MV22 may be formed on the second insulating layer IL2.

[0061] Next, as shown Figure 7 in the figure, the substrate portion SUB is peeled off from both sides of the carrier substrate CS.

[0062] Hereinafter, one substrate portion SUB peeled off from the carrier substrate CS will be described.

[0063] As shown Figure 8 in the figure, the first copper foil layer TC1 is removed from the substrate portion SUB, and a first pad layer MP1 is formed on the first wiring layer ML1.

[0064] Referring to Figure 9 the figure, a first solder resist layer PL1 is formed on the first insulating layer IL1, and a second solder resist layer PL2 is formed under the second insulating layer IL2.

[0065] The first solder resist layer PL1 may include a first opening OP1 that completely exposes the first sacrificial layer SF1 and a second opening OP2 that overlaps at least a part of the first pad layer MP1, and the second solder resist layer PL2 may have a third opening OP3A that overlaps the second pad layer MP2 and a fourth opening OP3B that overlaps the third pad layer MP3.

[0066] As shown Figure 10As shown, a first mask layer MSK1 having a fifth opening OP4 is disposed on a first solder resist layer PL1 such that the first mask layer MSK1 covers a second opening OP2 of the first solder resist layer PL1 and exposes a first opening OP1, and a second mask layer MSK2 is disposed below the second solder resist layer PL2 to cover a third opening OP3A and a fourth opening OP3B. The first mask layer MSK1 and the second mask layer MSK2 may cover all parts except for the area where the cavity CV will be formed.

[0067] Using the first mask layer MSK1 and the second mask layer MSK2 as etching masks, a first sacrificial layer SF1 located in the area where the cavity CV will be formed may be subjected to a first etching ET. Thus, as Figure 11 shown, a preliminary cavity CV11 may be formed in the part where the first sacrificial layer SF1 is located.

[0068] Referring to Figure 12 , using the first mask layer MSK1 and the second mask layer MSK2 as etching masks, a part P1 of the sidewall and the bottom at the edge portion of the preliminary cavity CV11 may be removed by a second etching ET1. The second etching ET1 may use a laser, but the embodiment is not limited thereto.

[0069] In Figure 12 , a part P1 of the sidewall and the bottom at the edge portion of the preliminary cavity CV11 to be removed by the second etching ET1 is indicated by a dotted line in an approximate quadrilateral shape.

[0070] By removing the part P1 of the sidewall and the bottom at the edge portion of the preliminary cavity CV11 by the second etching ET1, as Figure 13 shown, a first part CV1 of the cavity CV at the side surface of the first wiring layer ML1 and a second part CV2 of the cavity CV at the side surface of the first via MV1 may be formed.

[0071] As previously referred to Figure 2 described, according to an embodiment, a corner portion CP where the bottom surface and the sidewall of the second part CV2 of the cavity CV intersect may be formed to have a curved and rounded shape.

[0072] The first opening OP1 of the first solder resist layer PL1 that completely exposes the first sacrificial layer SF1 may be a third part CV3 of the cavity CV.

[0073] Thereafter, the first mask layer MSK1 and the second mask layer MSK2 may be removed to form Figure 1 the printed circuit board 100.

[0074] A method of manufacturing a printed circuit board according to the present embodiment includes forming a plurality of first wiring layers ML1 and a first sacrificial layer SF1 to be buried in a first insulating layer IL1, removing the first sacrificial layer SF1 by a first etching ET using mask layers MSK1 and MSK2 as etching masks to form a preliminary cavity CV11, and removing a part P1 of the sidewall and bottom of the edge portion of the preliminary cavity CV11 by a second etching ET1 to form a cavity CV including a second portion CV2. The cavity CV can be formed to have a wider width and a deeper depth than the preliminary cavity CV11 (for example, refer to Figure 13 ), and "deeper depth" may mean that the bottom surface of the second portion CV2 of the cavity CV is lower than the bottom surface of the preliminary cavity CV11). Therefore, by maintaining a sufficient bottom surface on which an electronic component can be mounted and increasing the surface area of the bottom of the cavity CV, when a semiconductor device is formed by mounting an electronic component on the printed circuit board, the molding characteristics can be improved by increasing the bonding surface area between the molding material injected into the cavity CV and the cavity, and when injecting the molding material, the molding material can be easily moved to the edge portion of the cavity and voids can be prevented from occurring.

[0075] In addition, according to some embodiments of the present disclosure, a corner portion CP where the bottom surface and the sidewall of the second portion CV2 of the cavity CV, which is located at the edge of the bottom surface of the cavity CV, intersect can be formed to have a curved and rounded shape. Since the corner portion where the bottom surface and the sidewall intersect is formed to have a curved and rounded shape, the molding material can be well filled into the corner portion, thereby preventing defects such as voids from occurring.

[0076] According to an embodiment, the first sacrificial layer SF1 formed at the position of the preliminary cavity CV11 for forming the cavity CV is formed to be located within at least a part of the first insulating layer IL1. However, according to another embodiment, the first sacrificial layer SF1 formed at the position of the preliminary cavity CV11 to be formed can be additionally formed in an additional insulating layer. In this case, the depth of the first portion CV1 of the cavity CV can become larger.

[0077] Reference will be made to Figure 14 to describe a semiconductor device including a printed circuit board according to some embodiments. Figure 14 is a schematic cross-sectional view of a semiconductor device including a printed circuit board according to an embodiment.

[0078] Referring to Figure 14 , a semiconductor device 1000 according to some embodiments may include a printed circuit board according to the previous reference Figures 1 to 3The printed circuit board 100 of the described embodiment, the opposing substrate SUB1 facing the printed circuit board 100, the mounting piece CHP for electronic components located within the cavity CV of the printed circuit board 100 and electrically connected to the opposing substrate SUB1 via the connecting member SP, and the molding layer MDL, which is located between the printed circuit board 100 and the opposing substrate SUB1 and connects the printed circuit board 100 and the opposing substrate SUB1 to each other.

[0079] For the semiconductor device 1000 according to the present embodiment, the cavity CV of the printed circuit board 100 in which the mounting piece CHP is located may further include a second portion CV2 of the cavity CV, which is formed in a part of the first insulating layer IL1, at the edge of the bottom surface of the cavity CV and has a greater depth than the first portion CV1 of the cavity CV (for example, refer to Figure 14 ,"greater depth" may mean that the bottom surface of the second portion CV2 of the cavity CV is lower than the bottom surface of the first portion CV1), so as to maintain a sufficient bottom surface on which the electronic components can be mounted and increase the surface area of the bottom of the cavity CV. Therefore, during the manufacturing process, the molding characteristics can be improved by increasing the bonding surface area between the molding material injected into the cavity CV and formed into the molding layer MDL and the cavity, and when injecting the molding material, it is easy for the molding material to move to the edge portion of the cavity, and the generation of voids and the like can be prevented.

[0080] In addition, according to the embodiment, the corner portion CP where the side wall and the bottom surface of the second portion CV2 of the cavity CV intersect at the edge of the bottom surface of the cavity CV may be formed to have a curved and rounded shape, so that the molding material can be well filled into the corner portion, thereby preventing the occurrence of defects such as voids.

[0081] Many features of the printed circuit board 100 and the manufacturing method of the printed circuit board according to the embodiment described above are applicable to the semiconductor device 1000 according to the present embodiment.

[0082] Although the preferred embodiments have been described above, the present disclosure is not limited thereto, and the present disclosure can be variously modified within the scope of the claims, the specific embodiments of the present disclosure, and the drawings, and it is natural that various modified schemes also fall within the scope of the present disclosure.

Claims

1. A printed circuit board, comprising: a first insulating layer; a first wiring layer, buried in the first insulating layer; A first solder resist layer, located on the first insulating layer; as well as a cavity penetrating a portion of the first insulating layer and the first solder resist layer along a height direction, Wherein, a depth of a central portion of the cavity along the height direction is smaller than a depth of an edge portion of the cavity along the height direction.

2. The printed circuit board of claim 1, wherein: The cavity includes a first portion in the portion of the first insulating layer, a second portion in the edge portion of the cavity, and a third portion in the first solder resist layer, and A side wall of the first portion and a side wall of the second portion are aligned with each other along the height direction.

3. The printed circuit board according to claim 2, wherein: A corner portion where a side wall and a bottom surface of the second portion of the cavity meet has a rounded shape.

4. The printed circuit board according to claim 2, wherein: A width of the first portion along a planar direction, a width of the second portion along the planar direction, and a width of the third portion along the planar direction are different from each other, the planar direction being perpendicular to the height direction.

5. The printed circuit board according to claim 4, wherein: The width of the second portion is smaller than the width of the first portion and the width of the third portion.

6. The printed circuit board according to claim 5, wherein: The width of the third portion is greater than the width of the first portion.

7. The printed circuit board according to claim 6, further comprising: a first via hole located in a first via hole in the first insulating layer and connected to the first wiring layer, wherein the depth of the central portion of the cavity is equal to a first thickness of the first wiring layer, and A depth of the second portion is less than a second thickness of the first via hole.

8. The printed circuit board according to claim 7, wherein: The depth of the third portion is equal to the third thickness of the first solder resist layer.

9. The printed circuit board according to claim 1, further comprising: a first via hole located in a first via hole in the first insulating layer and connected to the first wiring layer, wherein the cavity includes a first portion in the portion of the first insulating layer, a second portion in the edge portion of the cavity, and a third portion in the first solder resist layer, The depth of the first portion is equal to a first thickness of the first wiring layer, and A depth of the second portion is less than a second thickness of the first via hole.

10. The printed circuit board according to claim 9, wherein The depth of the third portion is equal to the third thickness of the first solder resist layer.

11. A method for manufacturing a printed circuit board, comprising: forming a first wiring layer and a first sacrificial layer; stacking a first insulating layer on the first wiring layer and the first sacrificial layer, wherein the first insulating layer buries the first wiring layer and the first sacrificial layer; forming a first via hole in the first insulating layer to overlap the first wiring layer; forming a first via hole in the first via hole of the first insulating layer; removing the first sacrificial layer by a first etching to form a preliminary cavity; as well as Parts of the sidewalls and the bottom of the edge portion of the preliminary cavity are removed by the second etching to form a cavity in which the depth of the central portion of the cavity along the height direction is smaller than the depth of the edge portion of the cavity along the height direction.

12. The manufacturing method according to claim 11, further comprising: A first solder resist layer is formed on the first insulating layer, the first solder resist layer having an opening exposing the preliminary cavity.

13. The manufacturing method according to claim 12, wherein: The cavity includes a first portion in the first insulating layer, a second portion in the edge portion of the cavity, and a third portion in the first solder resist layer, and By the second etching, the sidewall of the first portion and the sidewall of the second portion are aligned with each other along the height direction.

14. The manufacturing method according to claim 13, wherein: A width of the first portion along a planar direction, a width of the second portion along the planar direction, and a width of the third portion along the planar direction are different from each other, the planar direction being perpendicular to the height direction.

15. The manufacturing method according to claim 14, wherein: The width of the second portion is smaller than the width of the first portion and the width of the third portion.

16. The manufacturing method according to claim 15, wherein: The width of the third portion is greater than the width of the first portion.

17. The manufacturing method according to claim 16, wherein: The depth of the first portion is equal to a first thickness of the first wiring layer, and A depth of the second portion is less than a second thickness of the first via hole.

18. The manufacturing method according to claim 17, wherein: The depth of the third portion is equal to the third thickness of the first solder resist layer.

19. The manufacturing method according to claim 11, further comprising forming a first solder resist layer on the first insulating layer, the first solder resist layer having an opening exposing the preliminary cavity, in, The cavity includes a first portion in the first insulating layer, a second portion in the edge portion of the cavity, and a third portion in the first solder resist layer, the depth of the first portion being equal to a first thickness of the first wiring layer, and A depth of the second portion is less than a second thickness of the first via hole.

20. The manufacturing method according to claim 19, wherein: The depth of the third portion is equal to the third thickness of the first solder resist layer.

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