Semiconductor structure and sense amplifier

Abstract

The invention provides a semiconductor structure, relates to the technical field of semiconductors, and is used for solving the technical problem that the semiconductor structure is easy to break. The semiconductor structure includes an active structure, a first gate structure, and a second gate structure. The active structure comprises a first active region and a second active region which are connected along a first direction, one ends, far away from each other, of the first active region and the second active region are respectively provided with a first concave part and a second concave part, and the first concave part and the second concave part are spaced along the first direction; the thickness of the active structure between the first recess and the second recess along the first direction is increased, and the active structure is not easy to break. The first gate structure is arranged on the first active region, crosses the first concave part and is separated from the end part of the first concave part, and the second gate structure is arranged on the second active region, crosses the second concave part and is separated from the end part of the second concave part, so that extra increase of the channel length of the first gate structure and the second gate structure is avoided; the performance of the semiconductor structure is ensured.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a sense amplifier. Background Art

[0002] With the development of semiconductor technology, semiconductor structures are more and more widely used. Semiconductor structures are applied in memories, especially in dynamic random access memories (DRAMs) to improve the storage density and read / write speed of dynamic random access memories.

[0003] A dynamic random access memory includes a plurality of memory cells, and each memory cell generally includes a transistor and a capacitor. Among them, the gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0004] However, disconnections often occur during the manufacturing process of semiconductor structures, affecting the yield. Summary of the Invention

[0005] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure and a sense amplifier to reduce disconnections and improve the yield.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure, which includes:

[0007] An active structure, the active structure includes a first active region and a second active region connected in a first direction, a first recess is provided at one end of the first active region away from the second active region, a second recess is provided at one end of the second active region away from the first active region, and the first recess and the second recess have a spacing in the first direction;

[0008] A first gate structure and a second gate structure arranged at intervals in the first direction, the first gate structure and the second gate structure both extend in a second direction, the first gate structure is disposed on the first active region, spans the first recess and is spaced from the end of the first recess, the second gate structure is disposed on the second active region, spans the second recess and is spaced from the end of the second recess, and the second direction intersects the first direction.

[0009] In some possible examples, the first active region includes a first connection portion and a plurality of first extension portions provided at one end of the first connection portion, the plurality of first extension portions are arranged at intervals in the second direction, and the first recess is formed between two adjacent first extension portions;

[0010] The second active region includes a second connection portion, and a plurality of second extension portions disposed at one end of the second connection portion. The plurality of second extension portions are arranged at intervals along the second direction, and a second concave portion is formed between two adjacent second extension portions;

[0011] The first connection portion and the second connection portion are in contact with each other.

[0012] In some possible examples, the first extension portion includes a first portion connected to the first connection portion, and a second portion connected to the side of the first portion away from the first connection portion. Along the second direction, the distance between adjacent first portions is greater than the distance between adjacent second portions, and the first gate structure is in contact with the corresponding first portion;

[0013] The second extension portion includes a third portion connected to the second connection portion, and a fourth portion connected to the side of the third portion away from the second connection portion. Along the second direction, the distance between adjacent third portions is greater than the distance between adjacent fourth portions, and the second gate structure is in contact with the corresponding third portion.

[0014] In some possible examples, the first concave portion of the first active region faces the second concave portion of the second active region along the first direction.

[0015] In some possible examples, the first concave portion of the first active region and the second concave portion of the second active region are arranged in a dislocation manner along the second direction.

[0016] In some possible examples, the first concave portion of the first active region faces the second extension portion of the second active region along the first direction, and the second concave portion of the second active region faces the first extension portion of the first active region along the first direction.

[0017] In some possible examples, along the second direction, the width of the first concave portion of the first active region is smaller than the width of the first extension portion of the first active region, and the width of the second concave portion of the second active region is smaller than the width of the extension portion of the second active region.

[0018] In some possible examples, along the second direction, the width of the first concave portion of the first active region is equal to the width of the second concave portion of the second active region;

[0019] And / or, along the second direction, the plurality of first concave portions of the first active region are arranged at equal intervals, and the plurality of second concave portions of the second active region are arranged at equal intervals.

[0020] In some possible examples, along the first direction, the length of the first extension of the first active region is greater than the length of the second extension of the second active region;

[0021] The number of the first gate structures provided on the first active region is greater than the number of the second gate structures provided on the second active region.

[0022] In some possible examples, the range of the spacing between the first recess and the second recess along the first direction is from 10 nm to 50 nm.

[0023] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0024] The semiconductor structure provided by the embodiments of the present disclosure includes an active structure, a first gate structure, and a second gate structure. The active structure includes a first active region and a second active region connected in series along a first direction. A first recess is provided at one end of the first active region away from the second active region, and a second recess is provided at one end of the second active region away from the first active region. The first recess and the second recess have a spacing along the first direction. The connection of the first active region and the second active region increases the thickness of the active structure between the first recess and the second recess along the first direction, and the active structure is not easily disconnected when the first recess and the second recess are formed, thereby improving the yield of the semiconductor structure. The first gate structure and the second gate structure are spaced apart along the first direction and both extend along a second direction. The first gate structure is provided on the first active region, spans across the first recess and is spaced from the end of the first recess, so as to avoid the first gate structure contacting a part of the first active region opposite to the first recess along the second direction, so as to avoid additionally increasing the channel length opposite to the first gate structure and ensuring the performance of the semiconductor structure. The second gate structure is provided on the second active region, spans across the second recess and is spaced from the end of the second recess, so as to avoid the second gate structure contacting a part of the second active region opposite to the second recess along the second direction, so as to avoid additionally increasing the channel length opposite to the second gate structure and ensuring the performance of the semiconductor structure.

[0025] According to some embodiments, the present disclosure further provides a sense amplifier, including an equalization unit, a sense amplification unit, and a column selection unit; wherein, the equalization unit includes the semiconductor structure as described above. Since the sense amplifier includes the above semiconductor structure, it has at least the advantages of not being easily disconnected and having a high yield. For the specific effects, refer to the above, and details are not described herein again. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is the first schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0027] Figure 2 is the second schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0028] Figure 3 The third schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0029] Figure 4 The fourth schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0030] Figure 5 The fifth schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0031] Figure 6 The sixth schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0032] Figure 7 The seventh schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0033] Figure 8 The eighth schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0034] Figure 9 The ninth schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0035] Figure 10 The tenth schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0036] Figure 11 The eleventh schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0037] Figure 12 The twelfth schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0038] Figure 13 The thirteenth schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0039] Figure 14 The fourteenth schematic diagram of the semiconductor structure in an embodiment of the present disclosure;

[0040] Figure 15 The application schematic diagram of the sense amplifier in an embodiment of the present disclosure.

[0041] Explanation of reference numerals:

[0042] 11 - First connection part; 12 - First extension part;

[0043] 13 - First part; 14 - Second part;

[0044] 15 - First recess; 21 - Second connection part;

[0045] 22 - Second extension; 23 - Third part;

[0046] 24 - Fourth part; 25 - Second recess;

[0047] 30 - First gate structure; 40 - Second gate structure;

[0048] 50 - Bit line; 60 - Complementary bit line;

[0049] 70 - Equalization unit; 71 - Third signal terminal;

[0050] 72 - Fourth signal terminal; 80 - Sense amplifier unit;

[0051] 81 - First signal terminal; 82 - Second signal terminal;

[0052] 90 - Column selection unit; 91 - Fifth signal terminal;

[0053] 100 - Semiconductor structure. Detailed implementation mode

[0054] In the related art, there is a problem that the semiconductor structure is prone to disconnection. After research by the inventor, it is found that the reason is that the semiconductor structure has recesses, which will reduce the size of the semiconductor structure. During the formation of the recesses, the bottom of the recesses is easily etched through, causing the semiconductor structure to disconnect. Especially as the semiconductor size is scaled down, the bottom of the recesses is more likely to be etched through, the semiconductor structure is easily disconnected, and the yield is reduced.

[0055] The embodiment of the present disclosure provides a semiconductor structure, which includes an active structure, a first gate structure, and a second gate structure. The active structure includes a first active region and a second active region connected in a first direction. At one end of the first active region and the second active region away from each other, a first recess and a second recess are respectively provided, and there is a spacing between the first recess and the second recess along the first direction. The first gate structure is disposed on the first active region, spans across the first recess and is spaced from the end of the first recess. The second gate structure is disposed on the second active region, spans across the second recess and is spaced from the end of the second recess. The connection of the first active region and the second active region increases the thickness of the active structure between the first recess and the second recess along the first direction. When the first recess and the second recess are formed, the active structure is not easily disconnected, and the yield of the semiconductor structure is improved.

[0056] To make the above objects, features, and advantages of the embodiments of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0057] Referring to Figure 1 , an embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure 100 includes an active structure AS, a first gate structure 30, and a second gate structure 40. The active structure AS includes a first active region and a second active region. The first active region Figure 1 is shown at A in Figure 1 , and the second active region is shown at B in Figure 1 . The first active region and the second active region are connected along a first direction. One end of the first active region and the second active region that are opposite to each other is connected to form an integral body. The first direction is the Y direction shown in

[0058] A first recess 15 is provided at one end of the first active region A away from the second active region B, and a second recess 25 is provided at one end of the second active region B away from the first active region A. That is, a first recess 15 and a second recess 25 are correspondingly provided at the ends of the first active region A and the second active region B that face away from each other. The opening of the first recess 15 faces away from the second active region B, and the bottom of the first recess 15 is close to the second active region B. The opening of the second recess 25 faces away from the first active region A, and the bottom of the second recess 25 is close to the first active region A.

[0059] The first recess 15 and the second recess 25 have a spacing D along the first direction, that is, the end of the first recess 15 and the end of the second recess 25 are spaced apart along the first direction Y. The sum of the depths of the first recess 15 and the second recess 25 along the first direction Y is less than the sum of the widths of the first active region A and the second active region B along the first direction.

[0060] The method for forming the semiconductor structure provided by the embodiment of the present disclosure includes: providing a substrate, forming a mask pattern on the substrate, etching the substrate based on the mask pattern to form an active structure, filling a shallow trench isolation structure, and forming a first gate structure and a second gate structure on the active structure and the shallow trench isolation structure. Among them, the shallow trench isolation structure fills the first recess and the second recess defined by the active structure. The shallow trench isolation structure may be a low dielectric constant material, including but not limited to silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride, so as to reduce the coupling between transistors formed based on the active structure.

[0061] With such an arrangement, compared with the separate first active region A and the first recess 15, or the separate second active region B and the second recess 25, the first active region A and the second active region B are in contact, and a part of the first active region A at the bottom of the first recess 15 and a part of the second active region B at the bottom of the second recess 25 are in contact, increasing the thickness of the active structure AS between the first recess 15 and the second recess 25 in the first direction. When forming the first recess 15 and the second recess 25, the active structure AS is not easily disconnected, improving the yield of the semiconductor structure.

[0062] In addition, on the basis of ensuring the continuity of the active structure AS, the critical dimension (CD) of the active structure AS can be further reduced. For example, the critical dimension of the first active region A opposite to the first recess 15 can be less than 50 nm, and the critical dimension of the second active region A opposite to the second recess 25 can be less than 50 nm.

[0063] Exemplarily, as Figure 1 shown, the first direction is the Y direction, and the first active region A and the second active region B are in end-to-end contact along the Y direction. Among them, one end of the first active region A is in contact with one end of the second active region B. The other end of the first active region A is provided with the first recess 15, and the opening of the first recess 15 faces away from the second active region B. The other end of the second active region B is provided with the second recess 25, and the opening of the second recess 25 faces away from the first active region A.

[0064] In some possible examples, the range of the spacing D between the first recess 15 and the second recess 25 in the first direction Y is 10 nm to 50 nm. The spacing between the first recess 15 and the second recess 25 in the first direction is greater than or equal to 10 nm and less than or equal to 50 nm, that is, 10 nm ≤ D ≤ 50 nm. With such an arrangement, it is avoided that the spacing D between the first recess 15 and the second recess 25 in the first direction Y is too small, thereby avoiding the disconnection of the active structure AS in the first direction when forming the first recess 15 and the second recess 25. At the same time, it can also avoid that the spacing D between the first recess 15 and the second recess 25 in the first direction Y is too large, thereby improving the space utilization rate of the semiconductor structure.

[0065] Continuing to refer to Figure 1 , the first gate structure 30 and the second gate structure 40 are spaced apart along the first direction Y and both extend along the second direction X. The first gate structure 30 is disposed on the first active region A, spans across the first recess 15 and is spaced from the end of the first recess 15. The second gate structure 40 is disposed on the second active region B, spans across the second recess 25 and is spaced from the end of the second recess 25. Among them, the second direction X intersects with the first direction Y, for example, is perpendicular, and the second direction X can be the X direction as shown in Figure 1 . The second direction X and the first direction Y are directions parallel to the plane where the substrate is located.

[0066] The end portion of the first recess 15 includes the opening and the bottom of the first recess 15. Along the second direction X, the first gate structure 30 straddles the first recess 15, and along the first direction Y, the two side walls of the first gate structure 30 are respectively spaced apart from the corresponding end portions of the first recess 15. The portion of the first gate structure 30 facing the first active region A along the first direction Y (i.e., the first active region at the bottom of the first recess 15) is spaced apart to avoid contact between the first gate structure 30 and the first active region of the portion of the first recess 15 facing it along the first direction, so as to avoid additionally increasing the channel length of the first gate structure 30.

[0067] The end portion of the second recess 25 includes the opening and the bottom of the second recess 25. Along the second direction X, the first gate structure 30 straddles the second recess 25, and along the first direction Y, the two side walls of the second gate structure 40 are respectively spaced apart from the corresponding end portions of the second recess 25. The portion of the second gate structure 40 facing the second active region B along the first direction Y (i.e., the second active region at the bottom of the second recess 25) is spaced apart to avoid contact between the second gate structure 40 and the second active region of the portion of the second recess 25 facing it along the first direction, so as to avoid additionally increasing the channel length of the second gate structure 40.

[0068] Continue to refer to Figure 1 , the first active region A includes a first connection portion 11 and a plurality of first extension portions 12 provided at one end of the first connection portion 11. The plurality of first extension portions 12 are arranged at intervals along the second direction X, and a first recess 15 is formed between two adjacent first extension portions 12. The second active region B includes a second connection portion 21 and a plurality of second extension portions 22 provided at one end of the second connection portion 21. The plurality of second extension portions 22 are arranged at intervals along the second direction X, and a second recess 25 is formed between two adjacent second extension portions 22. The first connection portion 11 and the second connection portion 21 are connected.

[0069] Wherein, one end of the first connection portion 11 and the second connection portion 21 facing each other is connected, the plurality of first extension portions 12 are provided at the end of the first connection portion 11 away from the second connection portion 21, and the plurality of second extension portions 22 are provided at the end of the second connection portion 21 away from the first connection portion 11.

[0070] The plurality of first extension portions 12 are arranged at intervals along the second direction X, and a first recess 15 is formed between two adjacent first extension portions 12 along the second direction X. For example, at least two first recesses 15 can be formed. The plurality of second extension portions 22 are arranged at intervals along the second direction X, and a second recess 25 is formed between two adjacent second extension portions 22 along the second direction. For example, at least two second recesses 25 can be formed. With such an arrangement, the integration density of the semiconductor structure can be improved.

[0071] It can be understood that the first gate structure 30 contacts a plurality of first extensions 12 along the second direction X and is spaced apart from the first connection portion 11 along the first direction Y, that is, the first gate structure 30 does not contact the first connection portion 11. The second gate structure 40 contacts a plurality of second extensions 22 along the second direction X and is spaced apart from the second connection portion 21 along the first direction Y, that is, the second gate structure 40 does not contact the second connection portion 21.

[0072] In some possible examples, referring to Figure 1 , the first extension 12 includes a first portion 13 connected to the first connection portion 11 and a second portion 14 connected to the side of the first portion 13 away from the first connection portion 11. The first portion 13 is connected between the first connection portion 11 and the second portion 14. One end of the first portion 13 is connected to the first connection portion 11, and the other end of the first portion 13 is connected to the second portion 14.

[0073] Along the second direction X, the distance between adjacent first portions 13 is greater than the distance between adjacent second portions 14, and the first gate structure 30 contacts the corresponding first portion 13. Wherein, the width of the first portion 13 along the second direction X is less than the width of the second portion 14 along the second direction X, and the opposite ends of the second portion 14 along the second direction X respectively protrude from the opposite ends of the first portion 13 along the second direction.

[0074] As Figure 1 shown, the left end of the first portion 13 is located on the left side of the left end of the second portion 14, and the right end of the first portion 13 is located on the right side of the right end of the second portion 14. The first gate structure 30 is opposite to the first portion 13 in the direction perpendicular to the plane of the substrate and is spaced apart from both the second portion 14 and the first connection portion 11, that is, the first gate structure 30 is spaced apart from both the second portion 14 and the first connection portion 11.

[0075] Continuing to refer to Figure 1 , the second extension 22 includes a third portion 23 connected to the second connection portion 21 and a fourth portion 24 connected to the side of the third portion 23 away from the second connection portion 21. The third portion 23 is connected between the second connection portion 21 and the fourth portion 24. One end of the third portion 23 is connected to the second connection portion 21, and the other end of the third portion 23 is connected to the fourth portion 24.

[0076] Along the second direction, the distance between adjacent third portions 23 is greater than the distance between adjacent fourth portions 24, and the second gate structure 40 contacts the corresponding third portion 23. Wherein, the width of the third portion 23 along the second direction is less than the width of the fourth portion 24 along the second direction, and the opposite ends of the fourth portion 24 along the second direction respectively protrude from the opposite ends of the third portion 23 along the second direction.

[0077] AsFigure 1 As shown, the left end of the third part 23 is located to the left of the left end of the fourth part 24, and the right end of the third part 23 is located to the right of the right end of the fourth part 24. The second gate structure 40 is opposite to the third part 23 and is staggered from both the fourth part 24 and the second connection part 21, that is, the second gate structure 40 is spaced apart from both the fourth part 24 and the second connection part 21.

[0078] It can be understood that at least in the GDS (Graphic Design System, a data conversion format for integrated circuit layout) layout, along the second direction, the distance between adjacent first parts 13 is greater than the distance between adjacent second parts 14, and the distance between adjacent third parts 23 is greater than the distance between adjacent fourth parts 24. After actual development (ADI, After Developing Inspection) or actual etching (AEI, After Etching Inspection), there may be a situation where along the second direction X, the distance between adjacent first parts 13 is greater than the distance between adjacent second parts 14, and the distance between adjacent third parts 23 is greater than the distance between adjacent fourth parts 24. Or there may be a situation where along the second direction X, the distance between adjacent first parts 13 is less than the distance between adjacent second parts 14, and / or the distance between adjacent third parts 23 is less than the distance between adjacent fourth parts 24.

[0079] In some possible examples, refer to Figures 2 to 4 , the first recess 15 of the first active region A faces the second recess 25 of the second active region along the first direction Y, that is, along the first direction, the first recess 15 faces the second recess 25.

[0080] Such as Figure 2 As shown, in some possible implementation manners, along the second direction X, the width of the first recess 15 is equal to the width of the second recess 25, both sides of the first recess 15 are aligned with both sides of the second recess 25 respectively, and the first recess 15 and the second recess 25 are axially symmetrically distributed.

[0081] Such as Figure 3 As shown, in some other possible implementation manners, along the second direction, the width of the first recess 15 is greater than the width of the second recess 25, and both sides of the first recess 15 are respectively located outside both sides of the second recess 25.

[0082] Such as Figure 4 As shown, in some other possible implementation manners, along the first direction, the width of the first recess 15 is less than the width of the second recess 25, and both sides of the first recess 15 are respectively located between both sides of the second recess 25.

[0083] In some other possible examples, refer to Figures 5 to 7 , the first recess 15 of the first active region A and the second recess 25 of the second active region B are arranged with a dislocation along the second direction X, that is, along the second direction X, the first recess 15 and the second recess 25 are at least partially dislocated. The projection of the first recess 15 in the first direction Y and the projection of the second recess 25 in the first direction Y only partially overlap. With such an arrangement, a part of the second recess 25 that is staggered from the first recess 15 is also directly opposite to a part of the first active region A, and the thickness of the directly opposite active structure increases, and the active structure is not easily disconnected along the second direction. A part of the first recess 15 that is staggered from the second recess 25 is also directly opposite to the second extension 22 of the second active region B along the first direction Y, and the thickness of the connecting part of the directly opposite active structure increases, and the active structure is not easily disconnected along the second direction.

[0084] Based on the above examples, as Figure 5 shown, in some possible implementation manners, in terms of the projection along the first direction Y, one side wall of the two side walls of the first recess 15 is between the two side walls of the second recess 25, and the other side wall is outside the two side walls of the second recess 25, and the first recess 15 and the second recess 25 are partially dislocated.

[0085] Based on the above examples, as Figure 6 shown, in some other possible implementation manners, in terms of the projection along the first direction Y, both side walls of the first recess 15 are on the same side of the two side walls of the second recess 25, the first recess 15 and the second recess 25 are completely dislocated, and are spaced apart along the first direction.

[0086] Based on the above examples, as Figure 7 shown, in some other possible implementation manners, the first recess 15 of the first active region A is directly opposite to the second extension 22 of the second active region B along the first direction Y, the second recess 25 of the second active region B is directly opposite to the first extension 12 of the first active region A along the first direction Y, the first recess 15 and the second recess 25 are completely dislocated, and are adjacent in sequence along the second direction X. For example, there are second recesses 25 on both the left and right sides of the first recess 15, the left side wall of the first recess 15 is flush with the right side wall of the second recess 25 on its left, and the right side wall of the first recess 15 is flush with the left side wall of the second recess 25 on its right.

[0087] Refer to Figure 5 and Figure 6, in some possible examples, along the second direction, the width of the first concave portion 15 of the first active region A is smaller than the width of the first extension portion 12 of the first active region A, and the width of the second concave portion 25 of the second active region B is smaller than the width of the second extension portion 22 of the second active region B. With such an arrangement, the smaller width of the first concave portion 15 can improve the transistor integration degree formed by the first active region A; the smaller width of the second concave portion 25 can improve the transistor integration degree formed by the second active region B.

[0088] Refer to Figure 8 , in some possible examples, along the second direction X, the width of the first concave portion 15 of the first active region A is greater than the width of the first extension portion 12 of the first active region A, and the width of the second concave portion 25 of the second active region B is greater than the width of the second extension portion 22 of the second active region B. With such an arrangement, the larger width of the first concave portion 15 results in a larger spacing between adjacent first extension portions 12, which can reduce the interference between adjacent transistors formed by the first active region A. The larger width of the second concave portion 25 results in a larger spacing between adjacent second extension portions 22, which can reduce the interference between adjacent transistors formed by the second active region B.

[0089] In some possible examples, along the second direction X, the width of the first concave portion 15 of the first active region A is equal to the width of the second concave portion 25 of the second active region B. With such an arrangement, along the second direction X, the spacing between adjacent first extension portions 12 is equal to the spacing between adjacent second extension portions 22, the interference effects between adjacent transistors in the first active region A are the same, and are the same as the interference effects between adjacent transistors in the second active region B.

[0090] In some possible examples, along the second direction, multiple first concave portions 15 of the first active region A are arranged at equal intervals, and multiple second concave portions 25 of the second active region B are arranged at equal intervals. With such an arrangement, along the second direction X, the widths of multiple first extension portions 12 are the same, and the transistors formed by the first active region A have better consistency. Along the second direction X, the widths of multiple second extension portions 22 are the same, and the transistors formed by the second active region B have better consistency.

[0091] Exemplarily, refer to Figure 9, along the second direction X, the width L1 of the first recess 15 is equal to the width L2 of the second recess 25. The multiple first recesses 15 of the first active region A are arranged at equal intervals, and the multiple second recesses 25 of the second active region B are arranged at equal intervals. Moreover, the distance L3 between adjacent first recesses 15 is equal to the distance L4 between adjacent second recesses 25, that is, L1 = L2 and L3 = L4. The width L1 of the first recess 15 is the distance between adjacent first extension portions 12, the width L2 of the second recess 25 is the distance between adjacent second extension portions 22, the distance L3 between adjacent first recesses 15 is the width of the first extension portion 12, and the distance L4 between adjacent second recesses 25 is the width of the second extension portion 22. With such an arrangement, along the second direction X, the width of the first extension portion 12 is equal to the width of the second extension portion 22, and the distance between adjacent first extension portions 12 is equal to the distance between adjacent second extension portions 22. The channel lengths of the transistors formed by the first active region A and the transistors formed by the second active region B are equal and the arrangements are the same, and the balancing effect is relatively good.

[0092] Again, by way of example, refer to Figure 10 , along the second direction X, the width L1 of the first recess 15 is greater than or less than the width L2 of the second recess 25. The multiple first recesses 15 of the first active region A are arranged at equal intervals, and the multiple second recesses 25 of the second active region B are arranged at equal intervals. Moreover, the distance L3 between adjacent first recesses 15 is equal to the distance L4 between adjacent second recesses 25, that is, L1 ≠ L2 and L3 = L4. With such an arrangement, along the second direction X, the width of the first extension portion 12 is equal to the width of the second extension portion 22, the distance between adjacent first extension portions 12 is not equal to the distance between adjacent second extension portions 22, the channel lengths of the transistors formed by the first active region A and the transistors formed by the second active region B are the same, but the intervals are different.

[0093] Also, by way of example, refer to Figure 11 , along the second direction X, the width L1 of the first recess 15 is equal to the width L2 of the second recess 25. The multiple first recesses 15 of the first active region A are arranged at equal intervals, and the multiple second recesses 25 of the second active region B are arranged at equal intervals. Moreover, the distance L3 between adjacent first recesses 15 is not equal to the distance L4 between adjacent second recesses 25, that is, L1 = L2 and L3 ≠ L4. With such an arrangement, along the second direction X, the width of the first extension portion 12 is not equal to the width of the second extension portion 22, the distance between adjacent first extension portions 12 is equal to the distance between adjacent second extension portions 22, the channel lengths of the transistors formed by the first active region A and the transistors formed by the second active region B are different, but the intervals are the same.

[0094] Another, by way of example, refer to Figure 12, along the second direction X, the width L1 of the first recess 15 is not equal to the width L2 of the second recess 25. The multiple first recesses 15 of the first active region A are arranged at equal intervals, and the multiple second recesses 25 of the second active region B are arranged at equal intervals. Moreover, the distance L3 between adjacent first recesses 15 is not equal to the distance L4 between adjacent second recesses 25, that is, L1≠L2, L3≠L4. With such a setting, along the second direction X, the width of the first extension 12 is not equal to the width of the second extension 22, the distance between adjacent first extensions 12 is not equal to the distance between adjacent second extensions 22, the channel lengths of the transistors formed by the first active region A and the transistors formed by the second active region B are different, and the intervals are different.

[0095] It can be understood that in the above example, along the first direction Y, the first recesses 15 have the same width, the second recesses 25 have the same width, the widths between adjacent first recesses 15 are the same, and the widths between adjacent second recesses 25 are the same, that is, both the first recesses 15 and the second recesses 25 are rectangular. When the first recesses 15 and the second recesses 25 are of other shapes, the widths of the first recess 15 and the second recess 25 respectively refer to the widths of the first recess 15 and the second recess 25 at the same distance from the bottom of the first recess 15 and the bottom of the second recess 25 along the first direction Y.

[0096] Refer to Figure 13 and Figure 14 , a plurality of first gate structures 30 may be provided on the first active region A so that the multiple transistors formed by the first active region A share the source / drain electrodes, improving the integration degree of the transistors. At least one second gate structure 40 may be provided on the second active region B so that the multiple transistors formed by the second active region B share the source / drain electrodes, improving the integration degree of the transistors.

[0097] In some possible examples, as Figure 13 and Figure 14 shown, along the first direction Y, the length of the first extension 12 of the first active region A is greater than the length of the second extension 22 of the second active region B. The number of the first gate structures 30 provided on the first active region A is greater than the number of the second gate structures 40 provided on the second active region B. With such a setting, along the first direction Y, the length of the first extension 12 is longer and the depth of the first recess 15 is greater. Compared with the second extension 22 and the second recess 25, more first gate structures 30 can be provided on the first extension 12 and the first recess 15, improving the space utilization rate of the semiconductor structure.

[0098] In summary, the semiconductor structure provided by the embodiments of the present disclosure includes an active structure AS, a first gate structure 30, and a second gate structure 40. The active structure AS includes a first active region and a second active region connected in a first direction. A first recess 15 is provided at an end of the first active region away from the second active region, and a second recess 25 is provided at an end of the second active region away from the first active region. The first recess 15 and the second recess 25 have a spacing in the first direction. The connection of the first active region and the second active region increases the thickness of the active structure between the first recess 15 and the second recess 25 in the first direction, and the active structure is not easily disconnected when the first recess 15 and the second recess 25 are formed, improving the yield of the semiconductor structure. The first gate structure 30 and the second gate structure 40 are spaced apart in the first direction and both extend in a second direction. The first gate structure 30 is disposed on the first active region, spans across the first recess 15 and is spaced from the end of the first recess 15, so as to avoid the first gate structure 30 contacting a part of the first active region facing the first recess 15 in the second direction, so as to avoid additionally increasing the channel length opposite to the first gate structure 30 and ensuring the performance of the semiconductor structure. The second gate structure 40 is disposed on the second active region, spans across the second recess 25 and is spaced from the end of the second recess 25, so as to avoid the second gate structure 40 contacting a part of the second active region facing the second recess 25 in the second direction, so as to avoid additionally increasing the channel length opposite to the second gate structure 40 and ensuring the performance of the semiconductor structure.

[0099] The embodiments of the present disclosure further provide a sense amplifier (abbreviated as SA), refer to Figure 15 , the sense amplifier includes an equalization unit 70, a sense amplifier unit 80, and a column selection unit 90, and the equalization unit 70 includes the above semiconductor structure. Among them, the sense amplifier can be applied to a dynamic random access memory, and the dynamic random access memory performs a data writing operation or a data reading operation through a capacitor unit.

[0100] An equalization unit 70, a sense amplifier unit 80, and a column selection unit 90 are connected between the bit line 50 and the complementary bit line 60. In the pre-charge stage of the read operation, the equalization unit 70 stabilizes the bit line 50 and the complementary bit line 60 at a reference voltage based on an equalization signal, the sense amplifier unit 80 reads and amplifies the voltage difference between the bit line 50 and the complementary bit line 60, and the column selection unit 90 is used to select the corresponding bit line 50.

[0101] In some possible examples, the sense amplifier unit 80 includes a first P-type transistor T1, a second P-type transistor T2, a first N-type transistor T3, and a second N-type transistor T4. The first P-type transistor T1 is connected between the first signal terminal 81 and the bit line 50, and has a control terminal connected to the complementary bit line 60. The second P-type transistor T2 is connected between the first signal terminal 81 and the complementary bit line 60, and has a control terminal connected to the bit line 50. The first N-type transistor T3 is connected between the second signal terminal 82 and the bit line 50, and has a control terminal connected to the complementary bit line 60. The second N-type transistor T4 is connected between the second signal terminal 82 and the complementary bit line 60, and has a control terminal connected to the bit line 50.

[0102] Specifically, the source of the first P-type transistor T1 is connected to the first signal terminal 81, the drain is connected to the bit line 50, and the gate is connected to the complementary bit line 60. The source of the second P-type transistor T2 is connected to the first signal terminal 81, the drain is connected to the complementary bit line 60, and the gate is connected to the bit line 50. The source of the first N-type transistor T3 is connected to the second signal terminal 82, the drain is connected to the bit line 50, and the gate is connected to the complementary bit line 60. The source of the second N-type transistor T4 is connected to the second signal terminal 82, the drain is connected to the complementary bit line 60, and the gate is connected to the bit line 50. Among them, the first signal terminal 81 receives a first-level signal SAP, and the second signal terminal 82 receives a second-level signal SAN.

[0103] In some possible examples, the voltage of the first-level signal SAP is greater than the voltage of the second-level signal SAN. For example, the first-level signal SAP is a high level corresponding to logic "1", and the second-level signal SAN is a low level corresponding to logic "0". In other examples, the voltage of the first-level signal SAP is less than the voltage of the second-level signal SAN, that is, the first-level signal SAP is a low level corresponding to logic "0", and the second-level signal SAN is a high level corresponding to logic "1".

[0104] The equalization unit 70 includes a first transistor T5, a second transistor T6, and a third transistor T7, and the first transistor T5, the second transistor T6, and the third transistor T7 all have control terminals receiving an equalization signal EQ. The first transistor T5 is connected between the third signal terminal 71 and the bit line 50, and has a control terminal connected to the fourth signal terminal 72. The second transistor T6 is connected between the third signal terminal 71 and the complementary bit line 60, and has a control terminal connected to the fourth signal terminal 72. The third transistor T7 is connected between the bit line 50 and the complementary bit line 60, and has a control terminal connected to the fourth signal terminal 72. Among them, the fourth signal terminal 72 receives the equalization signal EQ.

[0105] Specifically, the source of the first transistor T5 is connected to the bit line 50, the drain is connected to the third signal terminal 71, and the gate is connected to the fourth signal terminal 72. The source of the second transistor T6 is connected to the complementary bit line 60, the drain is connected to the third signal terminal 71, and the gate is connected to the fourth signal terminal 72. The source of the third transistor T7 is connected to the bit line 50, the drain is connected to the complementary bit line 60, and the gate is connected to the fourth signal terminal 72.

[0106] The column selection unit 90 includes a fourth transistor T8 and a fifth transistor T9. The fourth transistor T8 and the fifth transistor T9 are respectively disposed on the bit line 50 and the complementary bit line 60, and both have control terminals for receiving a strobe signal. The fourth transistor T8 is located on the bit line 50 and has a control terminal connected to the fifth signal terminal 91. The fifth transistor T9 is located on the complementary bit line 60 and has a control terminal connected to the fifth signal terminal 91. Among them, the fifth signal terminal 91 receives the strobe signal SCL.

[0107] It should be noted that the specific connection manners of the "source" and "drain" defined by the above various transistors do not constitute a limitation on the embodiments of the present disclosure. In other embodiments, the connection manner of replacing the "source" with the "drain" and the "drain" with the "source" can be adopted.

[0108] During the data reading process of the dynamic random access memory, a pre-charge stage will be executed first to pre-charge the bit line 50 and the complementary bit line 60 to a preset voltage V ref , and then enter the next stage, such as the data readout stage.

[0109] Among them, in the pre-charge stage, by providing an equalization signal EQ to turn on the first transistor T5, the second transistor T6, and the third transistor T7. After the first transistor T5, the second transistor T6, and the third transistor T7 are turned on, the voltages of the bit line 50 and the complementary bit line 60 are stabilized at the preset voltage V ref . The preset voltage V ref is the voltage received by the third signal terminal 71. In the embodiments of the present disclosure, V ref = 1 / 2V DD , V DD is the internal power supply voltage of the dynamic random access memory; in other embodiments, the preset voltage V ref can be set according to specific application scenarios.

[0110] In summary, the sense amplifier in the embodiments of the present disclosure includes an equalization unit 70, a read amplification unit 80, and a column selection unit 90. The equalization unit 70 includes the above semiconductor structure. The sense amplifier includes the above semiconductor structure, and thus has at least the advantages of being not easily disconnected and having a high yield. For the specific effects, refer to the above text and will not be elaborated here.

[0111] The embodiments or implementation manners in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. The descriptions with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, it includes: An active structure, the active structure includes a first active region and a second active region connected in a first direction, a first concave portion is provided at one end of the first active region away from the second active region, and a second concave portion is provided at one end of the second active region away from the first active region, and there is a spacing between the first concave portion and the second concave portion along the first direction; A first gate structure and a second gate structure spaced along the first direction, both the first gate structure and the second gate structure extend in a second direction, the first gate structure is disposed on the first active region, straddles the first concave portion and is spaced from the end of the first concave portion, the second gate structure is disposed on the second active region, straddles the second concave portion and is spaced from the end of the second concave portion, and the second direction intersects the first direction.

2. The semiconductor structure according to claim 1, characterized in that, The first active region includes a first connecting portion, and a plurality of first extending portions provided at one end of the first connecting portion, the plurality of first extending portions are arranged at intervals along the second direction, and the first concave portion is formed between two adjacent first extending portions; The second active region includes a second connecting portion, and a plurality of second extending portions provided at one end of the second connecting portion, the plurality of second extending portions are arranged at intervals along the second direction, and the second concave portion is formed between two adjacent second extending portions; The first connecting portion and the second connecting portion are connected.

3. The semiconductor structure according to claim 2, characterized in that, The first extending portion includes a first part connected to the first connecting portion, and a second part connected to the side of the first part away from the first connecting portion. Along the second direction, the distance between adjacent first parts is greater than the distance between adjacent second parts, and the first gate structure is in contact with the corresponding first part; The second extending portion includes a third part connected to the second connecting portion, and a fourth part connected to the side of the third part away from the second connecting portion. Along the second direction, the distance between adjacent third parts is greater than the distance between adjacent fourth parts, and the second gate structure is in contact with the corresponding third part.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The first concave portion of the first active region faces the second concave portion of the second active region along the first direction.

5. The semiconductor structure according to claim 2 or 3, characterized in that, The first concave portion of the first active region and the second concave portion of the second active region are arranged in a dislocation along the second direction.

6. The semiconductor structure according to claim 5, characterized in that, The first concave portion of the first active region faces the second extending portion of the second active region along the first direction, and the second concave portion of the second active region faces the first extending portion of the first active region along the first direction.

7. The semiconductor structure according to claim 2 or 3, Characterized in that, Along the second direction, the width of the first recess of the first active region is smaller than the width of the first extension portion of the first active region, and the width of the second recess of the second active region is smaller than the width of the extension portion of the second active region.

8. The semiconductor structure according to claim 2 or 3, Characterized in that, Along the second direction, the width of the first recess of the first active region is equal to the width of the second recess of the second active region; And / or, along the second direction, the plurality of first recesses of the first active region are arranged at equal intervals, and the plurality of second recesses of the second active region are arranged at equal intervals.

9. The semiconductor structure according to claim 2 or 3, Characterized in that, Along the first direction, the length of the first extension portion of the first active region is greater than the length of the second extension portion of the second active region; The number of the first gate structures provided on the first active region is greater than the number of the second gate structures provided on the second active region.

10. The semiconductor structure according to any one of claims 1-3, Characterized in that, The range of the distance between the first recess and the second recess along the first direction is 10 nm to 50 nm.

11. A sense amplifier, comprising an equalization unit, a sense amplification unit and a column selection unit; Wherein, The equalization unit includes the semiconductor structure according to any one of claims 1-10.

Images