Semiconductor structure and method of forming the same

Abstract

The present disclosure provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a plurality of active pillars arranged in an array; a plurality of word lines; the word lines extend along a first direction and cover the sidewalls of the active pillars in the same row arranged along the first direction; the first direction is perpendicular to the direction in which the active pillars extend; a plurality of word line isolation structures; the word line isolation structures extend along the first direction and are located between adjacent word lines, and comprise first isolation structures and second isolation structures arranged alternately along the first direction; wherein the first size of the first isolation structures along a second direction is different from the second size of the second isolation structures along the second direction; the second direction is parallel to the direction in which the active pillars extend.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers, which is composed of a plurality of memory cells. With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. However, as the density of semiconductor devices increases, the size is reduced, which makes the manufacturing process of semiconductor devices more difficult, and thus the performance of the formed semiconductor devices is greatly reduced. SUMMARY

[0003] Therefore, embodiments of the present disclosure provide a semiconductor structure and a forming method thereof.

[0004] According to a first aspect of embodiments of the present disclosure, a semiconductor structure is provided, comprising: a plurality of active pillars arranged in an array; a plurality of word lines; the word lines extend along a first direction and cover the sidewalls of the active pillars in the same row arranged along the first direction; the first direction is perpendicular to the direction in which the active pillars extend; a plurality of word line isolation structures; the word line isolation structures extend along the first direction and are located between adjacent word lines, and comprise first isolation structures and second isolation structures arranged alternately along the first direction; wherein the first size of the first isolation structure along a second direction is different from the second size of the second isolation structure along the second direction; the second direction is parallel to the direction in which the active pillars extend.

[0005] In an optional implementation, the first isolation structure is located between two active pillars adjacent along a third direction, the second isolation structure is located between two interval structures adjacent along the third direction, and the interval structures are located between two active pillars adjacent along the first direction; the third direction is perpendicular to the second direction and intersects the first direction; the first size is smaller than the second size.

[0006] In an optional implementation, the word line comprises first conductive structures and second conductive structures arranged alternately along the first direction; wherein the first conductive structure covers part of the surface of two sidewalls of the active pillar oppositely arranged along a third direction, and the second conductive structure connects two first conductive structures adjacent along the first direction; the first isolation structure is located between two first conductive structures adjacent along the third direction, and the second isolation structure is located between two second conductive structures adjacent along the third direction.

[0007] In an optional implementation, a size of the first isolation structure along the second direction is greater than a size of the first conductive structure along the second direction; and the semiconductor structure further includes a first insulating structure, the first insulating structure partially surrounding a portion of the first isolation structure extending beyond the first conductive structure along the second direction.

[0008] In an optional implementation, a bottom of the first insulating structure is not higher than a bottom of the first isolation structure.

[0009] In an optional implementation, the semiconductor structure further includes a second insulating structure, the second insulating structure including a first portion and a second portion; wherein the first portion is located between the first conductive structure and two sidewalls of the active pillar oppositely arranged along a third direction, and the second portion is located between two second conductive structures adjacent along the first direction and two sidewalls of the active pillar oppositely arranged along the first direction.

[0010] According to a second aspect of the embodiments of the present disclosure, a method for forming a semiconductor structure is provided, including: forming a plurality of active pillars arranged in an array; forming a plurality of word lines extending along a first direction; the word lines covering sidewalls of the active pillars in the same row arranged along the first direction; the first direction being perpendicular to a direction in which the active pillars extend; forming a word line isolation structure extending along the first direction between two adjacent word lines; the word line isolation structure including first isolation structures and second isolation structures alternately arranged along the first direction; wherein a first size of the first isolation structure along a second direction is different from a second size of the second isolation structure along the second direction; the second direction being parallel to the direction in which the active pillars extend.

[0011] In an optional implementation, forming the active pillars includes: providing a semiconductor substrate; forming a plurality of first trenches extending along a third direction in the semiconductor substrate, and filling the first trenches with insulating material; the third direction being perpendicular to the second direction and intersecting the first direction; performing a first etching operation to form second trenches extending along the first direction in the semiconductor substrate filled with insulating material; the first etching operation using etching sources with different etching selectivity ratios for the semiconductor substrate and the insulating material; performing a second etching operation on the second trenches to form third trenches, the first trenches and the third trenches dividing the semiconductor substrate into a plurality of active pillars; the first etching operation using etching sources different from those used in the second etching operation; wherein each of the third trenches includes first sub-trenches and second sub-trenches alternately arranged along the first direction; wherein a first depth of the first sub-trenches along the second direction is different from a second depth of the second sub-trenches along the second direction.

[0012] In an alternative embodiment, the first etching operation uses an etching source with an etching rate on the semiconductor substrate greater than that on the insulating material; the second etching operation uses an etching source with an etching rate on the insulating material greater than that on the semiconductor substrate; the first sub-trench is located between two active pillars adjacent along the third direction; the second sub-trench is located between two insulating materials adjacent along the third direction; and the first depth is less than the second depth.

[0013] In an alternative embodiment, the method further comprises: forming a protection layer on at least the top of the semiconductor substrate before performing the second etching operation; forming the protection layer on at least the top of the semiconductor substrate comprises: in-situ oxidizing the semiconductor substrate with the second trench formed thereon before performing the second etching operation to form an oxide layer on the top of the semiconductor substrate, the sidewalls and the bottom of the second trench between two active pillars adjacent along the third direction; the oxide layer covering the top of the semiconductor substrate is the protection layer; wherein during the second etching operation, the oxide layer covering the bottom of the second trench is removed; or forming a dielectric layer on the top of the semiconductor substrate and the sidewalls and the bottom of the third trench before performing the second etching operation; the dielectric layer covering the top of the semiconductor substrate is the protection layer; wherein during the second etching operation, the dielectric layer covering the bottom of the second trench is removed.

[0014] In an alternative embodiment, forming the word line and the word line isolation structure comprises: filling the third trench with an isolation material; the top of the isolation material is flush with the top of the active pillar; performing a first back-etching on the oxide layer / dielectric layer and the insulating material of the sidewall of the third trench, and forming an isolation layer at the part where the material is removed by the first back-etching; the isolation material below the bottom of the isolation layer forms the word line isolation structure; performing a second back-etching on the oxide layer / dielectric layer and the insulating material of the sidewall of the third trench, and forming the word line at the part where the material is removed by the second back-etching; the oxide layer / dielectric layer remaining on the sidewall of the third trench forms a first insulating structure.

[0015] The word line isolation structure in the embodiment of the present disclosure extends along the first direction and is located between adjacent word lines, and includes first isolation structures and second isolation structures arranged alternately along the first direction; wherein the first size of the first isolation structure along the second direction is different from the second size of the second isolation structure along the second direction; the second direction is parallel to the direction in which the active pillar extends. The different settings of the first size and the second size can meet the corresponding topography requirements of the word line isolation structure under different environmental materials, so that the word line isolation structure has a more optimal topography in the direction in which the active pillar extends, can effectively isolate adjacent word lines, avoid the short circuit problem of adjacent word lines, and also effectively prevent the problem of sharp tip discharge, thereby improving the stability of the semiconductor device in which the semiconductor structure is located. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A top view structural schematic diagram of a part of a semiconductor structure formed in an embodiment of the present disclosure;

[0017] Figures 2A-2H A cross-sectional schematic diagram of main process steps in the process of forming a semiconductor structure in an embodiment of the present disclosure;

[0018] Figure 3 A top view structural schematic diagram of a part of a semiconductor structure provided by another embodiment of the present disclosure;

[0019] Figure 4 A local enlarged view corresponding to the dashed box in Figure 3

[0020] Figure 5A A cross-sectional schematic diagram of main process steps in the process of forming a semiconductor structure in an embodiment of the present disclosure; Figure 3

[0021] Figure 5B A cross-sectional schematic diagram of main process steps in the process of forming a semiconductor structure in an embodiment of the present disclosure; Figure 3

[0022] Figure 6 A specific implementation flowchart of a forming method of a semiconductor structure provided by an embodiment of the present disclosure;

[0023] Figures 7A-7K A cross-sectional schematic diagram of main process steps in the process of forming a semiconductor structure in an embodiment of the present disclosure;

[0024] Figure 8 A cross-sectional schematic diagram of a process step of forming a protective layer on the top of a semiconductor substrate before performing a second etching operation provided by another embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] ​​​The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0026] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features are not described in detail to avoid obscuring the present disclosure. In the interest of clarity, not all features of the actual implementation are described in detail (exemplary implementations are shown in excessive detail, not to be construed as limiting).

[0027] In the drawings, the size of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference numbers represent the same elements throughout the drawings.

[0028] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to" or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0032] Figure 1 This is a top view schematic diagram of a portion of the semiconductor structure formed in one embodiment of the present disclosure. Figures 2A-2H This is a cross-sectional schematic diagram of the main process steps in forming a semiconductor structure according to an embodiment of the present disclosure. Figures 2A-2H from Figure 1 The four directions aa', bb', cc', and dd' in the diagram show cross-sectional schematics of the main process steps in the formation of the semiconductor structure, clearly illustrating the formation process of the semiconductor structure.

[0033] It should be noted that herein and hereinafter, the first direction can be the direction in which the word line extends, and the third direction can be the direction in which the bit line extends, both of which are perpendicular to the direction in which the active pillar extends, or parallel to the top surface of the semiconductor substrate. In some embodiments, the first direction is perpendicular to the third direction. Exemplarily, the first direction can be the direction in which the x-axis extends in the drawing, and the third direction can be the direction in which the y-axis extends in the drawing. The second direction is parallel to the direction in which the active pillar extends, or parallel to the thickness direction of the semiconductor substrate. The second direction is perpendicular to both the first direction and the third direction. Exemplarily, the second direction can be the direction in which the z-axis extends in the drawing.

[0034] As shown in Figure 1 , the semiconductor structure includes active pillars 12 arranged in an array, word lines 11 extending in the first direction (x direction shown in the drawing), and bit lines 10 extending in the third direction (y direction shown in the drawing).

[0035] It should be noted that, for the convenience of illustration and description, Figures 2A-2H , the bit lines in Figure 1 are not shown.

[0036] Referring to Figure 1 and Figures 2A-2H , the method for forming the semiconductor structure is as follows.

[0037] As shown in Figure 2A , a substrate 101 is provided and etched to form a plurality of first grooves extending in the third direction, a filling layer 102 and a strip-shaped portion 103 are formed in the first grooves.

[0038] Exemplarily, the material of the substrate 101 includes but is not limited to a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (such as a germanium-silicon substrate, etc.), etc. The material of the filling layer 102 includes but is not limited to silicon oxide.

[0039] As shown in Figure 2B , the strip-shaped portion 103 and the filling layer 102 are etched to form a plurality of second grooves extending in the first direction, active pillars 12 and insulating pillars 106, the second grooves including first sub-grooves 104 formed by etching the strip-shaped portion 103 and second sub-grooves 105 formed by etching the filling layer 102. The first sub-grooves 104 and the second sub-grooves 105 are alternately arranged in the first direction.

[0040] Because the second groove has a large depth-to-width ratio, insufficient etching sources reach the bottom during its formation. This reduced reactant concentration leads to a lower reaction rate in the bottom region of the second groove. Therefore, when etching the strip-shaped portion 103 and the filling layer 102 from top to bottom, the resulting second groove will be an inverted trapezoidal shape, wider at the top and narrower at the bottom. It is understandable that, ideally, both the first sub-groove 104 and the second sub-groove 105 formed in the same etching process would be inverted trapezoidal shapes, wider at the top and narrower at the bottom. However, because the etching source used in the etching process for forming the second groove has a similar vertical etching rate for the strip portion 103 as it does for the filling layer 102, but a greater lateral etching rate for the strip portion 103 than for the filling layer 102, for example, the strip portion 103 is silicon and the filling layer 102 is silicon oxide. Etching silicon oxide requires high-energy ions to break the Si-O bonds, resulting in a very slow lateral etching rate for the filling layer 102. This leads to insufficient lateral etching at the bottom of the second sub-groove 105, causing the second sub-groove 105 to appear... Figure 2B The "V" shape shown in the bb' section.

[0041] like Figure 2C As shown, a first isolation layer 107 and a second isolation layer 108 are sequentially formed, covering at least the inner wall and top of the second groove. Because... Figure 2B The second sub-groove 105 formed in the middle is V-shaped. The first isolation layer 107 and the second isolation layer 108 in the second sub-groove are conformal to the second sub-groove. Therefore, the first isolation layer 107 and the second isolation layer 108 in the second sub-groove are also V-shaped.

[0042] refer to Figure 2C and Figure 2D The first isolation layer 107, the second isolation layer 108 and the filling layer 102 on the sidewall of the second groove are etched back to form the first gap 109.

[0043] refer to Figure 2D and Figure 2E A sidewall 110 is formed in the first gap 109. A second isolation layer located below the bottom of the sidewall 110 is used to isolate adjacent word lines.

[0044] refer to Figure 2E and Figure 2F The first isolation layer 107 and the filling layer 102 on the sidewall of the second groove are etched back along the sidewall 110 to form the second gap 111-1 and the third gap 111-2. Exemplarily, a wet etching process can be used to form the second gap 111-1 and the third gap 111-2. During the wet etching process, the following may occur: Figure 2FOver Etch phenomenon shown in the dotted circle at B in the schematic view of the section along the direction of bb' in FIG. 1, causes the first isolation layer 107 on the sidewall and even the bottom of the second recess to be consumed too much, so that the second gap 111-1 on both sides of the second isolation layer 108 along the third direction is too deep or even connected.

[0045] Referring to Figure 2F and Figure 2G , the gate oxide layer 113 and the gate layer 112 are sequentially formed in the second gap 111-1 and the third gap 111-2 to form a word line. Referring to Figure 2G and Figure 2H , after the word line is formed, a cover layer 115 covering the word line is formed.

[0046] In combination with Figure 2E , the second isolation layer below the bottom of the side wall 110 is used to isolate adjacent word lines, but as shown in the dotted circle at A in the schematic view of the section along the direction of bb' in FIG. 1, Figure 2G and Figure 2H , the second isolation layer below the bottom of the side wall in the second recess is in a "V" shape, not only prone to tip discharge phenomenon, which is not conducive to the stability of the device, but also causes the adjacent word lines to short circuit due to insufficient depth.

[0047] In addition, in combination with Figure 2F , over etching causes the second gap 111-1 on both sides of the second isolation layer 108 along the third direction to be too deep or even connected, and subsequently when the word line is formed, as shown in the dotted circle at B in the schematic view of the section along the direction of bb' in FIG. 1, Figure 2G and Figure 2H , the gate layer in the second gap 111-1 will also be connected, which will cause the adjacent word lines on both sides of the second isolation layer 108 along the third direction to short circuit. Therefore, the present disclosure provides a semiconductor structure and a forming method thereof. Figure 3 A schematic view of the top structure of a partial structure of a semiconductor structure provided by another embodiment of the present disclosure, Figure 4 is a local enlarged view corresponding to the dotted box in Figure 3 , Figure 5A is a schematic view of the section along the tangent direction of aa' and the direction of bb' shown in Figure 3 , Figure 5B is a schematic view of the section along the tangent direction of cc' and the direction of dd' shown in Figure 3 .

[0048] It should be noted that, in order to more clearly show the bit line and the word line, Figure 3 the cover layer (26 in the bb' section of FIG. 1) above the word line is hidden in Figure 5A .

[0049] Referring to Figures 3-5BThe semiconductor structure comprises: a plurality of active pillars 22 arranged in an array; a plurality of word lines 21; the word lines 21 extend along a first direction (x direction shown in the figure) and cover the sidewalls of the active pillars 22 in the same row arranged along the first direction; the first direction is perpendicular to the direction in which the active pillars 22 extend; a plurality of word line isolation structures; the word line isolation structures extend along the first direction and are located between adjacent word lines 21, and comprise first isolation structures and second isolation structures arranged alternately along the first direction; wherein the first size H1 of the first isolation structure along a second direction is different from the second size H2 of the second isolation structure along the second direction; the second direction is parallel to the direction in which the active pillars 22 extend.

[0050] As shown in Figure 5A The semiconductor structure comprises an isolation layer 24 and a cap layer 26 covering the word lines, and the materials of the isolation layer 24 and the cap layer 26 can be the same or different. Exemplarily, the materials of the isolation layer 24 and the cap layer 26 are both silicon nitride.

[0051] The semiconductor structure further comprises a semiconductor substrate 201, and the active pillars 22 are located on the semiconductor substrate 201. Exemplarily, the material of the semiconductor substrate 201 is but not limited to a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (such as a silicon-germanium substrate, etc.), etc.

[0052] In some embodiments, the first size H1 is smaller than the second size H2. In this way, the depth of the second isolation structure of the word line isolation structure is larger, which can effectively isolate the adjacent word lines and avoid short circuit of the adjacent word lines.

[0053] It should be noted that the design depths of the first isolation structure and the second isolation structure of the word line isolation structure are consistent, and the depth difference caused by manufacturing errors, etc. is not included in the different depth dimensions described in the disclosure.

[0054] In some embodiments, the ratio of the difference between the first size H1 and the second size H2 to the second size H2 ranges from 1 / 10 to 1 / 5. More specifically, the ratio of the difference ΔH between the first size H1 and the second size H2 to the second size H2 can be 1 / 10, 1 / 9, 1 / 8, 1 / 7, 1 / 16, or 1 / 5.

[0055] In some embodiments, the first size H1 ranges from 80 nm to 150 nm, and the second size H2 ranges from 90 nm to 250 nm. Exemplarily, the first size H1 is 100 nm, and the second size H2 is 120 nm.

[0056] In some embodiments, the ratio of the size of the top of the second isolation structure along the first direction / third direction to the size of the bottom of the second isolation structure along the first direction / third direction ranges from 5:2 to 3:2.

[0057] AsFigure 5A As shown, W1 is the opening size of the top of the second isolation structure along the third direction, and W2 is the opening size of the bottom of the second isolation structure along the third direction. The ratio of W1 to W2 ranges from 5:2 to 3:2. More specifically, the ratio of W1 to W2 can be 5:2, 4:2, or 3:2.

[0058] In this way, the bottom of the second isolation structure of the word line isolation structure is widened, which can effectively prevent the tip discharge problem, improve the stability of the device, effectively isolate the adjacent word lines, and avoid short circuit of the adjacent word lines.

[0059] In some embodiments, the opening size of the top of the second isolation structure along the third direction is 25 nm, and the opening size of the bottom of the second isolation structure along the third direction is 10 nm.

[0060] In some embodiments, the opening size of the top of the second isolation structure along the third direction is 21 nm, and the opening size of the bottom of the second isolation structure along the third direction is 14 nm.

[0061] In some embodiments, the first isolation structure is located between two active pillars adjacent along the third direction, the second isolation structure is located between two spacing structures adjacent along the third direction, and the spacing structure is located between two active pillars adjacent along the first direction; the third direction is perpendicular to the second direction and intersects the first direction.

[0062] The word line is electrically connected to the gate of each active pillar in a row of active pillars extending along the first direction. Here, the shape of the gate is different in different types of transistors; for example, in a columnar gate transistor, the gate is formed on one side of the channel region; the gate fully surrounds the channel region. Figure 3 and Figure 4 , Figure 5A , Figure 5B The case where the gate covers four sides of the channel region is exemplified in the above.

[0063] In some embodiments, the word line includes first conductive structures and second conductive structures arranged alternately along the first direction; the first conductive structure covers part of the surface of two sidewalls of the active pillar oppositely arranged along the third direction, and the second conductive structure connects two first conductive structures adjacent along the first direction; the first isolation structure is located between two first conductive structures adjacent along the third direction, and the second isolation structure is located between two second conductive structures adjacent along the third direction.

[0064] As Figure 4As shown, the word line 21 includes first conductive structures 211 and second conductive structures 212 arranged alternately along the first direction; wherein the first conductive structure 211 covers part of the surface of the two side walls of the active pillar 22 oppositely arranged along the third direction, and the second conductive structure 212 connects two first conductive structures 211 adjacent along the first direction; the first isolation structure is located between two first conductive structures 211 adjacent along the third direction, and the second isolation structure is located between two second conductive structures 212 adjacent along the third direction.

[0065] As shown, Figure 5A the first isolation structure is located between two active pillars 22 adjacent along the third direction, and the second isolation structure is located between two spacing structures 27 adjacent along the third direction, and the spacing structure 27 is located between two active pillars 22 adjacent along the first direction. The spacing structure 27 includes the second conductive structure 212 and the insulating material located below the second conductive structure 212.

[0066] In some embodiments, the size of the first isolation structure along the second direction is greater than the size of the first conductive structure along the second direction; the semiconductor structure further includes a first insulating structure, and the first insulating structure partially surrounds the part of the first isolation structure extending beyond the first conductive structure along the second direction.

[0067] Exemplarily, as shown, Figure 5A the size H1 of the first isolation structure along the second direction is greater than the size H3 of the first conductive structure along the second direction. The semiconductor structure further includes a first insulating structure 28, and the first insulating structure 28 partially surrounds the part of the first isolation structure extending beyond the first conductive structure 211 along the second direction.

[0068] In some embodiments, the bottom of the first insulating structure is not higher than the bottom of the first isolation structure. In this way, the bottom of the first insulating structure can be prevented from being broken down when the semiconductor structure is working in the semiconductor device, and become a channel for short circuit of adjacent word lines located on both sides of the second isolation layer along the third direction.

[0069] Preferably, the bottom of the first insulating structure is higher than the bottom of the first isolation structure.

[0070] In some embodiments, the semiconductor structure further includes a second insulating structure 23, and the second insulating structure 23 includes a first part 231 and a second part 232; wherein the first part 231 is located between the first conductive structure 211 and the two side walls of the active pillar 22 oppositely arranged along the third direction, and the second part 232 is located between two second conductive structures 323 adjacent along the first direction and the two side walls of the active pillar 33 oppositely arranged along the first direction.

[0071] Here, the second insulating structure 23 can serve as the gate oxide layer of the aforementioned gate.

[0072] In some embodiments, the active pillar comprises a first active region, a channel region and a second active region distributed from bottom to top; as Figure 3 shown, the semiconductor structure further comprises: a plurality of bit lines 20 located below the plurality of word lines 21; each bit line 20 extends along a third direction and is electrically connected to the first active region of the active pillar 22 in the same column arranged along the third direction; the third direction is perpendicular to the second direction and intersects the first direction; the word line 21 covers the channel region of the active pillar 22 in the same row arranged along the first direction; a storage structure (not shown in the figure) is located above the plurality of word lines 21 and is electrically connected to the second active region of the active pillar 22. Figure 3

[0073] Here, the storage structure can include a capacitor. Here, by setting the bit line below the word line to form a buried bit line (BBL), the resistance can be reduced, the process difficulty can be reduced, and the circuit design scheme of the memory is more matched.

[0074] The embodiments of the present disclosure further provide a memory comprising the semiconductor structure of any one of the preceding embodiments. Exemplarily, the memory can be a DRAM, a static random access memory (SRAM), etc.

[0075] The embodiments of the present disclosure further provide a forming method of a semiconductor structure. Figure 6 A specific implementation flowchart of the forming method of the semiconductor structure provided by an embodiment of the present disclosure is shown in the figure. As Figure 6 shown, the specific steps of the forming method of the semiconductor structure include:

[0076] Step S10: forming a plurality of active pillars arranged in an array.

[0077] Step S20: forming a plurality of word lines extending along a first direction; the word line covers the sidewall of the active pillar in the same row arranged along the first direction; the first direction is perpendicular to the direction in which the active pillar extends.

[0078] Step S30: forming a word line isolation structure extending along the first direction between two adjacent word lines; the word line isolation structure comprises first isolation structures and second isolation structures arranged alternately along the first direction; wherein the first dimension of the first isolation structure along the second direction is different from the second dimension of the second isolation structure along the second direction; the second direction is parallel to the direction in which the active pillar extends.

[0079] Figures 7A-7K A cross-sectional schematic diagram of the main process steps in the process of forming the semiconductor structure provided by an embodiment of the present disclosure is shown in the figure. Figures 7A-7K From Figure 3 ​The four directions of aa', bb', cc', and dd' in FIG. 1 show cross-sectional schematic diagrams of main process steps in the forming process of the semiconductor structure, to clearly show the forming process of the semiconductor structure. The forming process of the semiconductor structure of the present embodiment will be described below with reference to FIGS. 1-4. Figure 6 and Figures 7A-7K The forming process of the semiconductor structure of the present embodiment will be described below with reference to FIGS. 1-4.

[0080] As shown in FIG. 1, a semiconductor substrate 201 is provided. Exemplarily, the material of the semiconductor substrate 201 includes but is not limited to a single-element semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium substrate, etc.), etc. Figure 7A As shown in FIG. 2, the semiconductor substrate 201 is etched to form a plurality of first trenches 202 extending along a third direction in the semiconductor substrate 201, the third direction being perpendicular to the second direction and intersecting the first direction. In some embodiments, a dry etching process can be used to etch the semiconductor substrate 201 along a direction perpendicular to the top surface of the semiconductor substrate 201 to form a plurality of first trenches 202 parallel to each other and spaced apart along the cc' direction. The semiconductor substrate remaining between adjacent first trenches 202 forms a first initial active pillar 203. The method of etching the semiconductor substrate 201 can use a SADP (Self-Aligned Double Patterning) process, a SARP (Self-Aligned Reverse Patterning) process, or a SAQP (Self-Aligned Quadruple Patterning) process to accurately control the position and topography of the first trenches 202.

[0081] Figure 7B As shown in FIG. 2, the semiconductor substrate 201 is etched to form a plurality of first trenches 202 extending along a third direction in the semiconductor substrate 201, the third direction being perpendicular to the second direction and intersecting the first direction. In some embodiments, a dry etching process can be used to etch the semiconductor substrate 201 along a direction perpendicular to the top surface of the semiconductor substrate 201 to form a plurality of first trenches 202 parallel to each other and spaced apart along the cc' direction. The semiconductor substrate remaining between adjacent first trenches 202 forms a first initial active pillar 203. The method of etching the semiconductor substrate 201 can use a SADP (Self-Aligned Double Patterning) process, a SARP (Self-Aligned Reverse Patterning) process, or a SAQP (Self-Aligned Quadruple Patterning) process to accurately control the position and topography of the first trenches 202.

[0082] As shown in FIG. 3, the first trenches 202 are filled with an insulating material 204. Exemplarily, the material of the insulating material 204 includes but is not limited to one or more of silicon oxide, silicon nitride, or silicon oxynitride. Figure 7B Figure 7C The process of filling the first trenches 202 with the insulating material 204 can include any process known in the art, including but not limited to CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), sputtering, or ALD (Atomic Layer Deposition).

[0083] The process of filling the first trenches 202 with the insulating material 204 can include any process known in the art, including but not limited to CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), sputtering, or ALD (Atomic Layer Deposition).

[0084] ​​In some embodiments, before filling the first trench 202 with the insulating material 204, the first type of doping ions and the second type of doping ions are respectively implanted into different regions of the first initial active pillar 203 to form a first initial active pillar comprising a first active region, a channel region and a second active region distributed from bottom to top.

[0085] As shown, a first etching operation is performed to form a second trench extending along the first direction in the semiconductor substrate 201 filled with the insulating material 204, the second trench comprising a third sub-trench 205 and a fourth sub-trench 206, the third sub-trench 205 being located between two second initial active pillars 207 adjacent along the third direction, and the fourth sub-trench 206 being located between two insulating materials 204 adjacent along the third direction; the first etching operation uses an etching source with different etching selectivity for the semiconductor substrate 201 and the insulating material 204. Figure 7D In some embodiments, a second etching operation is performed on the second trench to form a third trench, the first trench and the third trench dividing the semiconductor substrate into a plurality of active pillars; the etching source used in the first etching operation is different from the etching source used in the second etching operation; wherein each third trench comprises a first sub-trench and a second sub-trench arranged alternately in the first direction; wherein the first depth of the first sub-trench in the second direction is different from the second depth of the second sub-trench in the second direction.

[0086] In some embodiments, before performing the second etching operation, a protective layer is formed at least on the top of the semiconductor substrate; forming the protective layer at least on the top of the semiconductor substrate comprises: before performing the second etching operation, in-situ oxidation is performed on the semiconductor substrate with the third trench formed thereon to form an oxide layer on the top of the semiconductor substrate, the sidewall and the bottom of the first sub-trench; the oxide layer covering the top of the semiconductor substrate is used as the protective layer; wherein during the second etching operation, the oxide layer covering the bottom of the first sub-trench is removed.

[0087] In some embodiments, in combination with

[0088] and Figure 7D , before performing the second etching operation, in-situ oxidation is performed on the semiconductor substrate 201 with the second trench formed thereon to form an oxide layer on the top of the semiconductor substrate 201, the sidewall and the bottom of the third sub-trench 205, i.e. to form an oxide layer 208 on the top of the semiconductor substrate 201, the sidewall and the bottom of the third sub-trench 205. The oxide layer 208 covering the top of the semiconductor substrate 201 is used as the protective layer to protect the top of the second initial active pillar 207 from being damaged in subsequent processes. Figure 7E In combination with

[0089] and Figure 7E , before performing the second etching operation, in-situ oxidation is performed on the semiconductor substrate 201 with the second trench formed thereon to form an oxide layer on the top of the semiconductor substrate 201, the sidewall and the bottom of the third sub-trench 205, i.e. to form an oxide layer 208 on the top of the semiconductor substrate 201, the sidewall and the bottom of the third sub-trench 205. The oxide layer 208 covering the top of the semiconductor substrate 201 is used as the protective layer to protect the top of the second initial active pillar 207 from being damaged in subsequent processes. Figure 7FA second etching operation is performed on the second trench to form a third trench. The first trench and the third trench divide the semiconductor substrate 201 into a plurality of active pillars 22. The etching source used in the first etching operation is different from the etching source used in the second etching operation. Each third trench includes a first sub-trench 209 and a second sub-trench 210 alternately arranged in a first direction. The first depth L1 of the first sub-trench 209 in the second direction is different from the second depth L2 of the second sub-trench 210 in the second direction.

[0090] like Figure 7F As shown, during the second etching operation, the oxide layer covering the bottom of the second trench is removed. It can be understood that after the second etching operation, the bottom of the oxide layer is flush with the bottom of the second sub-trench 210 of the second trench. This prevents the oxide layer at the bottom of the second trench from becoming a channel for short circuits between adjacent word lines in subsequent processes.

[0091] Furthermore, the etching source used in the second etching operation can further etch the semiconductor substrate at the location where the oxide layer at the bottom of the second trench is removed. It is understood that after the second etching operation, the bottom of the oxide layer is higher than the bottom of the second sub-trench 210 of the second trench. Thus, while increasing the depth of the second trench, conditions are created for completely isolating the oxide layer on the sidewalls of the second trench in subsequent processes. In some embodiments, the etching rate of the etching source used in the first etching operation on the semiconductor substrate 201 is greater than the etching rate on the insulating material 204; the etching rate of the etching source used in the second etching operation on the insulating material 204 is greater than the etching rate on the semiconductor substrate 201.

[0092] For example, when the first etching operation uses hydrogen fluoride (HF) gas as the etching source, the semiconductor substrate is a silicon substrate, and the insulating material is silicon oxide, the hydrogen fluoride gas can effectively react with the silicon substrate to generate gaseous silicon hexafluoride (SiF6). Therefore, the etching rate of the hydrogen fluoride gas on the silicon substrate is greater than that of the silicon oxide.

[0093] In other embodiments, when nitrogen trifluoride (N2O) gas, other fluoride gases such as sulfur difluoride (SF2) gas, sulfur hexafluoride (SF6) gas, or nitrogen trifluoride (NF3) gas are used as the etching source for the first etching operation, the etching rate of the etching source on the semiconductor substrate is greater than the etching rate on the insulating material.

[0094] Exemplarily, the second etching operation uses a carbon tetrafluoride (CF2) gas mixed with a certain concentration of oxygen (O2) as the etching source, the semiconductor substrate is a silicon substrate, and the insulating material is silicon oxide. In this case, the etching rate of the etching source on the insulating material is greater than the etching rate on the semiconductor substrate. In a specific embodiment, when the mixed gas of carbon tetrafluoride gas and oxygen is used as the etching source, the concentration of oxygen is greater than 20%.

[0095] As shown in FIG. 2A, the first sub-trench 209 is located between two adjacent active pillars 22 along the third direction, and the second sub-trench 210 is located between two adjacent insulating materials 204 along the third direction. Figure 7F

[0096] In some embodiments, the first depth L1 is less than the second depth L2.

[0097] In some embodiments, the ratio of the difference AL between the first depth L1 and the second depth L2 to the second depth L2 ranges from 1 / 10 to 1 / 5. More specifically, the ratio of the difference AL between the first depth L1 and the second depth L2 to the second depth L2 can be 1 / 10, 1 / 9, 1 / 8, 1 / 7, 1 / 16, or 1 / 5.

[0098] In some embodiments, the first depth L1 ranges from 80 nm to 150 nm, and the second depth L2 ranges from 90 nm to 250 nm. Exemplarily, the first depth L1 is 100 nm, and the second depth L2 is 120 nm.

[0099] In some embodiments, the ratio of the opening size of the top of the second sub-trench along the first / third direction to the opening size of the bottom of the second sub-trench along the first / third direction ranges from 5:2 to 3:2.

[0100] As shown in FIG. 2A, L3 is the opening size of the top of the second sub-trench 210 along the third direction, and L4 is the opening size of the bottom of the second sub-trench 210 along the third direction. The ratio of L3 to L4 ranges from 5:2 to 3:2. More specifically, the ratio of L3 to L4 can be 5:2, 4:2, or 3:2. Figure 7F In some embodiments, the opening size of the top of the second sub-trench 210 along the third direction is 25 nm, and the opening size of the bottom of the second sub-trench 210 along the third direction is 10 nm.

[0101] In some embodiments, the opening size of the top of the second sub-trench 210 along the third direction is 21 nm, and the opening size of the bottom of the second sub-trench 210 along the third direction is 14 nm.

[0102] In some embodiments, the opening size of the top of the second sub-trench 210 along the third direction is 21 nm, and the opening size of the bottom of the second sub-trench 210 along the third direction is 14 nm.

[0103] ​This embodiment of the present disclosure successfully widens and deepens the fourth sub-trench 206 in the second trench by performing a second etching operation on the second trench. The third trench formed by the second etching operation has a better morphology and can effectively prevent tip discharge problems. While improving the stability of the semiconductor device in which the semiconductor structure is located, it also creates favorable conditions for effective isolation of adjacent word lines in subsequent processes.

[0104] like Figure 7G As shown, the third trench is filled with an isolation material 25; the top of the isolation material 25 is flush with the top of the active pillar 22. The material of the isolation material 25 includes, but is not limited to, silicon nitride, and one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or combinations thereof, can be used to fill the third trench with the isolation material 25.

[0105] like Figure 7H As shown, the oxide layer and insulating material on the sidewall of the third trench are etched back for the first time to form the third gap 30 and the fourth gap 31. The process of the first etch back includes, but is not limited to, dry etching.

[0106] like Figure 7I As shown, an isolation layer 24 is formed at the part of the material removed during the first etch (the third gap 30 and the fourth gap 31); the isolation material 24 below the bottom of the isolation layer 24 forms a word line isolation structure.

[0107] In some embodiments, the materials of the isolation layer 24 and the isolation material 25 may be the same or different. The isolation layer 24 can protect the second active region of the active pillar and prevent subsequent processes from damaging the second active region of the active pillar and affecting the conductivity of the active pillar.

[0108] like Figure 7J As shown, a second etching process is performed on the oxide layer and insulating material on the sidewall of the third trench to form the fourth gap 33 and the fifth gap 34. The second etching process includes, but is not limited to, wet etching and dry etching processes. Combined with... Figure 3 , Figure 7J and Figure 7K Word lines are formed at the material removal sites during the second etch (fourth gap 33 and fifth gap 34); the remaining oxide layer on the sidewall of the third trench forms the first insulating structure 28.

[0109] Preferably, the bottom of the first insulating structure is higher than the bottom of the insulating material.

[0110] In some embodiments, since Figure 7F The second etching operation shown removes the bottom oxide layer and further deepens the second trench. Figure 7GThe bottom of the isolation material 25 is lower than the bottom of the oxide layer on both sides of the isolation material 25, i.e. the isolation material 25 can completely isolate the oxide layer. Therefore, when the fifth gap 34 is formed in the Figure 7J , even if over-etching occurs, the fifth gap 34 on both sides of the isolation material 25 in the third direction cannot be connected, and thus when the word line is formed in the Figure 7K , short circuit of adjacent word lines can be avoided. In some embodiments, before forming the word line, the semiconductor substrate is in-situ oxidized to form a second insulating structure 23 covering two sidewalls of the active pillar arranged opposite in the first direction and two sidewalls of the active pillar arranged opposite in the third direction; after forming the second insulating structure 23, a conductive material is filled in the material removed by the second time of over-etching to form the word line. Exemplarily, the conductive material includes but is not limited to tungsten, cobalt, copper, aluminum, gold, silver, nickel or polysilicon, etc.

[0111] It can be understood that the second insulating structure 23 and the conductive material together form the word line as the gate oxide layer.

[0112] In some embodiments, as shown in Figure 7K , after forming the word line, a cap layer 26 covering the word line is formed. The material of the cap layer 26 can be silicon nitride.

[0113] Figure 8 A cross-sectional schematic diagram of a process step of forming a protective layer on the top of the semiconductor substrate before performing the second etching operation is provided for another embodiment of the present disclosure. Figure 8 This step is shown from the four directions of aa', bb', cc' and dd' in Figure 3 . The process step will be described below in combination with Figures 7A-7D and Figure 8 . Figures 7A-7D The process step shown can refer to the description in the embodiments of the present disclosure and will not be described here again.

[0114] Forming the protective layer on the top of the semiconductor substrate includes: forming a dielectric layer on the top of the semiconductor substrate and the sidewall and bottom of the second trench before performing the second etching operation; taking the dielectric layer covering the top of the semiconductor substrate as the protective layer; wherein during the second etching operation, the dielectric layer covering the bottom of the second trench is removed.

[0115] Exemplarily, as shown in Figure 8 , before performing the second etching operation, a dielectric layer 32 is formed on the top of the semiconductor substrate 201 and the sidewall and bottom of the second trench; the dielectric layer 32 covering the top of the semiconductor substrate 201 is taken as the protective layer for protecting the top of the second initial active pillar 207 from being damaged in the subsequent process.

[0116] Exemplarily, the material of the medium layer 32 includes, but is not limited to, carbon, silicon nitride, etc.

[0117] Next, a second etching operation is performed to form a third trench, and the specific process can refer to the related description of Figure 7F .

[0118] The subsequent process further includes filling an isolation material in the third trench; the top of the isolation material is flush with the top of the active pillar; performing a first back etching on the medium layer and the insulating material of the third trench sidewall, and forming an isolation layer at the material removal part of the first back etching; the isolation material below the bottom of the isolation layer forms a word line isolation structure; performing a second back etching on the medium layer and the insulating material of the third trench sidewall, and forming a word line at the material removal part of the second back etching; the remaining medium layer of the third trench sidewall forms a first insulating structure. Before forming the word line, in-situ oxidation is performed on the semiconductor substrate to form a second insulating structure covering two sidewalls of the active pillar arranged in the second direction and two sidewalls of the active pillar arranged in the third direction; after forming the second insulating structure, conductive material is filled in the material removal part of the second back etching to form the word line. The subsequent process can refer to the related description of Figures 7F-7K and Figure 3 , which will not be repeated here.

[0119] The word line isolation structure in the embodiment of the present disclosure extends in the first direction and is located between adjacent word lines, and includes a first isolation structure and a second isolation structure alternately arranged in the first direction; wherein the first size of the first isolation structure in the second direction is different from the second size of the second isolation structure in the second direction; the second direction is parallel to the direction in which the active pillar extends. The different settings of the first size and the second size can meet the corresponding topography requirements of the word line isolation structure in different environmental materials, so that the word line isolation structure has a better topography in the direction in which the active pillar extends, can effectively isolate adjacent word lines, avoid the short circuit problem of adjacent word lines, and also effectively prevent the problem of sharp tip discharge, thereby improving the stability of the semiconductor device in which the semiconductor structure is located.

[0120] It should be noted that only common memories are exemplarily listed here, and the protection scope of the present disclosure is not limited thereto, and any memory containing the semiconductor device provided by the embodiment of the present disclosure belongs to the protection scope of the present disclosure.

[0121] The above description is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure, and any equivalent structural transformation made under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor structure, comprising: a plurality of active pillars arranged in an array; a plurality of word lines; the word lines extend along a first direction and cover sidewalls of the active pillars in a same row arranged along the first direction; the first direction is perpendicular to a direction in which the active pillars extend; a plurality of word line isolation structures; the word line isolation structures extend along the first direction and are located between adjacent word lines, and comprise first isolation structures and second isolation structures arranged alternately along the first direction; wherein a first dimension of the first isolation structures along a second direction is different from a second dimension of the second isolation structures along the second direction; the second direction is parallel to the direction in which the active pillars extend; the first isolation structures are located between two active pillars adjacent along a third direction, and the second isolation structures are located between two interval structures adjacent along the third direction, the interval structures being located between two active pillars adjacent along the first direction; the third direction is perpendicular to the second direction and intersects the first direction; the first dimension is smaller than the second dimension. 2.The semiconductor structure of claim 1, wherein: the word lines comprise first conductive structures and second conductive structures arranged alternately along the first direction; wherein the first conductive structures cover part of surfaces of two sidewalls of the active pillars arranged oppositely along a third direction, and the second conductive structures connect two first conductive structures adjacent along the first direction; the first isolation structures are located between two first conductive structures adjacent along the third direction, and the second isolation structures are located between two second conductive structures adjacent along the third direction. 3.The semiconductor structure of claim 2, wherein: a dimension of the first isolation structures along the second direction is greater than a dimension of the first conductive structures along the second direction; the semiconductor structure further comprises a first insulating structure, the first insulating structure partially surrounds a part of the first isolation structures extending beyond the first conductive structures along the second direction. 4.The semiconductor structure of claim 3, wherein: a bottom of the first insulating structure is not higher than a bottom of the first isolation structures. 5.The semiconductor structure of claim 2, wherein: the semiconductor structure further comprises a second insulating structure, the second insulating structure comprises a first part and a second part; wherein the first part is located between the first conductive structures and two sidewalls of the active pillars arranged oppositely along a third direction, and the second part is located between two second conductive structures adjacent along the first direction and two sidewalls of the active pillars arranged oppositely along the first direction. 6.A method for forming a semiconductor structure, comprising: forming a plurality of active pillars arranged in an array; forming a plurality of word lines extending along a first direction; the word lines cover sidewalls of the active pillars in a same row arranged along the first direction; the first direction is perpendicular to a direction in which the active pillars extend; ​ ​ A word line isolation structure extending along the first direction is formed between two adjacent word lines; the word line isolation structure comprises first isolation structures and second isolation structures arranged alternately along the first direction; wherein a first dimension of the first isolation structure along a second direction is different from a second dimension of the second isolation structure along the second direction; the second direction is parallel to a direction in which the active pillar extends; The first isolation structure is located between two adjacent active pillars along a third direction, and the second isolation structure is located between two adjacent spacer structures along the third direction, the spacer structure being located between two adjacent active pillars along the first direction; the third direction is perpendicular to the second direction and intersects the first direction; The first dimension is smaller than the second dimension.

7. The forming method of claim 6, wherein, forming the active pillars comprises: providing a semiconductor substrate; forming a plurality of first trenches extending along a third direction in the semiconductor substrate, and filling insulating material in the first trenches; the third direction is perpendicular to the second direction and intersects the first direction; performing a first etching operation to form second trenches extending along the first direction in the semiconductor substrate filled with insulating material; the first etching operation uses etching sources with different etching selectivity ratios for the semiconductor substrate and the insulating material; performing a second etching operation on the second trenches to form third trenches, the first trenches and the third trenches dividing the semiconductor substrate into a plurality of active pillars; the etching source used by the first etching operation is different from the etching source used by the second etching operation; wherein each of the third trenches comprises first sub-trenches and second sub-trenches arranged alternately along the first direction; wherein a first depth of the first sub-trenches along the second direction is different from a second depth of the second sub-trenches along the second direction.

8. The forming method of claim 7, wherein, the etching source used by the first etching operation has a greater etching rate for the semiconductor substrate than for the insulating material; the etching source used by the second etching operation has a greater etching rate for the insulating material than for the semiconductor substrate; the first sub-trenches are located between two adjacent active pillars along the third direction, and the second sub-trenches are located between two adjacent insulating materials along the third direction; the first depth is smaller than the second depth.

9. The forming method of claim 8, wherein, the method further comprises: forming a protective layer on at least the top of the semiconductor substrate before performing the second etching operation; forming the protective layer on at least the top of the semiconductor substrate comprises: In a second etching operation, the semiconductor substrate with the second trench is in-situ oxidized to form an oxide layer on the top of the semiconductor substrate, the sidewall and the bottom of the second trench between two adjacent active pillars along the third direction; the oxide layer covering the top of the semiconductor substrate is used as the protection layer; wherein during the second etching operation, the oxide layer covering the bottom of the second trench is removed; Alternatively, In a second etching operation, a dielectric layer is formed on the top of the semiconductor substrate and the sidewall and the bottom of the second trench; the dielectric layer covering the top of the semiconductor substrate is used as the protection layer; wherein during the second etching operation, the dielectric layer covering the bottom of the second trench is removed.

10. The forming method of claim 9, wherein The word line and the word line isolation structure are formed by: Filling the third trench with an isolation material; the top of the isolation material is flush with the top of the active pillar; First back-etching the oxide layer / dielectric layer and the insulating material of the sidewall of the third trench, and forming an isolation layer at the part where the material is removed by the first back-etching; the isolation material below the bottom of the isolation layer forms the word line isolation structure; Second back-etching the oxide layer / dielectric layer and the insulating material of the sidewall of the third trench, and forming the word line at the part where the material is removed by the second back-etching; the remaining oxide layer / dielectric layer of the sidewall of the third trench forms a first insulating structure.

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