Method for improving stability of eSTM Flash selection gate transistor
By depositing a polysilicon layer in the eSTM Flash selection gate transistor and etching to form a select gate structure, the problem of trench depth fluctuations affecting the stability of working performance is solved, and higher working stability and more uniform source-end impurity concentration distribution are achieved.
Patent Information
- Application Number
- CN202510169573.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-06-10
AI Technical Summary
The operating performance stability of the existing eSTM Flash select gate transistors is affected by fluctuations in the depth of the trench, resulting in uneven distribution of impurity concentration at the source, and the vertical transistor Id is offset by a large offset, and the offset exceeds 25%.
By depositing a polysilicon layer in the semiconductor structure, and etching the hard mask layer and the polysilicon layer according to a preset pattern, a select gate structure is formed, and a gate oxide layer is formed on the side walls of the polysilicon layer, unnecessary pad oxide layer is removed, an epitaxial layer is formed and planarized, and finally a well region and gate structure are formed on the surface of the epitaxial layer.
By precisely controlling the gate height of the selection gate transistor, the operating stability of the selection gate transistor is improved, the uneven distribution of impurity concentration at the source is reduced, and the offset of the vertical transistor Id is reduced.
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Figure CN120129243A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a method for improving the stability of the select gate transistor of eSTM Flash. Background Art
[0002] As Figure 1 shown, the 40nm node eSTM (floating gate embedded trench memory) Flash uses a trench transistor as the select gate transistor, and compared with the traditional ETOX (floating gate technology) structure Flash device, the area is reduced. This structure introduces a trench, and polysilicon is formed in the trench to form a trench transistor. The source end of the trench transistor needs to be led out from the N-well at the bottom of the trench. However, taking the trench with a certain depth as a reference and performing TCAD (Technology Computer Aided Design) simulation with a certain step size for biasing shows that the peak concentration of the source end changes significantly (as Figure 2 shown). Moreover, when the trench depth changes , the Id offset of the vertical transistor is too large, and the offset exceeds 25% (see Table 1). It can be seen that the trench depth will greatly affect the source end impurity concentration distribution.
[0003] Table 1
[0004]
[0005] Moreover, when forming a trench using the current process method, there is no etch stop layer. Therefore, the fluctuation of the etched trench depth is difficult to be precisely controlled, thereby affecting the working performance stability of the select gate transistor. Summary of the Invention
[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for improving the stability of the select gate transistor of eSTM Flash, which is used to solve the problem that the working performance stability of the existing select gate transistor is affected.
[0007] To achieve the above purpose and other related purposes, the present invention provides a method for improving the stability of the select gate transistor of eSTM Flash, and the method includes:
[0008] Providing a semiconductor structure, which includes a substrate, an isolation well formed on the surface of the substrate, and a pad oxide layer formed on the surface of the isolation well;
[0009] Forming a polysilicon layer on the surface of the pad oxide layer, and forming a hard mask layer on the surface of the polysilicon layer;
[0010] Etch the hard mask layer and the polysilicon layer according to a preset pattern until the pad oxide layer is exposed to form a select gate structure;
[0011] Form a gate oxide layer on the sidewalls of the polysilicon layer of the select gate structure, and remove the pad oxide layer in the regions other than the two sides of the select gate structure to expose the isolation well;
[0012] Form an epitaxial layer on the surfaces of the isolation wells on both sides of the select gate structure, and perform planarization processing until the hard mask layer is exposed;
[0013] Perform ion implantation on the epitaxial layers on both sides of the select gate structure to form well regions on their surfaces, and form a gate structure above the well regions, and the gate structure includes a floating gate and a control gate located above the floating gate.
[0014] Optionally, the hard mask layer is a silicon nitride layer.
[0015] Optionally, the gate oxide layer is formed by ISSG growth process.
[0016] Optionally, before performing ion implantation on the epitaxial layers on both sides of the select gate structure to form the well regions on their surfaces, the method includes the step of forming a sacrificial oxide layer on the surfaces of the epitaxial layers.
[0017] Optionally, after forming the well regions, the method includes the steps of removing the sacrificial oxide layer and forming a tunneling oxide layer.
[0018] Optionally, the sacrificial oxide layer is removed by a wet process.
[0019] Optionally, the tunneling oxide layer is formed by a thermal oxidation process.
[0020] Optionally, the floating gate is formed on the surface of the tunneling oxide layer, and a dielectric layer is formed between the floating gate and the control gate.
[0021] Optionally, the method further includes the step of forming a drain region by ion implantation on the side of the gate structure away from the select gate structure.
[0022] Optionally, the method further includes the step of forming a contact hole above the drain region.
[0023] Optionally, the isolation well is an N-type doped isolation well.
[0024] Optionally, the epitaxial layer is a P-type epitaxial layer.
[0025] Optionally, the well region is an N well.
[0026] As described above, the method for improving the stability of the select gate transistor of eSTM Flash in the present invention controls the height of the gate of the select gate transistor more precisely by first depositing a polysilicon layer and then etching it, thereby improving the operating stability of the select gate transistor. Description of the Drawings
[0027] Figure 1 It shows a schematic cross-sectional structure diagram of a typical existing eSTM flash structure.
[0028] Figure 2 It shows a source end peak simulation result diagram of a select gate transistor formed by an existing method.
[0029] Figures 3 to 9 It shows a schematic cross-sectional structure diagram of the process of forming a select gate according to the present invention.
[0030] Figure 10 It shows a flowchart of the method for improving the stability of the select gate transistor of eSTM Flash according to the present invention.
[0031] Description of the Reference Numerals in the Drawings
[0032] 10: Semiconductor structure; 11: Substrate; 12: Isolation well; 13: Pad oxide layer; 20: Polysilicon layer; 30: Hard mask layer; 40: Gate oxide layer; 50: Epitaxial layer; 60: Well region; 70: Gate structure; 71: Floating gate; 72: Control gate; 73: Dielectric layer; 80: Tunneling oxide layer; 90: Metal barrier layer; 100: Drain region; 110: Contact hole Detailed Embodiments
[0033] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0034] Please refer to Figures 1 to 10 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation, the form, number, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout form may also be more complex.
[0035] As Figure 10As shown, this embodiment provides a method for improving the stability of the select gate transistor of eSTM Flash. The method includes: step 1), step 2), step 3), step 4), step 5) and step 6).
[0036] As Figure 3 shown, in step 1), a semiconductor structure 10 is provided, which includes a substrate 11, an isolation well 12 formed on the surface of the substrate 11, and a pad oxide layer 13 formed on the surface of the isolation well 12.
[0037] In this embodiment, the substrate 11 is a silicon substrate. In this embodiment, the isolation well 12 leads to a source region.
[0038] Specifically, the isolation well 12 is an N-type doped isolation well. In this embodiment, the isolation well 12 is formed by implanting N-type doping ions into the substrate 11.
[0039] As Figure 3 shown, in step 2), a polysilicon layer 20 is formed on the surface of the pad oxide layer 13, and a hard mask layer 30 is formed on the surface of the polysilicon layer 20.
[0040] In this embodiment, the material of the pad oxide layer 13 includes silicon oxide.
[0041] Specifically, the hard mask layer 30 is a silicon nitride layer.
[0042] As Figure 4 shown, in step 3), the hard mask layer 30 and the polysilicon layer 20 are etched according to a preset pattern until the pad oxide layer 13 is exposed to form a select gate structure.
[0043] As Figure 4 shown, in step 4), a gate oxide layer 40 is formed on the sidewalls of the polysilicon layer 20 of the select gate structure, and the pad oxide layer 13 in the regions other than both sides of the select gate structure is removed to expose the isolation well 12.
[0044] Specifically, the gate oxide layer 40 is formed by ISSG growth process. In this embodiment, the material of the gate oxide layer 40 includes silicon oxide.
[0045] As Figure 6 and Figure 7 shown, in step 5), an epitaxial layer 50 is formed on the surfaces of the isolation wells 12 on both sides of the select gate structure, and it is planarized until the hard mask layer 30 is exposed.
[0046] In this embodiment, the thickness of the formed epitaxial layer 50 is greater than the sum of the thicknesses of the polysilicon layer 20 and the hard mask layer 30, and covers the hard mask layer 30. When the epitaxial layer 50 is planarized, its height can be slightly lower than the height of the hard mask layer 30.
[0047] Specifically, the epitaxial layer 50 is a P-type epitaxial layer.
[0048] As Figure 8 and Figure 9 shown, in step 6), ion implantation is performed on the epitaxial layer 50 on both sides of the select gate structure to form a well region 60, and a gate structure 70 is formed above the well region 60, and the gate structure 70 includes a floating gate 71 and a control gate 72 located above the floating gate 71.
[0049] Specifically, before ion implantation is performed on the epitaxial layer 50 on both sides of the select gate structure to form the well region 60 on its surface, the method includes the step of forming a sacrificial oxide layer on the surface of the epitaxial layer 50.
[0050] In this embodiment, before the sacrificial oxide layer is formed, the method includes the step of removing the hard mask layer 30.
[0051] Specifically, the well region 60 is an N-well.
[0052] Specifically, the sacrificial oxide layer is removed by a wet process. In this embodiment, the material of the sacrificial oxide layer includes silicon oxide.
[0053] Specifically, after the well region 60 is formed, the method includes the steps of removing the sacrificial oxide layer and forming a tunneling oxide layer 80.
[0054] In this embodiment, the tunneling oxide layer 80 is formed on the surface of the N-type well region and on the surface of the polysilicon layer 20. When a metal barrier layer 90 is subsequently formed on the surface of the polysilicon layer 20, the tunneling oxide layer 80 formed on the surface of the polysilicon layer 20 will be removed.
[0055] Specifically, the tunneling oxide layer 80 is formed by a thermal oxidation process.
[0056] Specifically, the floating gate 71 is formed on the surface of the tunneling oxide layer 80, and a dielectric layer 73 is formed between the floating gate 71 and the control gate 72.
[0057] In this embodiment, the dielectric layer 73 includes an ONO layer (that is, a silicon oxide layer - a silicon nitride layer - a silicon oxide layer).
[0058] Specifically, the method further includes a step of forming a drain region 100 on a side of the gate structure 70 away from the select gate structure by ion implantation.
[0059] Specifically, the method further includes a step of forming a contact hole 110 above the drain region 100.
[0060] In this embodiment, a metal barrier layer 90 is formed in the drain region, and the contact hole 110 is formed on the surface of the metal barrier layer 90.
[0061] Further, a metal barrier layer 90 is formed on the surface of the polysilicon layer 20 of the select gate structure and the surface of the gate structure 70.
[0062] In summary, the method for improving the stability of the select gate transistor of the eSTM Flash of the present invention controls the height of the gate of the select gate transistor more precisely by first depositing a polysilicon layer and then etching it, thereby improving the working stability of the select gate transistor. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.
[0063] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for improving the stability of an eSTM Flash select gate transistor, characterized in that: The method comprises: A semiconductor structure is provided, comprising a substrate, an isolation well formed on a surface of the substrate, and a pad oxide layer formed on a surface of the isolation well; forming a polysilicon layer on a surface of the pad oxide layer, and forming a hard mask layer on a surface of the polysilicon layer; Etching the hard mask layer and the polysilicon layer according to a preset pattern until the pad oxide layer is exposed to form a select gate structure; forming a gate oxide layer on the sidewalls of the polysilicon layer of the select gate structure, and removing the pad oxide layer in the area other than the two sides of the select gate structure to expose the isolation well; forming an epitaxial layer on the surface of the isolation well at both sides of the select gate structure, and performing a planarization process on the surface until the hard mask layer is exposed; Ions are implanted into the epitaxial layer on both sides of the selection gate structure to form a well region on the surface thereof, and a gate structure is formed above the well region, wherein the gate structure includes a floating gate and a control gate located above the floating gate.
2. The method for improving the stability of the eSTM Flash select gate transistor according to claim 1, characterized in that: The hard mask layer is a silicon nitride layer.
3. The method for improving the stability of the eSTM Flash select gate transistor according to claim 1, characterized in that: The gate oxide layer is formed by an ISSG growth process.
4. The method for improving the stability of the eSTM Flash select gate transistor according to claim 1, characterized in that: Before ion implantation is performed on the epitaxial layer at both sides of the select gate structure to form the well region on the surface thereof, the method includes the step of forming a sacrificial oxide layer on the surface of the epitaxial layer.
5. The method for improving the stability of the eSTM Flash select gate transistor according to claim 4, characterized in that: After forming the well region, the method includes the steps of removing the sacrificial oxide layer and forming a tunneling oxide layer.
6. The method for improving the stability of the eSTM Flash select gate transistor according to claim 4, characterized in that: The sacrificial oxide layer is removed by a wet process.
7. The method for improving the stability of the eSTM Flash select gate transistor according to claim 5, characterized in that: The tunnel oxide layer is formed by a thermal oxidation process.
8. The method for improving the stability of the eSTM Flash select gate transistor according to claim 5, characterized in that: The floating gate is formed on the surface of the tunneling oxide layer, and a dielectric layer is formed between the floating gate and the control gate.
9. The method for improving the stability of the eSTM Flash select gate transistor according to claim 1, characterized in that: The method further comprises the step of forming a drain region on a side of the gate structure away from the selection gate structure by ion implantation.
10. The method for improving the stability of the eSTM Flash select gate transistor according to claim 9, characterized in that: The method further comprises the step of forming a contact hole above the drain region.
11. The method for improving the stability of the eSTM Flash select gate transistor according to claim 1, characterized in that: The isolation well is an N-type doped isolation well.
12. The method for improving the stability of the eSTM Flash select gate transistor according to claim 11, characterized in that: The epitaxial layer is a P-type epitaxial layer.
13. The method for improving the stability of the eSTM Flash select gate transistor according to claim 12, characterized in that: The well region is an N-well.