Sidewall forming method of SONOS memory

Abstract

The invention provides a method for forming a side wall of an SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory, which comprises the following steps of: providing a substrate, forming a first oxide layer on the logic region of the substrate, forming an ONO layer on the storage region, depositing a polycrystalline silicon layer, and forming a second oxide layer, a nitride layer and a third oxide layer which are sequentially stacked from bottom to top on the first oxide layer, the nitride layer and the third oxide layer, patterning the polycrystalline silicon layer by utilizing a photoetching and etching method to form a gate polycrystalline silicon layer on the logic region and the storage region; the exposed third oxide layer is removed so that the nitride layer below the third oxide layer is exposed, a fourth oxide layer is formed on the surface of the grid polycrystalline silicon layer, a first side wall located on the fourth oxide layer on the side wall of the grid polycrystalline silicon layer is formed, and the first side wall is made of nitride; oxidizing the first side wall and the exposed nitride layer into a fifth oxide layer; and forming a subsequent side wall structure by using a deposition and back etching method. On the basis that the substrate is not damaged, the ONO layer of the SONOS region and the first oxide layer of the logic region are completely etched, and an effective protection side wall is formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for forming sidewalls of a SONOS memory. Background Art

[0002] In the process development of embedded SONOS memories, the formation of sidewalls needs to take into account both MOS transistors in the logic region and SONOS transistors in the memory region, which poses some challenges. After gate etching and before sidewall formation, the remaining dielectric layer of the SONOS transistor is the ONO layer, while the remaining dielectric of the MOS transistor is SiO2. The sidewall process of the prior art is difficult to balance the SONOS transistor region and the MOS transistor region during etching:

[0003] 1. If over-etching in the logic region is ensured, the problem of SIN residue in the ONO layer in the SONOS region will occur, preventing the formation of metal silicide in the source / drain region, which will further lead to poor contact and inability to etch through the contact holes.

[0004] 2. If the ONO layer in the SONOS region is etched cleanly, excessive loss of the silicon substrate will occur in the logic region, resulting in poor source / drain junctions and increased leakage current of the logic device.

[0005] To solve the above problems, a new method for forming sidewalls of a SONOS memory needs to be proposed. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for forming sidewalls of a SONOS memory, which is used to solve the problem that it is difficult to balance the SONOS transistor region and the MOS transistor region during etching in the prior art.

[0007] To achieve the above purpose and other related purposes, the present invention provides a method for forming sidewalls of a SONOS memory, including:

[0008] Step 1: Provide a substrate, on which a logic region and a memory region are formed. A first oxide layer is formed in the logic region on the substrate, and an ONO layer is formed on the memory region. The ONO layer is composed of a second oxide layer, a nitride layer, and a third oxide layer stacked from bottom to top. Deposit a polysilicon layer, and then pattern the polysilicon layer by photolithography and etching methods to form gate polysilicon layers on the logic region and the memory region;

[0009] Step 2: Remove the exposed third oxide layer to expose the underlying nitride layer, form a fourth oxide layer on the surface of the gate polysilicon layer, and form a first sidewall on the fourth oxide layer on the sidewalls of the gate polysilicon layer. The material of the first sidewall is nitride;

[0010] Step 3: Oxidize the first sidewall and the exposed nitride layer to form a fifth oxide layer, with the nitride layer being completely oxidized.

[0011] Step 4: Form subsequent sidewall structures by means of deposition and re-etching.

[0012] Preferably, the method of patterning the polysilicon layer in Step 1 includes: forming a photoresist layer on the polysilicon layer; lithographically opening the photoresist layer to define the formation position of the gate polysilicon layer; patterning the polysilicon layer by etching to form the gate polysilicon layer; and removing the remaining photoresist layer.

[0013] Preferably, the etching method in Step 1 is dry etching.

[0014] Preferably, the exposed third oxide layer is removed by wet etching in Step 2.

[0015] Preferably, the fourth oxide layer is formed by thermal oxidation in Step 2.

[0016] Preferably, the thickness of the fourth oxide layer in Step 2 is 20 to 50 angstroms.

[0017] Preferably, the method of forming the first sidewall in Step 2 includes: depositing a first sidewall material layer and re-etching the first sidewall material layer to form the first sidewall.

[0018] Preferably, the thickness of the first sidewall in Step 2 is 60 to 100 angstroms.

[0019] Preferably, the first sidewall and the exposed nitride layer are oxidized to the fifth oxide layer by in-situ steam oxidation in Step 3.

[0020] Preferably, the method of forming the subsequent sidewall structures in Step 4 includes: sequentially depositing second and third sidewall material layers, where the second sidewall material layer is a nitride and the third sidewall material layer is an oxide; etching the second and third material layers, with the etching stopping on the fifth oxide layer, so that it remains at the sidewalls of the gate polysilicon layer to form a sidewall structure, with the fifth oxide layer on the upper surface of the gate polysilicon layer being exposed and the fifth oxide layer extending from the bottom end of the second sidewall being exposed; and continuing to etch to remove the fifth oxide layer on the upper surface of the gate polysilicon layer, the fourth oxide layer, and the first, second, and fifth oxide layers exposed on the substrate.

[0021] Preferably, the second and third sidewall material layers are etched by dry etching in Step 4.

[0022] Preferably, in step four, the fifth oxide layer, the fourth oxide layer and the exposed first, second and fifth oxide layers on the upper surface of the gate polysilicon layer are etched away by wet etching.

[0023] Preferably, the thickness of the second sidewall material layer in step four is 150 to 300 angstroms.

[0024] Preferably, the thickness of the third sidewall material layer in step four is 200 to 700 angstroms.

[0025] Preferably, the method is used for processes with a technology node of 55 nm and below.

[0026] As described above, the sidewall formation method of the SONOS memory of the present invention has the following beneficial effects:

[0027] The present invention can completely etch the ONO layer in the SONOS region and the first oxide layer in the logic region without damaging the substrate, and form effective protection sidewalls for the SONOS and MOS transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of depositing the ONO sidewall shown as the prior art;

[0029] Figure 2 Schematic diagram of the structure after etching the ONO sidewall shown as the prior art;

[0030] Figure 3 Schematic diagram of the process flow of the present invention;

[0031] Figure 4 Schematic diagram of forming the gate polysilicon layer of the present invention;

[0032] Figure 5 Schematic diagram of removing the exposed third oxide layer of the present invention;

[0033] Figure 6 Schematic diagram of forming the fourth oxide layer of the present invention;

[0034] Figure 7 Schematic diagram of depositing the first sidewall material layer of the present invention;

[0035] Figure 8 Schematic diagram of etching the first sidewall material layer of the present invention;

[0036] Figure 9 Schematic diagram of oxidizing the first sidewall and the exposed nitride layer into the fifth oxide layer of the present invention;

[0037] Figure 10 Schematic diagram of depositing the second and third sidewall material layers of the present invention;

[0038] Figure 11 It shows a schematic diagram of the first etching for forming the sidewall structure of the present invention;

[0039] Figure 12 It shows a schematic diagram of the second etching for forming the sidewall structure of the present invention. Specific embodiments

[0040] The following uses specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Please refer to Figure 3 , the present invention provides a method for forming sidewalls of a SONOS memory, including:

[0042] Step 1: Provide a substrate 1, on which there are a logic region and a storage region. A first oxide layer 2 is formed in the logic region on the substrate 1, and an ONO layer 3 is formed on the storage region. The ONO layer 3 is composed of a second oxide layer, a nitride layer, and a third oxide layer stacked in sequence from bottom to top. Deposit a polysilicon layer, and then use photolithography and etching methods to pattern the polysilicon layer to form a gate polysilicon layer 4 on the logic region and the storage region, forming a structure as Figure 4 shown; in various embodiments of the present invention, the material of the oxide layer can be silicon dioxide, and the material of the nitride layer can be silicon nitride;

[0043] In some embodiments, the method for patterning the polysilicon layer in Step 1 includes: forming a photoresist layer on the polysilicon layer; opening the photoresist layer by photolithography to define the formation position of the gate polysilicon layer 4; using etching to pattern the polysilicon layer to form the gate polysilicon layer 4; removing the remaining photoresist layer, and the photoresist layer can be removed by ashing process, wet cleaning and other methods.

[0044] In some embodiments, the etching method in Step 1 is dry etching.

[0045] Step 2: Remove the exposed third oxide layer to expose the nitride layer below, forming a structure as Figure 5 shown, form a fourth oxide layer 5 on the surface of the gate polysilicon layer 4, forming a structure as Figure 6 shown, form a first sidewall 6 on the sidewall of the fourth oxide layer 5 on the gate polysilicon layer 4. The material of the first sidewall 6 is nitride, forming a structure as Figure 8 shown;

[0046] In some embodiments, in step two, the exposed third oxide layer is removed by wet etching.

[0047] In some embodiments, in step two, a fourth oxide layer 5 is formed by thermal oxidation, which is used to repair the etching loss of the gate polysilicon layer 4.

[0048] In some embodiments, the thickness of the fourth oxide layer 5 in step two is 20 to 50 angstroms.

[0049] In some embodiments, the method for forming the first sidewall 6 in step two includes: depositing a first sidewall 6 material layer to form a structure as Figure 7 shown, and then re-etching the first sidewall 6 material layer to form the first sidewall 6.

[0050] In some embodiments, the thickness of the first sidewall 6 in step two is 60 to 100 angstroms, and an oxide layer with a thickness of about 100 angstroms can be formed by oxidation later.

[0051] Step three: Oxidize the first sidewall 6 and the exposed nitride layer to form a fifth oxide layer 7. The nitride layer needs to be completely oxidized, and the first sidewall 6 does not have to be completely oxidized, forming a structure as Figure 9 shown. The residual ONO layer 3 in the SONOS region is converted into the same oxide as that in the logic region, and the oxide generated by oxidation can also act as the first layer of silicon oxide in the sidewall structure;

[0052] In some embodiments, in step three, the first sidewall 6 and the exposed nitride layer are oxidized to the fifth oxide layer 7 by in-situ steam oxidation. In-situ steam oxidation can also oxidize Si and polysilicon to oxides.

[0053] Step four: Form the subsequent sidewall structure by deposition and re-etching methods.

[0054] In some embodiments, the method for forming the subsequent sidewall structure in step four includes: sequentially depositing the second and third sidewall material layers. The second sidewall 8 material layer is a nitride, and the third sidewall 9 material layer is an oxide, forming a structure as Figure 10 shown; etching the second and third sidewall material layers, and stopping the etching on the fifth oxide layer 7 so that it remains at the sidewalls of the gate polysilicon layer 4 to form a sidewall structure. The fifth oxide layer 7 on the upper surface of the gate polysilicon layer 4 is exposed, and the fifth oxide layer 7 extending from the bottom end of the second sidewall 8 is exposed, forming a structure as Figure 11 shown; continuing to etch to remove the fifth oxide layer 7 on the upper surface of the gate polysilicon layer 4, the fourth oxide layer 5, and the exposed first, second, and fifth oxide layers on the substrate 1, and retaining the fifth oxide layer 7 as the first layer of the sidewall in the sidewall structure, forming a structure as Figure 12 shown.

[0055] In some embodiments, in step four, the second and third spacer material layers are etched by a dry etching method.

[0056] In some embodiments, in step four, the fifth oxide layer 7, the fourth oxide layer 5, and the exposed first, second, and fifth oxide layers on the upper surface of the gate polysilicon layer 4 are etched and removed by a wet etching method.

[0057] In some embodiments, the thickness of the second spacer 8 material layer in step four is 150 to 300 angstroms.

[0058] In some embodiments, the thickness of the third spacer 9 material layer in step four is 200 to 700 angstroms.

[0059] In some embodiments, the above method is used for processes with a technology node of 55 nm and below.

[0060] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0061] In summary, the present invention can completely etch the ONO layer in the SONOS region and the first oxide layer in the logic region without damaging the substrate, and form effective protective spacers for the SONOS and MOS transistors. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0062] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for forming a sidewall of a SONOS memory, characterized in that: At least: Step 1, providing a substrate, the substrate having a logic area and a storage area, a first oxide layer formed in the logic area of ​​the substrate, an ONO layer formed in the storage area, the ONO layer consisting of a second oxide layer, a nitride layer, and a third oxide layer stacked in sequence from bottom to top, depositing a polysilicon layer, and then patterning the polysilicon layer by photolithography and etching to form a gate polysilicon layer on the logic area and the storage area; Step 2: removing the exposed third oxide layer to expose the nitride layer thereunder, forming a fourth oxide layer on the surface of the gate polysilicon layer, and forming a first sidewall spacer located on the fourth oxide layer on the sidewall of the gate polysilicon layer, wherein the material of the first sidewall spacer is nitride; Step 3, oxidizing the first sidewall spacer and the exposed nitride layer to form a fifth oxide layer, wherein the nitride layer is completely oxidized; Step 4: Form a subsequent sidewall structure by using a deposition and back etching method.

2. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: The method for patterning the polysilicon layer in step 1 comprises: forming a photoresist layer on the polysilicon layer; opening the photoresist layer by photolithography to define the formation position of the gate polysilicon layer; patterning the polysilicon layer by etching to form the gate polysilicon layer; The remaining photoresist layer is removed.

3. The method for forming a sidewall of a SONOS memory according to claim 3, wherein: The etching method in step one is dry etching.

4. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: In step 2, the exposed third oxide layer is removed by wet etching.

5. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: In step 2, the fourth oxide layer is formed by thermal oxidation.

6. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: The thickness of the fourth oxide layer in step 2 is 20 to 50 angstroms.

7. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: The method for forming the first sidewall spacer in step 2 includes: depositing a first sidewall spacer material layer, and etching back the first sidewall spacer material layer to form a first sidewall spacer.

8. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: The thickness of the first sidewall spacer in step 2 is 60 to 100 angstroms.

9. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: In step three, the first sidewall spacer and the exposed nitride layer are oxidized into a fifth oxide layer by using an in-situ water vapor oxidation method.

10. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: The method for forming the subsequent sidewall structure in step four includes: depositing the second and third sidewall material layers in sequence, the second sidewall material layer is a nitride, and the third sidewall material layer is an oxide layer; etching the second and third material layers, and stopping the etching on the fifth oxide layer so that it remains at the sidewall of the gate polysilicon layer to form a sidewall structure, the fifth oxide layer on the upper surface of the gate polysilicon layer is exposed, and the fifth oxide layer extending from the bottom end of the second sidewall is exposed; continuing to etch and remove the fifth oxide layer and the fourth oxide layer on the upper surface of the gate polysilicon layer and the first, second and fifth oxide layers exposed on the substrate.

11. The method for forming a sidewall of a SONOS memory according to claim 10, wherein: In step 4, the second and third sidewall material layers are etched using a dry etching method.

12. The method for forming a sidewall of a SONOS memory according to claim 10, wherein: In step 4, the fifth oxide layer, the fourth oxide layer and the exposed first, second and fifth oxide layers on the upper surface of the gate polysilicon layer are etched away by a wet etching method.

13. The method for forming a sidewall of a SONOS memory according to claim 10, wherein: The thickness of the second spacer material layer in step 4 is 150 to 300 angstroms.

14. The method for forming a sidewall of a SONOS memory according to claim 10, wherein: The thickness of the third spacer material layer in step 4 is 200 to 700 angstroms.

15. The method for forming a sidewall of a SONOS memory device according to claim 1, wherein: The method is used for processes at technology nodes of 55nm and below.

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