IGBT (Insulated Gate Bipolar Translator) chip structure and manufacturing method

Abstract

The invention discloses an IGBT chip structure and a manufacturing method, and belongs to the technical field of semiconductor devices, the IGBT chip structure comprises a chip main body, a diamond layer and a collector metal layer, a porous two-dimensional network with a dense middle part and a sparse periphery is etched on the diamond layer, and metal aluminum is arranged in through holes of the porous two-dimensional network. The metal aluminum is connected with the chip main body and the collector metal layer to form a conductive path; the diamond layer with the porous two-dimensional network is additionally arranged between the chip main body and the collector metal layer, and the heat dissipation capability of the chip is enhanced by utilizing the high heat conductivity characteristic of diamond. Meanwhile, ohmic contact between back metal and a chip body is achieved through metal aluminum in pores of the porous two-dimensional network, the electrical connection requirement of the IGBT chip application working condition is met, and in addition, efficient preparation of the IGBT chip structure is achieved through the processes of diamond deposition, etching, modification and the like added in the manufacturing method and cooperation with the chip back technology.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to an IGBT chip structure and a manufacturing method thereof. Background Art

[0002] The existing chip heat dissipation methods mostly involve adding external heat dissipation structures. Common heat dissipation modes include natural heat dissipation, forced heat dissipation, liquid heat dissipation, refrigeration heat dissipation, diversion heat dissipation, and heat pipe heat dissipation, etc. However, with the increase in the total power density of IGBT applications and the reduction of the physical size of the chip, the conventional method of installing a radiator is difficult to meet the current heat dissipation requirements of electronic chips, and the radiator structure is extremely large and not conducive to the high integration of the chip.

[0003] To solve the above problems, the present invention provides an IGBT chip structure and a manufacturing method thereof to solve the problem of low heat dissipation efficiency of the chip structure in the prior art. Summary of the Invention

[0004] The present invention provides an IGBT chip structure and a manufacturing method thereof. By adding a diamond layer with a porous two-dimensional network between the chip body and the collector metal layer, the high thermal conductivity of the diamond layer can be used to improve the heat dissipation ability, and at the same time, the honeycomb structure with dense middle and sparse periphery can be used to match the heat generation area of the chip to achieve uniform temperature of the IGBT chip.

[0005] To achieve the above object, the technical solution adopted by the present invention is: The present invention discloses an IGBT chip structure, including a chip body, a diamond layer provided on the back of the chip body, and a collector metal layer provided on the back of the diamond layer. A porous two-dimensional network with dense middle and sparse periphery is etched on the diamond layer, and the inside of the porous two-dimensional network is filled with aluminum metal. Both the chip body and the collector metal layer are connected to the aluminum metal to form a conduction path.

[0006] Preferably, the diamond layer is a boron-doped diamond film.

[0007] Preferably, the thickness of the diamond layer is 1 um to 2 um.

[0008] Preferably, the chip body includes a drift layer and a collector layer sequentially arranged from the front to the back. An emitter metal region, a gate region, an N-type emitter region, and a P-type base region are provided on the front of the drift layer. The diamond layer is located between the collector layer and the collector metal layer.

[0009] Preferably, the drift layer is a phosphorus-doped silicon substrate layer, and the collector layer is a boron-doped silicon substrate layer.

[0010] Preferably, the collector metal layer includes an aluminum layer, a titanium layer, a nickel-vanadium alloy layer, and a silver layer that are sequentially connected from the front side to the back side, and the aluminum layer is connected to the diamond layer.

[0011] A manufacturing method of an IGBT chip structure is also disclosed, which is used to prepare the above-mentioned IGBT chip structure, and includes the following steps: Deposit a diamond layer on the back surface of the chip body; Etch a porous two-dimensional network with a dense middle and sparse periphery on the diamond layer, and fill metallic aluminum in the through holes of the porous two-dimensional network; Deposit a collector metal layer on the back surface of the etched diamond layer.

[0012] Preferably, before depositing the diamond layer, boron ions are implanted into the back surface of the chip body and then laser annealed to form a collector layer. A suspension is prepared by mixing diamond micropowder and absolute ethanol, and the surface of the collector layer is ultrasonically polished using the suspension, and then ultrasonically cleaned using distilled water and absolute ethanol.

[0013] Preferably, before etching the surface of the diamond layer, the surface of the diamond layer is cleaned using a wet chemical cleaning process; then a mask structure is formed by coating and depositing a film on the surface of the cleaned diamond layer using DC pulsed magnetron sputtering; a positive photoresist is coated on the surface of the mask structure, exposed to ultraviolet light, and then developed in a developer; nitric acid and phosphoric acid are used as corrosive acid solutions to remove the mask structure of the part where the positive photoresist is not attached, so that the mask structure is patterned, so as to etch the diamond layer to form a porous two-dimensional network subsequently.

[0014] Preferably, before depositing the collector metal layer, the surface of the diamond layer is modified: first, the surface of the chip body is cleaned using a wet chemical cleaning process; a tungsten coating is deposited on the surface of the diamond layer using magnetron sputtering.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention adds a diamond layer with high thermal conductivity between the back surface of the chip body and the collector metal layer to form a "silicon-diamond-metal" structure. The diamond layer has a porous two-dimensional network. The high thermal conductivity characteristic of diamond can enhance the heat dissipation ability of the chip. At the same time, the conductive characteristic of metallic aluminum in the porous two-dimensional network provides a current path for the IGBT chip to realize the normal operation of the chip, solves the problem of uneven heat distribution with a high temperature in the middle and a low temperature around due to poor heat dissipation performance during the operation of the IGBT chip, and reduces the device performance difference and the risk of reliability failure caused by uneven heat.

[0016] Compared with the prior art, other technical solutions of the present invention also have the following beneficial effects: The manufacturing method of the IGBT chip structure in the present invention is adapted to the current IGBT chip process flow, with simple process and high feasibility, and is suitable for popularization. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic structural diagram of an IGBT chip structure in an embodiment of the present invention; Figure 2 It is a schematic structural diagram of another IGBT chip structure in an embodiment of the present invention; Figure 3 It is a schematic structural diagram of the connection of the collector layer, diamond layer, and collector metal layer in an embodiment of the present invention; Figure 4 It is a schematic structural diagram of a porous two-dimensional network on the diamond layer in an embodiment of the present invention; Figure 5 It is a flowchart of the manufacturing method of the IGBT chip structure in an embodiment of the present invention.

[0019] Description of reference numerals: 1. Gate region; 2. Emitter metal region; 3. N-type emitter region; 4. P-type base region; 5. Drift layer; 6. Collector layer; 7. Diamond layer; 8. Collector metal layer; 9. Porous two-dimensional network; 10. Aluminum layer; 11. Titanium layer; 12. Nickel-vanadium alloy layer; 13. Silver layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0021] The present invention provides an IGBT chip structure and a manufacturing method to achieve the purpose of improving the heat dissipation efficiency of the chip. By adding a diamond layer with a porous two-dimensional network between the chip body and the collector metal layer, the high thermal conductivity of the diamond layer can be used to improve the heat dissipation ability, and at the same time, the honeycomb structure with dense middle and sparse periphery can be used to match the heat generation area of the chip to achieve uniform temperature of the IGBT chip.

[0022] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] Embodiment 1 As Figures 1 to 5 shown, this embodiment provides an IGBT chip structure, including a chip body, a diamond layer 7 disposed on the back surface of the chip body, and a collector metal layer 8 disposed on the back surface of the diamond layer 7. A porous two-dimensional network 9 that is dense in the middle and sparse around is etched on the diamond layer 7. The porous two-dimensional network 9 is a grid-like structure formed by arranging a plurality of through holes. Metal aluminum is disposed in each through hole of the porous two-dimensional network 9. The chip body and the collector metal layer 8 are both connected to the metal aluminum to form a conduction path. The density in the middle and sparseness around mainly rely on the aperture of a single through hole in the porous two-dimensional network 9. For example, the aperture of the through holes in the middle region is small, so it is dense, forming a middle dense region, while the aperture of the through holes in the surrounding region around the middle region is large, so it is sparse, forming a surrounding sparse region. The middle dense region needs to correspond and match with the middle high-heat region of the chip body, that is, the middle dense region needs to cover the middle high-heat region, and the surrounding sparse region needs to correspond and match with the surrounding low-heat regions of the chip body, and the surrounding sparse region needs to cover the surrounding low-heat regions. Specifically, the aperture sizes of the through holes in the middle dense region and the surrounding sparse region need to be set according to the heat generation amount of the chip body.

[0024] By depositing a conductive and highly thermally conductive diamond layer 7 structure on the back surface of the chip body and etching to form a porous two-dimensional network 9 that is dense in the middle and sparse around, the heat dissipation is enhanced by using the high thermal conductivity characteristic of diamond, and the uniform temperature of the IGBT chip is achieved by using the honeycomb structure design to increase the heat dissipation capacity in the middle. Aluminum metal is filled in the pores and combined with the chip body and the collector metal layer 8 to form a conduction path, realizing the ohmic contact between the collector metal layer 8 and the chip body, meeting the electrical connection requirements of the IGBT chip application working conditions. By using the high thermal conductivity characteristic of diamond, the heat dissipation capacity of the chip can be enhanced, solving the problem of uneven heat distribution in the IGBT chip during operation, where the middle has concentrated heat and high temperature while the surrounding has low temperature, and reducing the device performance difference and the risk of reliability failure caused by uneven heat. The application scope of this IGBT chip structure includes: trench-type IGBT (Insulated Gate Bipolar Transistor), planar gate-type IGBT, MOSFET (Metal Oxide Semiconductor Field Effect Transistor), diodes, thyristors and other silicon-based devices.

[0025] In one embodiment, the diamond layer 7 is a boron-doped diamond film. After doping boron into the diamond, the diamond layer 7 itself also has conductivity, thereby increasing the range of the conduction path between the chip body and the collector metal layer 8, which is indirectly beneficial for heat dissipation.

[0026] In one embodiment, the thickness of the diamond layer 7 is 1 um to 2 um.

[0027] In one embodiment, the chip body includes a drift layer 5 and a collector layer 6 arranged in sequence from the front to the back. The front of the drift layer 5 is provided with a gate region 1, an emitter metal region 2, an N-type emitter region 3, and a P-type base region 4. The diamond layer 7 is located between the collector layer 6 and the collector metal layer 8.

[0028] In one embodiment, the drift layer 5 is a phosphorus-doped silicon substrate layer, and the collector layer 6 is a boron-doped silicon substrate layer.

[0029] In one embodiment, the collector metal layer 8 includes an aluminum layer 10, a titanium layer 11, a nickel-vanadium alloy layer 12, and a silver layer 13 connected in sequence from the front to the back, wherein the aluminum layer 10 is connected to the diamond layer 7.

[0030] In one embodiment, the cross-sectional shape of a single through hole in the porous two-dimensional network 9 is a regular hexagon, so that the porous two-dimensional network is arranged in a honeycomb pattern. Of course, the cross-sectional shape of a single through hole in the porous two-dimensional network 9 can also be circular, rectangular or other shapes, which will not be elaborated here.

[0031] Example 2 As Figures 1 to 5 shown, this embodiment provides a manufacturing method of an IGBT chip structure for producing the IGBT chip structure in Example 1, including the following steps: Deposit the diamond layer 7 on the back of the chip body; Etch a porous two-dimensional network 9 with a dense middle and sparse periphery on the diamond layer 7, and fill the through holes in the porous two-dimensional network 9 with metallic aluminum; Deposit the collector metal layer 8 on the back of the etched diamond layer 7.

[0032] In one embodiment, before depositing the diamond layer 7, boron ions are implanted into the back of the chip body and laser annealed to form the collector layer 6. A suspension is prepared by mixing diamond micropowder and absolute ethanol, and the surface of the collector layer 6 is ultrasonically polished using the suspension, and then ultrasonically cleaned with distilled water and absolute ethanol.

[0033] In one embodiment, when depositing the diamond layer 7 on the back surface of the collector layer 6: First, deposit a 1-2 μm boron-doped diamond material on the collector layer 6, and then pattern the diamond thin film by dry etching to form the diamond layer 7 with a porous two-dimensional network 9 to provide a current conduction path. Then, deposit the collector metal layer 8 on the back surface of the diamond layer 7 to realize the electrode preparation of the chip.

[0034] In one embodiment, before etching the surface of the diamond layer 7, clean the surface of the diamond layer 7 using a wet chemical cleaning process; then coat the surface of the cleaned diamond layer 7 by DC pulsed magnetron sputtering to form a mask structure; coat the surface of the mask structure with a positive photoresist, expose it to ultraviolet light, and then develop it in a developer; use nitric acid and phosphoric acid as corrosive acid solutions to remove the mask structure of the part where the positive photoresist is not attached, so that the mask structure is patterned for subsequent etching of the diamond layer 7 to form the porous two-dimensional network 9.

[0035] In one embodiment, before depositing the collector metal layer 8, modify the surface of the diamond layer 7: First, clean the surface of the chip body using a wet chemical cleaning process to make the surface of the chip body free of organic contamination and particle attachment; deposit a tungsten coating on the surface of the diamond layer 7 by magnetron sputtering to inhibit the hydrolysis phenomenon at the bonding interface between the diamond layer 7 and the aluminum layer 10 and realize the surface modification of the diamond layer structure.

[0036] In one embodiment, it includes: 1. Back process ① Wafer thinning: After the front process of the chip body is completed, paste a protective film on the front of the chip body and thin the back to the specified thickness.

[0037] ② Collector implantation: Implant boron ions on the back surface and then perform laser annealing to form a doped boron collector metal layer 8.

[0038] 2. Deposit diamond layer ① Pretreatment: Prepare a suspension using about 1 μm diamond micropowder and absolute ethanol and ultrasonically grind the surface of the collector layer 6 using the suspension, and then ultrasonically clean it with distilled water and absolute ethanol for at least 10 min. The pretreatment is to increase the nucleation density of the diamond layer 7 on the collector layer 6 and at the same time enhance the adhesion strength between the diamond layer 7 and the collector layer 6.

[0039] ② Deposit diamond layer: Use microwave plasma chemical vapor deposition (MPCVD) to prepare a 1-2 μm boron-doped diamond thin film (diamond layer 7). Utilize the high thermal conductivity characteristic of diamond to enhance the heat dissipation of the chip, and utilize the low resistivity (10 -3 Ω·cm) formed by the boron-doped diamond layer 7 to reduce the application loss of the chip. Process parameters: The reaction gas is hydrogen (H 2) - Methane (CH 4 ) - Diborane (B 2 H 6 ) mixed gas, CH 4 , B 2 H 6 As a carbon source and a boron source, hydrogen gas is introduced into the reactor through a methane-diborane organic mixed liquid. The gas flow rates are 400 sccm for hydrogen, 24 sccm for methane, and 60 sccm for diborane. The deposition temperature is 900 °C, the pressure is 18 kPa, and the time is 10 h.

[0040] 3. Etching the diamond layer ① Cleaning: Use the standard wet chemical cleaning (RCA) process to clean and remove the surface of the wafer, so that there is no organic contamination and no particle attachment on the surface of the diamond layer 7, avoiding affecting the etching quality of the diamond layer 7 structure due to poor mask adhesion.

[0041] ② Aluminum mask plating: Use DC pulsed magnetron sputtering for coating. Sputter aluminum metal onto the surface of the diamond layer 7 in a high-purity argon gas environment to form a mask structure with a thickness of 150 - 200 nm, so that the diamond layer structure below the aluminum layer is not etched. Process parameters: Sputtering voltage - 250 V, target current 25 A, pulse duty cycle 50%. The vacuum pressure is 0.5×10 -3 Pa, temperature 150 °C.

[0042] ③ Exposure / development: Coat the surface of the aluminum film with a positive photoresist (positive resist), expose it with ultraviolet light with a wavelength of 405 nm, and then develop it in a developer. Use deionized water to rinse and remove the developer.

[0043] ④ Mask patterning: Wet etching process, use nitric acid and phosphoric acid as corrosive acid solutions to remove the aluminum layer where the photoresist is not attached, so that the aluminum layer is patterned, in order to etch the diamond layer subsequently to form a conductive porous two-dimensional network 9. Process parameters: The volume ratio of the wet etching solution is phosphoric acid (H 3 PO 4 ): nitric acid (HNO 3 ): acetic acid (CH 3 COOH): deionized water = 50:3:10:9, temperature 60 °C, time 5 min.

[0044] ⑤Etching: Use inductively coupled plasma (ICP) method to etch the diamond layer 7. According to the chip heat dissipation requirements, design the structure of the diamond layer 7 with a porous two-dimensional network 9 to enhance the chip heat dissipation capacity. The porous two-dimensional network 9 is filled with aluminum metal material to make the silicon wafer form an ohmic contact with the back metal. Process parameters: The gas atmosphere is 7 sccm of oxygen and 8 sccm of argon, the gas pressure is 0.3 Pa, the etching power is 600 W, the bias voltage is -160 V, and the etching time is 5 min to 10 min.

[0045] 4. Diamond surface modification ①Cleaning: Use the standard wet chemical cleaning (RCA) process to clean the surface of the chip body, so that there is no organic contamination and no particle attachment on the chip surface, and avoid affecting the bonding strength between the diamond and the back metal due to contamination.

[0046] ②Depositing a tungsten metal coating: Use magnetron sputtering to deposit a tungsten (W) coating of about 50 nm on the diamond surface to inhibit the hydrolysis phenomenon at the diamond / aluminum bonding interface, realize the surface modification of the diamond structure, and increase the interfacial bonding strength between the diamond layer and the back metal aluminum. Process parameters: The current of the magnetron sputtering process is 0.9 A, and the voltage is 600 V. The gas atmosphere is a constant argon environment, the vacuum pressure < 8×10 -3 Pa, the temperature is 300 °C, and the time is 200 min.

[0047] 5. Back metal deposition ①Aluminum metal deposition: Use magnetron sputtering to deposit about 100 nm of Al metal to form a diamond / Al interface and a Si / Al interface with high bonding strength and good ohmic contact, and reduce the working loss of the chip. Process parameters: The gas atmosphere is a constant Ar gas environment, and the gas flow rate is 100 sccm. The magnetron sputtering power is 6000 W, and the time is 10 s.

[0048] ②Titanium-nickel-silver metal deposition: Use magnetron sputtering to deposit a titanium metal layer with a thickness of about 100 nm, a nickel-vanadium alloy layer with a thickness of 400 nm, and a nickel-vanadium alloy layer with a thickness of 800 nm in sequence. The titanium layer 11 serves as a diffusion barrier layer, the nickel-vanadium alloy layer 12 is a solderable layer, and the silver layer 13 is a protective layer to prevent the nickel-vanadium alloy layer 12 from oxidation.

[0049] In one embodiment, the scheme for combining the diamond layer 7 with the collector layer 6: In addition to depositing the diamond layer by the microwave plasma chemical vapor deposition method described in the text, the hot filament chemical vapor deposition method, the direct current plasma chemical vapor deposition method, etc. can also be used.

[0050] In one embodiment, depositing boron-doped diamond reactants: In addition to hydrogen-methane (CH 4 )-diborane (B 2 H 6)In addition to the mixed gas, trimethylboron (B(CH 3 )) 3 ), trimethyl borate (B(OCH 3 )) 3 ) can be used as the boron source, and acetone (CH 3 COCH 3 ) can be used as the carbon source to prepare a boron-doped diamond structure. The resistivity of the boron-doped diamond depends on the carbon-boron ratio of the mixed gas, that is, the gas flow ratio of the carbon source and the boron source.

[0051] In one embodiment, the diamond surface modification scheme: to enhance the bonding strength of the diamond-aluminum interface, in addition to the chemical method of sputtering a tungsten coating on the diamond surface in the text, the diamond surface can also be treated by adding titanium, titanium carbide, tungsten carbide, silicon, and silicon carbide coatings; or by doping silicon, titanium, and other materials in the sputtered aluminum metal to form Al(Si) and Al(Ti) alloys.

[0052] The manufacturing method of the IGBT chip structure proposed in this embodiment does not conflict with the current front-end process of chip production. The key point of this embodiment is the cooperation between the processes of diamond deposition, etching, modification, etc. added in the process and the back-end process of the chip to realize the preparation of the "silicon-diamond-metal" three-layer heat dissipation structure (collector layer 6, diamond layer 7, and collector metal layer 8).

[0053] It should be noted that for those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention, and any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. An IGBT chip structure, characterized in that: It includes a chip body, a diamond layer arranged on the back of the chip body, and a collector metal layer arranged on the back of the diamond layer. A porous two-dimensional network with dense center and sparse surroundings is etched on the diamond layer. The porous two-dimensional network is filled with metal aluminum. The chip body and the collector metal layer are both connected to the metal aluminum to form a conductive path.

2. The IGBT chip structure according to claim 1, characterized in that: The diamond layer is a boron-doped diamond film.

3. The IGBT chip structure according to claim 2, characterized in that: The thickness of the diamond layer is 1 um to 2 um.

4. The IGBT chip structure according to any one of claims 1 to 3, characterized in that: The chip body includes a drift layer and a collector layer arranged in sequence from the front to the back, the front of the drift layer is provided with an emitter metal region, a gate region, an N-type emitter region and a P-type base region, and the diamond layer is located between the collector layer and the collector metal layer.

5. The IGBT chip structure according to claim 4, characterized in that: The drift layer is a phosphorus-doped silicon substrate layer, and the collector layer is a boron-doped silicon substrate layer.

6. The IGBT chip structure according to any one of claims 1 to 3, characterized in that: The collector metal layer includes an aluminum layer, a titanium layer, a nickel-vanadium alloy layer and a silver layer which are sequentially connected from the front side to the back side, and the aluminum layer is connected to the diamond layer.

7. A method for manufacturing an IGBT chip structure, characterized in that: The method for preparing the IGBT chip structure according to any one of claims 1 to 6 comprises the following steps: depositing a diamond layer on the back side of the chip body; Etching a porous two-dimensional network on the diamond layer, which is dense in the middle and sparse around, and filling metal aluminum in the through holes of the porous two-dimensional network; A collector metal layer is deposited on the back side of the etched diamond layer.

8. The method for manufacturing an IGBT chip structure according to claim 7, characterized in that: Before depositing the diamond layer, boron ions are injected into the back of the chip body and laser annealed to form a collector layer. Diamond micropowder and anhydrous ethanol are used to prepare a suspension and the suspension is used to ultrasonically grind the surface of the collector layer, and then distilled water and anhydrous ethanol are used for ultrasonic cleaning.

9. The method for manufacturing an IGBT chip structure according to claim 7, characterized in that: Before etching the surface of the diamond layer, the surface of the diamond layer is cleaned by a wet chemical cleaning process; and then a DC pulse magnetron sputtering method is used to coat the surface of the cleaned diamond layer and form a mask structure; A positive photoresist is used to coat the surface of the mask structure, which is exposed to ultraviolet light and then developed in a developer. Nitric acid and phosphoric acid are used as corrosive acid solutions to remove the mask structure where the positive photoresist is not attached, so that the mask structure is patterned so that the diamond layer can be subsequently etched to form a porous two-dimensional network.

10. The method for manufacturing an IGBT chip structure according to claim 7, characterized in that: Before the collector metal layer is deposited, the surface of the diamond layer is modified: first, a wet chemical cleaning process is used to clean the surface of the chip body; and a tungsten coating is deposited on the surface of the diamond layer by a magnetron sputtering method.

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