Silicon controlled rectifier integrated with heterojunction bipolar transistor

Abstract

The invention relates to a semiconductor structure, and more particularly relates to a silicon controlled rectifier integrated with a heterojunction bipolar transistor and a manufacturing method. The structure includes: a first region disposed in a semiconductor substrate and including a first dopant type; a second region disposed in the semiconductor substrate and including a second dopant type; an isolation region between the first region and the second region; a first semiconductor layer vertically contacting the first region, the first semiconductor layer having a dopant type opposite to the first dopant type; a second semiconductor layer vertically contacting the second region, the second semiconductor layer having a dopant type opposite to the second dopant type; a polycrystalline material vertically contacting the first semiconductor layer; and a single crystal semiconductor material vertically contacting the first semiconductor layer and the second semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly, to silicon controlled rectifiers integrated with heterojunction bipolar transistors and manufacturing methods thereof. Background Art

[0002] SCRs are used for electrostatic discharge (ESD) protection of integrated circuits (ICs) to prevent sudden currents caused by, for example, contact, electrical short circuits, or dielectric breakdown. Due to the high current handling capacity per unit area of SCRs, ESD devices using SCRs can protect integrated circuits from faults. These devices are most commonly used in high-performance analog and radio frequency (RF) designs for chips with large signal swings, low leakage, and low capacitance. For example, SCRs can be used to protect antenna ports. The radio frequency (RF) performance may be affected due to the capacitive load and poor harmonics of SCRs. Summary of the Invention

[0003] In one aspect of the present disclosure, a structure includes: a first region disposed in a semiconductor substrate and including a first dopant type; a second region disposed in the semiconductor substrate and including a second dopant type; an isolation region located between the first region and the second region; a first semiconductor layer vertically contacting the first region, the first semiconductor layer having a dopant type opposite to the first dopant type; a second semiconductor layer vertically contacting the second region, the second semiconductor layer having a dopant type opposite to the second dopant type; a polycrystalline material vertically contacting the first semiconductor layer; and a second semiconductor material having a doping type opposite to the first polycrystalline layer and vertically contacting the first semiconductor layer and the second semiconductor layer.

[0004] In one aspect of the present disclosure, a structure includes: a heterojunction bipolar transistor integrated with a silicon controlled rectifier, both sharing doped semiconductor material above a lower semiconductor substrate, the doped semiconductor material serving as the base of the heterojunction bipolar transistor and being isolated from a lower well having the same dopant type by regions of opposite dopant types in the lower semiconductor substrate.

[0005] In one aspect of the present disclosure, a method includes: forming a first region disposed in a semiconductor substrate and including a first dopant type; forming a second region disposed in the semiconductor substrate and including a second dopant type; an isolation region located between the first region and the second region; forming a first semiconductor layer vertically contacting the first region, the first semiconductor layer having a dopant type opposite to the first dopant type; forming a second semiconductor layer vertically contacting the second region, the second semiconductor layer having a dopant type opposite to the second dopant type; forming a polycrystalline material vertically contacting the first semiconductor layer; and forming a second semiconductor material having a doping type opposite to the first polycrystalline layer and vertically contacting the first semiconductor layer and the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following detailed description, the present disclosure is described with reference to the several figures mentioned, by way of non-limiting examples of exemplary embodiments of the present disclosure.

[0007] Figure 1A A top view of a device and corresponding manufacturing process in accordance with some aspects of the present disclosure is shown.

[0008] Figure 1B A cross-sectional view of the device and corresponding manufacturing process taken along line X1-X1 in accordance with some aspects of the present disclosure is shown. Figure 1A of the device and corresponding manufacturing process is shown.

[0009] Figure 2 A cross-sectional view of a device in accordance with additional aspects of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of another device in accordance with additional aspects of the present disclosure is shown.

[0011] Figures 4A - 4F A manufacturing process for manufacturing the device of FIG. 1 in accordance with some aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0012] The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers integrated with heterojunction bipolar transistors and manufacturing methods. More specifically, the present disclosure includes a silicon controlled rectifier (SCR) integrated with a SiGe heterojunction bipolar transistor (HBT). Advantageously, due to the improved β of the heterojunction bipolar transistor, the present disclosure provides lower capacitance, less RF degradation (vertical junctions and not well-based junctions), fast switching times, and higher current drive.

[0013] In a more specific embodiment, the SCR includes an n-type region and a p-type region on each side of the shallow trench isolation region. The n-type region and the p-type region may vertically contact SiGe materials of opposite doping types. In one embodiment, the N-type region with polysilicon bridges each SiGe region above the shallow trench isolation region or the buried insulator layer. The P-type polysilicon material may also be located on the p-SiGe region. Compared with known solutions, a low trigger voltage SCR can be achieved by utilizing the high N+ / P+ regions (e.g., SiGe regions) of the external base distribution. Compared with the diode-triggered SCR, this structure will also save area and reduce capacitance.

[0014] The structures of the present disclosure can be fabricated in a variety of different ways using a variety of different tools. Generally, however, methods and tools are used to form structures with micron and nanometer scale dimensions. Methods (i.e., techniques) for fabricating the structures of the present disclosure have been adopted in accordance with integrated circuit (IC) technology. For example, these structures are built on a wafer and are realized in a material film patterned by a photolithography process on top of the wafer. Specifically, the fabrication of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film with respect to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants on the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0015] Figure 1A A top view of the device is shown, Figure 1B showing a cross-section of the Figure 1A device taken along line X1-X1. Referring to Figure 1A and 1B , device 10 includes an SCR that includes an n-type region 12 and a p-type region 14 on opposite sides of the shallow trench isolation region 16. The n-type region 12 and the p-type region 14 may be subset electrode regions of a heterojunction bipolar transistor. The p-type region 14 may be formed in or on an N-well 19 in the semiconductor substrate 17. The n-type region 12, the p-type region 14, and the N-well 19 may be disposed between the shallow trench isolation regions 16, 16a. Thus, the n-p junction is defined by the shallow trench isolation regions 16, 16a, thereby reducing the parasitic capacitance. In an embodiment, the doped regions 12, 14, 19 may be formed by ion implantation processes known in the art and as described in reference to Figure 4A .

[0016] Contacts 21 can be provided for two regions 12, 14 through the interlayer dielectric material 15. The interlayer dielectric material 15 can be, for example, a layer of oxide and / or nitride materials known in the art. As described herein, the contacts 21 can be formed by conventional lithography, etching, and deposition processes. Additionally, a conventional silicide process can be used to provide silicide contacts for the regions 12, 14 before depositing a conductive material to form the contacts 21.

[0017] A collector region can be provided within the semiconductor substrate 17 between the n-type region 12 and the p-type region 14. The semiconductor substrate 17 can be composed of any suitable material, preferably a p-type Si material. In an embodiment, the semiconductor substrate 17 can be a single semiconductor material such as bulk silicon.

[0018] The n-type region 12 and the p-type region 14 are vertically located below and in contact with the respective SiGe materials 20, 22, and the doping types of the SiGe materials 20, 22 are opposite to those of the n-type region 12 and the p-type region 14. For example, the n-type region 12 is vertically in contact with the p-SiGe material 20, and the n-type region 12 is vertically in contact with the n-SiGe material 22. The respective SiGe materials 20, 22 can be the external base regions of a heterojunction bipolar transistor.

[0019] An n-type region 24 can be provided above the n-SiGe material 22, which bridges and contacts the p-type region 14. The n-type region 24 can include a single-crystal semiconductor material 24a and a polysilicon material 24b located between the single-crystal semiconductor materials 24a. The single-crystal n-type semiconductor material 24a is preferably a Si material that contacts the n-SiGe material 22 and the p-SiGe material 20; although other suitable semiconductor materials can also be contemplated herein. In an alternative embodiment, the region 24a can also include a polycrystalline material.

[0020] The single-crystal n-type semiconductor material 24a simultaneously contacts the n-SiGe material 22 and the p-type region 14; while the polysilicon material 24b can be provided between the n-type single-crystal regions 24a and span over the buried insulator material 26. The n-type single-crystal region 24a can be the emitter of a heterojunction bipolar transistor. The polysilicon material 24b will have a lower capacitance than a diode-triggered SCR. The contact 30a can extend to and contact the respective n-type single-crystal regions 24a. The buried insulator material 26 can be, for example, a buried oxide layer.

[0021] A p-type region 28 can be provided on the p-SiGe material 20. In an embodiment, the p-type region 28 can be a polysilicon material, which acts as the emitter region of a PNP HBT. Sidewall spacers 32 can isolate the p-type region 28 from the n-type region 24, more specifically, isolate the p-type region 28 from the n-type single-crystal region 24a that contacts the p-SiGe material 20. The contact 30b can extend to and contact the p-type region 28.

[0022] Those of ordinary skill in the art should understand that the n-SiGe material 22 is shared between the SCR and the HBT. For example, in Figure 1A and 1B the illustrated embodiment, the SCR is p-n-p-n, and the HBT can be a PNP transistor and / or an NPN transistor. More specifically, the SCR includes a p-type region 14, an n-SiGe material 22, and an N-type region 24, a p-type SiGe material 20, and an n-type region 12. In addition, in the embodiment, the PNP HBT can include a p-SiGe material 20, an N-type region 24, and an n-SiGe material 22, as well as a p-type region 14. On the other hand, the NPN HBT can include an n-type region 12, a p-SiGe material 20, and an n-SiGe material 22 and an N-type region 24.

[0023] In addition, in these configurations, for example, the polysilicon material 24b will form a vertical junction (e.g., not a well-based junction) that reduces the device capacitance while also providing less RF degradation than a diode-triggered SCR. In addition, the SiGe materials 20, 22 (e.g., the external base region) will provide an improved β due to higher current drive. In addition, as in each embodiment, the doped regions described herein can be formed by performing separate in-situ doping processes using, for example, a p-type dopant such as boron (B) and an n-type dopant such as arsenic (As), phosphorus (P), and antimony (Sb), and other suitable examples during the epitaxial growth process that will be described in more detail herein.

[0024] Figure 2 A cross-sectional view of a device according to an additional aspect of the present disclosure is shown. In Figure 2 device 10a, the p-SiGe material 20 and the n-SiGe material 22 extend over the shallow trench isolation region 16. That is, the p-SiGe material 20 and the n-SiGe material 22 overlap the underlying shallow trench isolation region 16. In addition, as in device 10, the n-p junction is defined by the shallow trench isolation regions 16, 16a, thereby reducing the parasitic capacitance. The remaining features of structure 10a are similar to Figure 1A and 1B the structure 10 shown, so no further explanation is needed to fully understand the present disclosure.

[0025] Figure 3 A cross-sectional view of another device according to an additional aspect of the present disclosure is shown. In Figure 3 device 10b, the N-type region 24 includes a single-crystal semiconductor material, such as Si material, located on the n-SiGe material 22. In this embodiment, as Figure 1A and 1BAs shown, there is no n-type polysilicon material between the single-crystalline semiconductor materials 24a. Instead, in this embodiment, the P-type region 28 includes single-crystalline semiconductor materials 28a and polysilicon materials 28b located between the single-crystalline semiconductor materials 28a. The single-crystalline P-type semiconductor material 28a is preferably a Si material; although other suitable semiconductor materials can also be contemplated herein. The polysilicon material 28a spans over the buried insulator material 26, wherein the single-crystalline P-type semiconductor material 28a contacts both the p-SiGe material 20 and the n-SiGe material 22 simultaneously. In other embodiments, the n-type region 12 can be a P-type region.

[0026] Figures 4A - 4F illustrates the fabrication of Figure 1A and 1B device 10 according to some aspects of the present disclosure. Those skilled in the art should understand that Figures 4A - 4F can also represent the fabrication process of a device fabricated, for example, by using different in-situ dopants during an epitaxial growth process as described herein. Figure 2 In an embodiment, the subset electrode regions can be formed by an ion implantation process well known in the art, such that no further explanation is required to fully understand the present disclosure.

[0027] In Figure 4A , for example, the n-type region 12, the N-well 19, and the P-type region 14 are formed by a conventional ion implantation process performed on the semiconductor substrate 17. For example, the n-type region 12, the N-well 19, and the P-type region 14 can be formed by introducing a certain concentration of different dopants into the semiconductor substrate 17 using different masking and implantation steps.

[0028] In a more specific embodiment, for example, corresponding patterned implantation masks can be used to define the selected regions exposed for implantation. For example, a first patterned implantation mask is used to select the exposed region for forming the n-type region 12, and the N-well 19 is stripped after implantation and before a second patterned implantation mask for forming the P-type region 14. Similarly, the second patterned implantation mask for selecting the exposed region for forming the P-type region 14 is stripped after implantation. The implantation mask can include a layer of photosensitive material, such as an organic photoresist, which is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. Each implantation mask has a thickness and stopping ability sufficient to prevent the masked region from receiving a certain dose of implanted ions. The P-type region 14 is doped with a p-type dopant, such as boron (B), and the n-type region 12 and the N-well 19 are doped with an n-type dopant, such as arsenic (As), phosphorus (P), and Sb, and other suitable examples.

[0029] Still referring to Figure 4A, a shallow trench isolation region 16 is formed between the n-type region 12 and the p-type region 14. The shallow trench isolation region 16 can be formed by conventional photolithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed above the semiconductor substrate 17 is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemical action, such as reactive ion etching (RIE), will be used to transfer the pattern from the patterned photoresist layer to the semiconductor substrate 17 to form one or more trenches in the semiconductor substrate 17. After removing the resist by a conventional oxygen ashing process or other known strippers, an insulator material (such as SiO 2 ) can be deposited by any conventional deposition process, such as chemical vapor deposition (CVD) process. Any residual material on the surface of the semiconductor substrate 17 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0030] In Figure 4B , a p-SiGe material 20 is formed above the n-type region 12. To form the p-SiGe material 20, an insulator material 26 is deposited on the semiconductor substrate 17. The insulator material 26 can be deposited by any conventional deposition method (e.g., CVD). A masking layer 34 is deposited on the insulator material 26. The masking layer 34 can be a nitride deposited by a conventional deposition method (e.g., CVD). Openings are formed through the buried insulator material 26 and the masking layer 34 to expose the underlying n-type region 12. The openings can be formed by conventional photolithography and etching processes known in the art. A SiGe material is epitaxially grown on the exposed underlying n-type region 12. In an embodiment, the epitaxial growth process includes an in-situ doping process using a p-type dopant to form the p-SiGe material 20.

[0031] In Figure 4C , an n-SiGe material 22 is formed above the p-type region 14. To form the n-SiGe material 22, an insulator material 36 and a masking layer 38 are formed above the masking layer 34 using any conventional deposition method (e.g., CVD). As an example, the insulator material 36 can also be an oxide, and the masking layer 38 can also be a nitride. Again, using conventional photolithography and etching processes, openings are formed through the insulator materials 26, 36 and the masking layers 34, 38 to expose the underlying p-type region 14. A SiGe material is epitaxially grown on the exposed underlying p-type region 14. In an embodiment, the epitaxial growth process includes an in-situ doping process using an n-type dopant to form the n-SiGe material 22.

[0032] In Figure 4DIn [description], the N-type region 24 (e.g., the N-type single crystal region 24a and the polysilicon material 24b) can be formed above the p-SiGe material 20, the n-SiGe material 22, and the buried insulator layer 26. Before forming the N-type region 24, the insulator material 36 and the masking layer 38 can be removed by a conventional removal process (e.g., CMP) or an etching process. In this way, the p-SiGe material 20, the n-SiGe material 22, and the insulator material 26 are exposed. The N-type region 24 can be epitaxially grown from the p-type region 14 and the n-type region 12, bridging over the insulator material 26. In an alternative embodiment, a CVD process can also be used to deposit the region 24. The epitaxial growth process can include performing an in-situ doping process using an N-type dopant (e.g., arsenic). As is well known in the art, the polysilicon material 24b will be formed above the insulator material 26. It should also be understood that a similar process can be used to form the P-type region 28, e.g., as Figure 3 shown, the regions 28a, 28b bridging between the P-SiGe material 20 and the n-SiGe material 22. After a conventional patterning process, sidewall spacer material 32, e.g., nitride, can be deposited and patterned above the N-type region 24.

[0033] In Figure 4E [description], the P-type region 28 can be formed above the p-SiGe material 20. The P-type region 28 is epitaxially grown from the p-SiGe material 20 using a p-type in-situ doping process. After a conventional patterning process, sidewall spacer material, e.g., nitride, can be deposited above the P-type region 28. It should be understood that a similar process can be used to form the N-type region 24, as Figure 3 shown.

[0034] In Figure 4F [description], the buried insulator material 26 (e.g., making it recessed) can be patterned to expose the underlying semiconductor substrate 27. The shallow trench isolation regions 16, 16a can be formed using the conventional lithography, etching, and deposition processes described herein. The shallow trench isolation region 16a can be used to isolate the p-type region 14 and the n-type region 12. The isolation region 16a in the underlying exposed semiconductor substrate 17 can also be a deep trench isolation region.

[0035] Returning to reference Figure 1B , e.g., contacts 21, 30a, 30 can be formed through the interlayer dielectric material 15 by conventional lithography, etching, and deposition processes known in the art. Before depositing the conductive material to form the contacts 21, 30, 30b, a conventional silicide process can be used to provide silicide contacts for the regions 12, 14, 24a, 28.

[0036] Those skilled in the art should understand that the silicide process begins with depositing a thin transition metal layer, such as nickel, cobalt, or titanium, over the exposed regions 12, 14, 24a, 28. After depositing the material, the structure is heated to allow the transition metal to react with the exposed silicon (or other semiconductor materials as described herein) to form a low-resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device.

[0037] These structures can be utilized in system-on-chip (SoC) technology. An SoC is an integrated circuit (also referred to as a "chip") that integrates all components of an electronic system onto a single chip or substrate. Since the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area compared to a multi-chip design with equivalent functionality. Thus, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0038] The above methods are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in the form of single-chip packages (e.g., plastic carriers, whose leads are fixed to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers, which have surface interconnections or buried interconnections, or both surface interconnections and buried interconnections). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to high-end computer products with displays, keyboards, or other input devices and central processors.

[0039] The description of the various embodiments of the present disclosure has been given for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology found in the market, or to enable other ordinary skilled artisans in the technical field to understand the embodiments disclosed herein.

Claims

1. A structure comprising: a first region disposed in the semiconductor substrate and comprising a first dopant type; a second region disposed in the semiconductor substrate and comprising a second dopant type; an isolation region located between the first region and the second region; a first semiconductor layer vertically contacting the first region, the first semiconductor layer having a dopant type opposite to the first dopant type; a second semiconductor layer vertically contacting the second region, the second semiconductor layer having a dopant type opposite to the second dopant type; a polycrystalline material vertically contacting the first semiconductor layer; as well as A second semiconductor material has an opposite doping type as the first polycrystalline layer and vertically contacts the first semiconductor layer and the second semiconductor layer.

2. The structure according to claim 1, wherein: The first dopant type is an n-type dopant and the second dopant type is a p-type dopant.

3. The structure according to claim 2, wherein: The first region and the second region include Si material, and the first semiconductor layer and the second semiconductor layer include SiGe material.

4. The structure according to claim 3, wherein: The first semiconductor layer includes a p-type SiGe material, and the second semiconductor layer includes an n-type SiGe material.

5. The structure according to claim 4, wherein: The polycrystalline material is a p-type semiconductor material, and the second semiconductor material is an n-type semiconductor material.

6. The structure of claim 5, further comprising an n-type polysilicon material located between the second semiconductor material, bridging over the insulator material between the first semiconductor layer and the second semiconductor layer.

7. The structure according to claim 1, wherein: The second region is located in a well having the first dopant type.

8. The structure according to claim 1, wherein: The first dopant type is a p-type dopant, the second dopant type is an n-type dopant, the first semiconductor layer includes n-type SiGe shared between a silicon-controlled rectifier and a bipolar transistor, the second semiconductor layer includes a p-SiGe material, the polycrystalline material is an n-type semiconductor material, and the second semiconductor material is a p-type semiconductor material.

9. The structure of claim 8, further comprising a p-type polysilicon material located between the second semiconductor material, bridging over the insulator material between the first semiconductor layer and the second semiconductor layer.

10. The structure according to claim 1, wherein: The structure of claim 1 comprises a heterojunction bipolar transistor integrated with a silicon controlled rectifier.

11. The structure of claim 10 further comprising contacts connected to the first region, the second region, the first semiconductor layer, and the second semiconductor layer.

12. A structure comprising a heterojunction bipolar transistor integrated with a silicon-controlled rectifier, both of which share a doped semiconductor material above a lower semiconductor substrate, the doped semiconductor material serving as a base of the heterojunction bipolar transistor and being isolated from an underlying well having the same dopant type by a region of opposite dopant type in the lower semiconductor substrate.

13. The structure according to claim 12, wherein: The doped semiconductor material includes an n-SiGe material, the lower well includes an N-well located in a p-type semiconductor substrate, and the opposite dopant type region includes a p-type sub-collector region of the heterojunction bipolar transistor.

14. The structure according to claim 12, wherein: The heterojunction bipolar transistor includes an NPN transistor and a PNP transistor.

15. The structure according to claim 14, wherein: The silicon controlled rectifier comprises a pnpn.

16. The structure of claim 14, wherein: The PNP transistor includes: a p-SiGe material; an n-SiGe material and an N-type region located above the n-SiGe; and the opposite dopant type region.

17. The structure according to claim 16, wherein: The SCR includes: the opposite dopant type region; the n-SiGe material and the N-type region; the p-SiGe material; and an n-type region located below the p-SiGe material.

18. The structure of claim 14, wherein: The NPN transistor includes: an n-type region located in the lower semiconductor substrate; a p-SiGe material; and an n-SiGe material and an N-type region located above the n-SiGe.

19. The structure of claim 18, wherein: The SCR includes: the opposite dopant type region; the n-SiGe material and the N-type region; the p-SiGe material; and an n-type region located below the p-SiGe material.

20. A method comprising: forming a first region disposed in a semiconductor substrate and comprising a first dopant type; forming a second region disposed in the semiconductor substrate and comprising a second dopant type; an isolation region located between the first region and the second region; forming a first semiconductor layer, the first semiconductor layer vertically contacting the first region, the first semiconductor layer having a dopant type opposite to the first dopant type; forming a second semiconductor layer, the second semiconductor layer vertically contacting the second region, the second semiconductor layer having a dopant type opposite to the second dopant type; forming a polycrystalline material, the polycrystalline material vertically contacting the first semiconductor layer; as well as A second semiconductor material is formed, the second semiconductor material having an opposite doping type as the first polycrystalline layer and vertically contacting the first semiconductor layer and the second semiconductor layer.

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