Method of forming semiconductor structure
By using a borophosphorus silicone glass layer to replace the traditional oxide layer during the formation of the semiconductor structure, and by forming and etching the spacer layer, the problem of instability in the etching process end point detection in the traditional method is solved, and the stability of the implanted position of the source/drain region and excellent electrical properties are achieved.
Patent Information
- Application Number
- CN202410374081.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-06
- Filing Date
- 2024-03-29
- Publication Date
- 2025-06-10
AI Technical Summary
When forming metal oxide semiconductor field effect transistors (MOSFETs), the traditional oxide spacer layer is the same as the top oxide layer, resulting in unstable detection of the end point of the etching process, affecting the implantation position and electrical properties of the source/drain region.
The borophosphorus silicon glass (BPSG) layer is used to replace the traditional oxide layer and serve as a mask to etch the metal layer and the semiconductor layer. By forming the first and second spacers, the top surfaces of the borophosphorus silicon glass layer and the second dielectric layer are etched to expose the top surfaces of the borophosphorus silicon glass layer and the second dielectric layer, ensuring that the second spacer layer directly contacts the second dielectric layer, achieving stable etch end detection.
By using borophosphorus silicone glass layer, the problem of difficult control of the thickness of the oxide spacer layer is solved, and the stability of the implanted position of the source/drain region and excellent electrical properties, such as saturation current (Idsat) are achieved.
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Figure CN120129264A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a method of forming a semiconductor structure. Background Art
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are commonly used in memory devices, including dynamic random access memory (DRAM) devices. A metal-oxide-semiconductor field-effect transistor is typically formed by providing a gate structure on a semiconductor substrate to define a channel region, and forming source and drain regions on opposite sides of the channel region.
[0003] Generally, the formation of a typical gate structure may include forming a stack having a polysilicon layer, a metal layer, a nitride layer, and a top oxide layer; using the top oxide layer as a mask to etch the polysilicon layer and the metal layer to form a gate stack; forming nitride spacers on sidewalls of the gate stack; and forming an oxide spacer layer to cover the nitride spacers and the top oxide layer. Then, the oxide spacer layer is etched to form oxide spacers until the nitride layer is exposed. However, the remaining top oxide layer on the nitride layer has the same material (i.e., oxide) as the oxide spacer layer, so the thickness of the remaining top oxide layer will affect the end point detection (EPD) for controlling the etching process time. As a result, the thickness of the oxide spacers is difficult to control due to the remaining top oxide layer, which further causes the implantation positions for the source / drain regions to be unstable, resulting in poor electrical performance. Summary of the Invention
[0004] According to some embodiments of the present disclosure, a method of forming a semiconductor structure includes sequentially forming a semiconductor layer and a metal layer on a first dielectric layer on a semiconductor substrate; forming a second dielectric layer on a portion of the metal layer; forming a borophosphosilicate glass layer on the second dielectric layer; etching the metal layer and the semiconductor layer using the borophosphosilicate glass layer as a mask; forming a first spacer layer on sidewalls of the semiconductor layer, sidewalls of the metal layer, sidewalls of the second dielectric layer, and on a top surface of the borophosphosilicate glass layer; etching the first spacer layer to expose the borophosphosilicate glass layer; removing the borophosphosilicate glass layer to expose the top surface of the second dielectric layer; forming a second spacer layer on sidewalls of the first spacer layer and on the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer.
[0005] In some embodiments, the above-mentioned borophosphosilicate glass layer has an etching selectivity different from that of the first dielectric layer.
[0006] In some embodiments, the material of the above-mentioned first dielectric layer includes silicon dioxide, and the first dielectric layer is formed by in-situ vapor generation.
[0007] In some embodiments, after etching the metal layer and the semiconductor layer, the top surface of the borophosphosilicate glass layer is convex outward.
[0008] In some embodiments, the second spacer layer is formed on the sidewalls of the first spacer layer and the top surface of the second dielectric layer such that the second spacer layer directly contacts the top surface of the second dielectric layer.
[0009] In some embodiments, the material of the second dielectric layer is different from the material of the first dielectric layer.
[0010] In some embodiments, the material of the first spacer layer is different from the material of the second spacer layer.
[0011] In some embodiments, the material of the first spacer layer is the same as the material of the second dielectric layer.
[0012] In some embodiments, the method of forming the semiconductor structure further includes, during etching of the second spacer layer, detecting whether the top surface of the second dielectric layer is exposed; and stopping etching of the second spacer layer when the top surface of the second dielectric layer is detected to be exposed.
[0013] In some embodiments, the method of forming the semiconductor structure further includes forming source / drain regions in a position of the semiconductor substrate according to the thickness of the second spacer layer.
[0014] In some embodiments, the material of the semiconductor layer includes polysilicon.
[0015] According to some embodiments of the present disclosure, a method of forming a semiconductor structure includes using a borophosphosilicate glass layer as a mask to etch a metal layer and a semiconductor layer under the metal layer, wherein the semiconductor layer is located between the metal layer and a first dielectric layer, and a second dielectric layer is located between the borophosphosilicate glass layer and the metal layer; forming a first spacer layer on the sidewalls of the semiconductor layer, the sidewalls of the metal layer, the sidewalls of the second dielectric layer, and the top surface of the borophosphosilicate glass layer; etching the first spacer layer to expose the borophosphosilicate glass layer; removing the borophosphosilicate glass layer to expose the top surface of the second dielectric layer, wherein the borophosphosilicate glass layer has an etching selectivity different from that of the first dielectric layer; forming a second spacer layer on the sidewalls of the first spacer layer and the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer.
[0016] In some embodiments, the material of the first dielectric layer includes silicon dioxide, and the first dielectric layer is formed by in-situ vapor generation.
[0017] In some embodiments, after etching the metal layer and the semiconductor layer, the top surface of the borophosphosilicate glass layer is convex outward.
[0018] In some embodiments, the second spacer layer is formed on the sidewalls of the first spacer layer and on the top surface of the second dielectric layer such that the second spacer layer directly contacts the top surface of the second dielectric layer.
[0019] In some embodiments, the material of the second dielectric layer is different from the material of the first dielectric layer.
[0020] In some embodiments, the material of the first spacer layer is different from the material of the second spacer layer.
[0021] In some embodiments, the material of the first spacer layer is the same as the material of the second dielectric layer.
[0022] In some embodiments, the method of forming the semiconductor structure further includes, during etching of the second spacer layer, detecting whether the top surface of the second dielectric layer is exposed; and stopping the etching of the second spacer layer when the top surface of the second dielectric layer is detected to be exposed.
[0023] In some embodiments, the method of forming the semiconductor structure further includes forming source / drain regions in positions of the semiconductor substrate according to the thickness of the second spacer layer.
[0024] In the above embodiments of the present disclosure, since a borophosphosilicate glass layer (BPSG) is formed on the second dielectric layer to replace the conventional oxide layer, the borophosphosilicate glass layer can be removed after etching the first spacer layer to expose the top surface of the second dielectric layer. In this way, the second spacer layer can be directly formed on the top surface of the second dielectric layer and on the sidewalls of the first spacer layer. Before etching the second spacer layer, there is no additional oxide layer located directly under the second spacer layer and having the same material as the second spacer layer, and the end point detection (EPD) for controlling the etching process time can be stabilized according to the thickness of the second spacer layer. Accordingly, the thickness of the remaining second spacer layer is easy to control, and thus a stable position for implantation for the source / drain regions is defined, resulting in excellent electrical properties, such as the saturation current (Idsat). BRIEF DESCRIPTION OF THE DRAWINGS
[0025] When read in conjunction with the accompanying Figure 1 drawings, the aspects of the present disclosure can be best understood from the following embodiments. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features can be arbitrarily increased or decreased.
[0026] Figure 1 FIG. is a flowchart illustrating a method of forming a semiconductor structure according to an embodiment of the present disclosure.
[0027] Figures 2 to 9 FIG. is a cross-sectional view illustrating an intermediate stage of a method of forming a semiconductor structure according to some embodiments of the present disclosure. Detailed implementation manners
[0028] The following disclosed implementation manner content provides many different implementation manners, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present case. Of course, these examples are only examples and are not intended to be limiting. In addition, the present case may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various implementation manners and / or configurations discussed.
[0029] Spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein for the purpose of facilitating description to describe the relationship between one element or feature and another element or feature as shown in the drawings. The spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive words used herein may be interpreted accordingly.
[0030] Figure 1 The flowchart shows a method of forming a semiconductor structure according to an embodiment of the present disclosure. The method of forming a semiconductor structure includes the following steps. In step S1, a semiconductor layer and a metal layer are sequentially formed on a first dielectric layer on a semiconductor substrate. Then, in step S2, a second dielectric layer is formed on a part of the metal layer. Then, in step S3, a boro-phospho-silicate-glass (BPSG) layer is formed on the second dielectric layer. After that, in step S4, the metal layer and the semiconductor layer are etched using the BPSG layer as a mask. Subsequently, in step S5, a first spacer layer is formed on the sidewalls of the semiconductor layer, the sidewalls of the metal layer, the sidewalls of the second dielectric layer, and the top surface of the BPSG layer. Then, in step S6, the first spacer layer is etched to expose the BPSG layer. Then, in step S7, the BPSG layer is removed to expose the top surface of the second dielectric layer. After that, in step S8, a second spacer layer is formed on the sidewalls of the first spacer layer and the top surface of the second dielectric layer. Subsequently, in step S9, the second spacer layer is etched to expose the top surface of the second dielectric layer.
[0031] In addition, each of steps S1 to S9 may include a plurality of detailed steps. The method of forming this semiconductor structure may include other steps between step S1 and step S9, and other steps before step S1 and after step S9. In the following description, steps S1 to S9 mentioned above will be described in detail.
[0032] Figures 2 to 9FIG. is a cross-sectional view of an intermediate stage of a method for forming a semiconductor structure according to some embodiments of the present disclosure. As Figure 2 shown, a first dielectric layer 110 is formed on a semiconductor substrate 120. The material of the first dielectric layer 110 may include silicon dioxide (SiO 2 ), and the first dielectric layer 110 may be formed by in-situ steam generation (ISSG) technology. A semiconductor layer 130 and a metal layer 140 are sequentially formed on the first dielectric layer 110. The material of the semiconductor layer 130 may include polysilicon, and the material of the metal layer 140 may include tungsten (W). The semiconductor substrate 120 may be a silicon substrate. The semiconductor layer 130 is below the metal layer 140, and the semiconductor layer 130 is located between the metal layer 140 and the first dielectric layer 110.
[0033] Next, a second dielectric layer 150 is formed on a part of the metal layer 140, and then, a borophosphosilicate glass layer 160 is formed on the second dielectric layer 150. The second dielectric layer 150 and the borophosphosilicate glass layer 160 may be formed by a patterning process of photolithography. The second dielectric layer 150 is located between the borophosphosilicate glass layer 160 and the metal layer 140. In addition, the material of the second dielectric layer 150 is different from the material of the first dielectric layer 110. In some embodiments, the material of the second dielectric layer 150 may be a nitride, such as carbon nitride.
[0034] Referring to Figure 3 , after the borophosphosilicate glass layer 160 is formed, the metal layer 140 and the semiconductor layer 130 can be etched using the borophosphosilicate glass layer 160 as a mask. After this etching process, since a part of the borophosphosilicate glass layer 160 is consumed during etching, the top surface 162 of the borophosphosilicate glass layer 160 is convex. In addition, the metal layer 140 is a gate electrode, and the structure on the Figure 3 semiconductor substrate 120 can be regarded as a gate stack.
[0035] Referring to Figure 4 , then, a first spacer layer 170 is formed on the sidewalls of the semiconductor layer 130, the sidewalls of the metal layer 140, the sidewalls of the second dielectric layer 150, and the top surface 162 of the borophosphosilicate glass layer 160. In some embodiments, the material of the first spacer layer 170 is the same as the material of the second dielectric layer 150, such as a nitride.
[0036] Referring to Figure 5 , after the first spacer layer 170 is formed, the first spacer layer 170 is etched to expose the borophosphosilicate glass layer 160. That is, there is no first spacer layer 170 on the top surface 162 of the borophosphosilicate glass layer 160.
[0037] Refer to Figure 6 , then, the borophosphosilicate glass layer 160 is removed to expose the top surface 152 of the second dielectric layer 150. The removal of the borophosphosilicate glass layer 160 can be performed by wet etching. In some embodiments, the borophosphosilicate glass layer 160 has an etch selectivity different from that of the first dielectric layer 110, so the first dielectric layer 110 remains after the borophosphosilicate glass layer 160 is etched.
[0038] Refer to Figure 7 , after the borophosphosilicate glass layer 160 is removed from the top surface 152 of the second dielectric layer 150, the second spacer layer 180 is formed on the sidewalls of the first spacer layer 170 and the top surface 152 of the second dielectric layer 150. The material of the second spacer layer 180 is different from that of the first spacer layer 170. For example, the second spacer layer 180 can be an oxide. In this step, the second spacer layer 180 directly contacts the top surface 152 of the second dielectric layer 150.
[0039] Refer to Figure 8 , then, the second spacer layer 180 is etched to expose the top surface 152 of the second dielectric layer 150, so that the gate structure shown in Figure 8 can be obtained. During the etching of the second spacer layer 180, it can be detected whether the top surface 152 of the second dielectric layer 150 is exposed. In addition, when the top surface 152 of the second dielectric layer 150 is detected to be exposed, the etching of the second spacer layer 180 is stopped. The etching process time is based on the end point detection (EPD) of the second dielectric layer 150. In addition, since part of the second dielectric layer 150 is consumed during the etching, the top surface 152 of the second dielectric layer 150 is convex.
[0040] Specifically, since the borophosphosilicate glass layer 160 (see Figure 5 ) is formed on the second dielectric layer 150 to replace the conventional oxide layer, the borophosphosilicate glass layer 160 can be removed after the first spacer layer 170 (see Figure 5 ) is etched to expose the top surface 152 of the second dielectric layer 150. In this way, the second spacer layer 180 can be directly formed on the top surface 152 of the second dielectric layer 150 and the sidewalls of the first spacer layer 170. Before the second spacer layer 180 is etched, there is no additional oxide layer located directly below the second spacer layer 180 and having the same material as the second spacer layer 180. In addition, the end point detection for controlling the etching process time can be stable according to the thickness of the second spacer layer 180. Therefore, the thickness of the remaining second spacer layer 180 is easy to control.
[0041] Refer to Figure 9, after etching the second spacer layer 180 to expose the top surface 152 of the second dielectric layer 150, the second spacer layer 180 has a thickness D. The thickness D of the second spacer layer 180 is a critical dimension (CD) that determines the formation position of the source / drain regions 190. According to the thickness D of the second spacer layer 180, the source / drain regions 190 can be formed at positions on the semiconductor substrate 120. In other words, the remaining thickness D of the second spacer layer 180 is easy to control, so it defines a stable position for the implantation used for the source / drain regions 190, and has excellent electrical properties, such as the saturation current (Idsat). In some embodiments, the source / drain regions 190 are located between the channel region of the semiconductor substrate 120 and the shallow trench isolation 112 (STI), where the channel region is located under the gate structure.
[0042] The foregoing has outlined the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.
[0043]
Symbol Description
[0044] 110: First dielectric layer
[0045] 112: Shallow trench isolation
[0046] 120: Semiconductor substrate
[0047] 130: Semiconductor layer
[0048] 140: Metal layer
[0049] 150: Second dielectric layer
[0050] 152: Top surface
[0051] 160: Boron phosphosilicate glass layer
[0052] 162: Top surface
[0053] 170: First spacer layer
[0054] 180: Second spacer layer
[0055] 190: Source / drain region
[0056] S1, S2, S3, S4, S5, S6, S7, S8, S9: Steps
[0057] D: Thickness
Claims
1. A method for forming a semiconductor structure, characterized in that: include: forming a semiconductor layer and a metal layer in sequence on a first dielectric layer on a semiconductor substrate; forming a second dielectric layer on a portion of the metal layer; forming a borophosphosilicate glass layer on the second dielectric layer; Using the borophosphosilicate glass layer as a mask, etching the metal layer and the semiconductor layer; Forming a first spacer layer on the sidewalls of the semiconductor layer, the sidewalls of the metal layer, the sidewalls of the second dielectric layer and the top surface of the borophosphosilicate glass layer; etching the first spacer layer to expose the borophosphosilicate glass layer; removing the borophosphosilicate glass layer to expose the top surface of the second dielectric layer; forming a second spacer layer on the sidewalls of the first spacer layer and the top surface of the second dielectric layer; as well as The second spacer layer is etched to expose the top surface of the second dielectric layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: The borophosphosilicate glass layer has an etching selectivity different from that of the first dielectric layer.
3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first dielectric layer includes silicon dioxide, and the first dielectric layer is formed by on-site vapor generation.
4. The method for forming a semiconductor structure according to claim 1, wherein: After etching the metal layer and the semiconductor layer, the top surface of the borophosphosilicate glass layer is convex.
5. The method for forming a semiconductor structure according to claim 1, wherein: The second spacer is formed on the sidewall of the first spacer and the top surface of the second dielectric layer so that the second spacer directly contacts the top surface of the second dielectric layer.
6. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second dielectric layer is different from the material of the first dielectric layer.
7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first spacer layer is different from the material of the second spacer layer.
8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first spacer layer is the same as that of the second dielectric layer.
9. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: During etching of the second spacer layer, detecting whether the top surface of the second dielectric layer is exposed; as well as When it is detected that the top surface of the second dielectric layer is exposed, etching the second spacer layer is stopped.
10. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: According to the thickness of the second spacer layer, a source / drain region is formed in the position of the semiconductor substrate.
11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the semiconductor layer includes polysilicon.
12. A method for forming a semiconductor structure, characterized in that: include: Using a borophosphosilicate glass layer as a mask to etch a metal layer and a semiconductor layer below the metal layer, wherein the semiconductor layer is located between the metal layer and a first dielectric layer, and a second dielectric layer is located between the borophosphosilicate glass layer and the metal layer; Forming a first spacer layer on the sidewalls of the semiconductor layer, the sidewalls of the metal layer, the sidewalls of the second dielectric layer and the top surface of the borophosphosilicate glass layer; etching the first spacer layer to expose the borophosphosilicate glass layer; Removing the borophosphosilicate glass layer to expose a top surface of the second dielectric layer, wherein the borophosphosilicate glass layer has a different etching selectivity than the first dielectric layer; forming a second spacer layer on the sidewalls of the first spacer layer and the top surface of the second dielectric layer; as well as The second spacer layer is etched to expose the top surface of the second dielectric layer.
13. The method for forming a semiconductor structure according to claim 12, wherein: The material of the first dielectric layer includes silicon dioxide, and the first dielectric layer is formed by on-site vapor generation.
14. The method for forming a semiconductor structure according to claim 12, wherein: After etching the metal layer and the semiconductor layer, the top surface of the borophosphosilicate glass layer is convex.
15. The method for forming a semiconductor structure according to claim 12, wherein: The second spacer is formed on the sidewall of the first spacer and the top surface of the second dielectric layer so that the second spacer directly contacts the top surface of the second dielectric layer.
16. The method for forming a semiconductor structure according to claim 12, wherein: The material of the second dielectric layer is different from the material of the first dielectric layer.
17. The method for forming a semiconductor structure according to claim 12, wherein: The material of the first spacer layer is different from the material of the second spacer layer.
18. The method for forming a semiconductor structure according to claim 12, wherein: The material of the first spacer layer is the same as that of the second dielectric layer.
19. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: During etching of the second spacer layer, detecting whether the top surface of the second dielectric layer is exposed; as well as When it is detected that the top surface of the second dielectric layer is exposed, etching the second spacer layer is stopped.
20. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: According to the thickness of the second spacer layer, source / drain regions are formed in the positions of the semiconductor substrate.