Thin film transistor, array substrate and display panel

Abstract

The embodiment of the invention provides a thin film transistor, an array substrate and a display panel, relates to the technical field of display, and is used for improving the mobility and the electrical stability of the thin film transistor. The thin film transistor comprises an active layer located on one side of a substrate and a gate layer located on the side, away from the substrate, of the active layer. Wherein the active layer comprises a first sub-layer and a second sub-layer, the second sub-layer is located on the side, away from the substrate, of the first sub-layer, and the mobility of the first sub-layer is higher than that of the second sub-layer; and the average thickness of the first sub-layer is smaller than that of the second sub-layer. The thin film transistor is used for driving a display panel to display an image.

Description

[0001] This application is a divisional application. The application number of the original application is 202410983767.4, the filing date of the original application is July 19, 2024, and the entire content of the original application can be incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technologies, and particularly to a thin film transistor, an array substrate, and a display panel. Background Art

[0003] Currently, common semiconductor active materials in the field of semiconductor displays include amorphous silicon, metal oxides, and low-temperature polycrystalline silicon. The mobility of amorphous silicon is about 1 cm 2 / V*s, the mobility of metal oxides is about 10 cm 2 / V*s, and the mobility of low-temperature polycrystalline silicon is about 80 cm 2 / V*s. Among them, low-temperature polycrystalline silicon has obvious material advantages. By increasing the proportion of In element and adding Sn element and other solutions, the mobility of metal oxides can be increased to 20 cm 2 / V*s to 50 cm 2 / V*s, but there is still a certain gap compared with low-temperature polycrystalline silicon. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide a thin film transistor, an array substrate, and a display panel, which are used to improve the mobility and electrical stability of the thin film transistor.

[0005] To achieve the above purpose, the embodiments of the present disclosure provide the following technical solutions:

[0006] On the one hand, a thin film transistor is provided. The thin film transistor includes: an active layer on one side of a substrate, and a gate layer on the side of the active layer away from the substrate; wherein, the active layer includes: a first sub-layer and a second sub-layer on the side of the first sub-layer away from the substrate, the mobility of the first sub-layer is higher than that of the second sub-layer; and the average thickness of the first sub-layer is less than the average thickness of the second sub-layer.

[0007] In the above-mentioned thin film transistor, the embodiment of the present disclosure forms a first conductive channel with higher mobility between the first sublayer and the second sublayer by setting the mobility of the first sublayer to be greater than the mobility of the second sublayer, and the average thickness of the first sublayer to be less than the average thickness of the second sublayer, and a part of the first conductive channel can be located in the first sublayer with higher mobility, which is conducive to the transmission of carriers, and the second sublayer can provide carriers to the first sublayer, so that the thin film transistor has a higher mobility. Moreover, the first conductive channel can be relatively far away from the gate insulating layer, reducing the capture of carriers in the first conductive channel by the interface defects of the gate insulating layer, so that the first conductive channel maintains a higher carrier concentration, so as to improve the electrical stability of the thin film transistor, thereby extending the switching capability and service life of the thin film transistor. Therefore, the embodiment of the present disclosure improves the electrical stability of the thin film transistor while ensuring that the thin film transistor has a higher mobility, thereby achieving the purpose of enhancing the switching capability and extending the service life of the thin film transistor.

[0008] In some embodiments, a ratio of an average thickness of the first sub-layer to an average thickness of the second sub-layer ranges from 0.1 to 0.85.

[0009] In some embodiments, the average thickness of the first sub-layer is in a range of 5 nm to 25 nm.

[0010] In some embodiments, the average thickness of the second sub-layer is in a range of 30 nm to 50 nm.

[0011] In some embodiments, the mobility of the first sublayer is greater than or equal to 20 cm 2 / V*s.

[0012] In some embodiments, the mobility of the second sublayer is in the range of 5 cm 2 / V*s~15cm 2 / V*s.

[0013] In some embodiments, the optical bandgap of the material of the first sub-layer is smaller than the optical bandgap of the material of the second sub-layer.

[0014] In some embodiments, the optical band gap of the material of the first sub-layer is less than or equal to 2.9 eV.

[0015] In some embodiments, the optical band gap of the material of the second sub-layer is greater than or equal to 3 eV.

[0016] In some embodiments, the first sublayer and the second sublayer meet at least one of the following conditions: the zinc content of the first sublayer is greater than the zinc content of the second sublayer; the gallium content of the first sublayer is less than the gallium content of the second sublayer; the tin content of the first sublayer is greater than the tin content of the second sublayer.

[0017] In some embodiments, a ratio of a zinc content in the first sublayer to a zinc content in the second sublayer is in a range of 1.1 to 2; and / or a ratio of a gallium content in the second sublayer to a gallium content in the first sublayer is in a range of 2 to 5.

[0018] In some embodiments, the material of the first sublayer includes: at least one of indium gallium oxide, indium tin zinc oxide and indium gallium zinc tin oxide; and / or, the material of the second sublayer includes: indium gallium zinc oxide.

[0019] In some embodiments, the thin film transistor further includes: an interlayer dielectric layer, the interlayer dielectric layer being located on a side of the gate layer away from the substrate; the interlayer dielectric layer including: a first interlayer dielectric layer and a second interlayer dielectric layer arranged in a direction away from the substrate; wherein the content of hydrogen atoms in the first interlayer dielectric layer is less than the content of hydrogen atoms in the second interlayer dielectric layer; and the density of the first interlayer dielectric layer is less than the density of the second interlayer dielectric layer.

[0020] In some embodiments, the thin film transistor also includes: a first via hole, which passes through the interlayer dielectric layer; the first via hole includes: a first hole passing through the first interlayer dielectric layer and a second hole passing through the second interlayer dielectric layer; wherein the boundary of the first hole surrounded by the first interlayer dielectric layer is located on the inner side of the boundary of the second hole surrounded by the second interlayer dielectric layer.

[0021] In some embodiments, a distance between a boundary of the first hole formed by the first interlayer dielectric layer and a boundary of the second hole formed by the second interlayer dielectric layer is in a range of 0.5 μm to 1.5 μm.

[0022] In some embodiments, the thin film transistor also includes: a source-drain metal layer; the source-drain metal layer is located on a side of the active layer away from the substrate, and the source-drain metal layer is connected to the second sublayer; or, the source-drain metal layer is located on a side of the active layer close to the substrate, and the source-drain metal layer is connected to the first sublayer.

[0023] On the other hand, an array substrate is provided, comprising: a substrate and a plurality of thin film transistors arranged on the substrate, wherein at least one of the plurality of thin film transistors is the thin film transistor described in any of the above embodiments.

[0024] In some embodiments, the array substrate further includes: a light-shielding layer and a buffer layer, wherein the light-shielding layer is located between the substrate and the active layer of the thin film transistor, and the buffer layer is located between the light-shielding layer and the active layer; the thin film transistor includes: a gate insulating layer, wherein the gate insulating layer is located between the active layer and the gate layer of the thin film transistor; wherein the average thickness of a portion of the buffer layer located between the light-shielding layer and the active layer is greater than the average thickness of the gate insulating layer.

[0025] On the other hand, a display panel is provided, comprising: an array substrate as described in any of the above embodiments; the display panel further comprises: an opposing substrate and a liquid crystal layer, the opposing substrate is opposite to the array substrate and is arranged at an interval; the liquid crystal layer is arranged between the array substrate and the opposing substrate.

[0026] On the other hand, a display panel is provided, comprising: an array substrate as described in any of the above embodiments; the display panel further comprises: a plurality of light-emitting devices, the plurality of light-emitting devices are arranged on the array substrate, and the array substrate is used to drive the plurality of light-emitting devices to emit light.

[0027] The array substrate and the display panel have the same structure and beneficial technical effects as the thin film transistors provided in some of the above embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, etc.

[0029] Figure 1 is a structural diagram of a thin film transistor according to some embodiments;

[0030] Figure 2 is a structural diagram of an array substrate according to some embodiments;

[0031] Figure 3 is a schematic diagram of a conduction principle of a thin film transistor according to some embodiments;

[0032] Figure 4 is another conduction principle diagram of a thin film transistor according to some embodiments;

[0033] Figure 5 is another conduction principle diagram of a thin film transistor according to some embodiments;

[0034] Figure 6 is the basic characteristic curve graph of a thin film transistor according to some embodiments;

[0035] Figure 7 is the electrical stability curve graph of a thin film transistor according to some embodiments;

[0036] Figure 8 is another electrical stability curve graph of a thin film transistor according to some embodiments;

[0037] Figure 9 is the cross-sectional microscopic morphology diagram of a thin film transistor taken by using a transmission electron microscope (TEM) according to some embodiments;

[0038] Figure 10 is the energy dispersive X-ray spectroscopy (EDX) diagram of the active layer of a thin film transistor according to some embodiments;

[0039] Figure 11 is the cross-sectional microscopic morphology diagram of an array substrate taken by using a transmission electron microscope according to some embodiments;

[0040] Figure 12 is another structural diagram of an array substrate according to some embodiments;

[0041] Figure 13 is yet another structural diagram of a thin film transistor according to some embodiments;

[0042] Figure 14 is the flowchart of the preparation method of an array substrate according to some embodiments;

[0043] Figure 15 and Figure 16 are the structural diagrams corresponding to each step of the preparation method of an array substrate according to some embodiments;

[0044] Figure 17 is the structural diagram of a display panel according to some embodiments;

[0045] Figure 18 is another structural diagram of a display panel according to some embodiments;

[0046] Figure 19 is the structural diagram of a display device according to some embodiments. Detailed implementation manners

[0047] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0048] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples", etc., are intended to indicate that a particular feature, structure, material, or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the described particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any suitable manner.

[0049] Hereinafter, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0050] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0051] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0052] As used herein, "about", "substantially", or "approximately" includes the recited value and the average within an acceptable deviation range of the particular value, where the acceptable deviation range is determined by those of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0053] As used herein, "parallel", "perpendicular", and "equal" include the stated cases as well as cases similar to the stated cases, where the similar cases are within an acceptable deviation range, and the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, the difference between the two equal values is less than or equal to 5% of either one of them.

[0054] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0055] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0056] In some embodiments, as Figure 1 shown, the thin film transistor 10 may include: an active layer 12 disposed on a substrate 11, a gate insulating layer 13, a gate layer 14, an interlayer dielectric layer 15, and a source-drain metal layer 16. The thin film transistor 10 has a gate 141, a source 161, and a drain 162. The gate 141 is located in the gate layer 14, and the source 161 and the drain 162 are located in the source-drain metal layer 16. The source 161 and the drain 162 are connected to the active layer 12 through a first via hole H1 penetrating the interlayer dielectric layer 15. When a certain voltage is applied to the gate 141 of the thin film transistor 10, the active layer 12 is turned on, so that a path is formed between the source 161 and the drain 162, realizing the turn-on of the thin film transistor 10.

[0057] Exemplarily, the material of the active layer 12 includes a semiconductor material. The high mobility of the semiconductor material is of great significance. A higher mobility indicates that electrons have a faster transmission speed in the semiconductor material, and a higher mobility is beneficial to improving the quality of the display screen of the display device 2000.

[0058] Among them, mobility refers to the average drift velocity of carriers generated under a unit electric field strength, and the unit is centimeter 2 / (volt·second), expressed as cm 2 / V*s.

[0059] In some examples, the material of the active layer 12 includes: amorphous silicon (a-Si), metal oxide or low temperature poly-silicon (abbreviated as LTPS). The mobility of amorphous silicon (a-Si) is about 1 cm 2 / V*s, the mobility of the metal oxide is about 10 cm 2 / V*s, and the mobility of low temperature poly-silicon is about 80 cm 2 / V*s.

[0060] The thin film transistor 10 formed with a metal oxide as the material of the active layer 12 is called an oxide thin film transistor. The oxide thin film transistor has been widely studied in recent years for its flexibility, large-area production and simple process characteristics. Adding Sn element to the metal oxide and increasing the proportion of In element can increase the mobility of the metal oxide to 20 cm 2 / V*s to 50 cm 2 / V*s. However, due to reasons such as the preparation process, the mobility of the currently prepared metal oxide active layer 12 is lower than the theoretical value.

[0061] Moreover, the metal oxide with high mobility has a smaller optical band gap Eg and chemical activation energy Ea. The reduction of the optical band gap Eg means that electrons can absorb light in a larger wavelength range and transition, thus turning on the thin film transistor 10 in advance. The reduction of the chemical activation energy Ea means that the high-mobility metal oxide is more likely to generate new defects, thus affecting the electrical stability of the thin film transistor 10. Therefore, while increasing the mobility, it is difficult for the high-mobility metal oxide to take into account the electrical stability, resulting in a reduced service life of the thin film transistor 10.

[0062] Based on this, as Figure 2 shown, the embodiment of the present disclosure provides an array substrate 100. The array substrate 100 includes a thin film transistor 10, and the thin film transistor 10 includes: an active layer 12 on one side of the substrate 11, and a gate layer 14 on the side of the active layer 12 away from the substrate 11.

[0063] In some embodiments, the active layer 12 may include a metal oxide material and / or a metal oxynitride material. The metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In 2 O 3 :Sn, In 2 O 3 :Mo, Cd 2 SnO 4 、ZnO:Al, TiO 2 :Nb and one or more of Cd-Sn-O.

[0064] The metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or a combination thereof.

[0065] The material of the active layer 12 can be in an amorphous, partially crystalline, single crystal, or polycrystalline state, and can also be a single-layer or multi-layer structure.

[0066] As Figure 2 shown, the active layer 12 includes: a first sub-layer 121 and a second sub-layer 122 located on the side of the first sub-layer 121 away from the substrate 11. The mobility of the first sub-layer 121 is higher than that of the second sub-layer 122; and the average thickness d1 of the first sub-layer 121 is less than the average thickness d2 of the second sub-layer 122.

[0067] Among them, the average thickness refers to the average value of the thicknesses measured in different regions selected at a certain distance under the same field of view. It can be understood that the thickness of the first sub-layer 121 is the dimension of the first sub-layer 121 in the direction Y perpendicular to the substrate 11, and the thickness of the second sub-layer 122 is the dimension of the second sub-layer 122 in the direction Y perpendicular to the substrate 11.

[0068] By setting that the mobility of the first sub-layer 121 is greater than that of the second sub-layer 122, and the average thickness d1 of the first sub-layer 121 is less than the average thickness d2 of the second sub-layer 122, while achieving a relatively high mobility of the thin film transistor 10, the thin film transistor 10 can have better electrical stability, so as to improve the switching ability and service life of the thin film transistor 10. The reasons why the thin film transistor 10 provided in the above embodiments has relatively high mobility and good electrical stability are as follows:

[0069] On the one hand, since the mobility of the first sublayer 121 is relatively high, for example, the mobility of the first sublayer 121 is greater than or equal to 20 cm 2 / V*s, high mobility materials are more likely to absorb visible light to generate photogenerated carriers, namely, photogenerated defects. The generation of photogenerated defects will affect the electrical stability of the thin film transistor 10, resulting in a shorter life of the thin film transistor 10.

[0070] In the embodiment of the present disclosure, the average thickness d1 of the first sublayer 121 is smaller than the average thickness d2 of the second sublayer 122, so as to form a first sublayer 121 with a relatively small average thickness d1. This can reduce the number of photogenerated defects in the first sublayer 121, thereby reducing the impact of photogenerated defects on the electrical stability of the thin film transistor 10 and improving the life of the thin film transistor 10.

[0071] On the other hand, Figure 2 and Figure 3 As shown, Figure 3 1 is a schematic diagram of the conduction principle of the thin film transistor 10 according to some embodiments. The thin film transistor 10 further includes: a gate insulating layer 13, the gate insulating layer 13 is located between the active layer 12 and the gate layer 14, due to defects at the interface of the gate insulating layer 13, such as defects formed during film formation, some carriers of the active layer 12 will be captured by the gate insulating layer 13, which is easy to reduce the electrical stability of the thin film transistor 10, thereby affecting the switching capability and service life of the thin film transistor 10.

[0072] Since the active layer 12 includes a first sublayer 121 and a second sublayer 122, and the mobility of the first sublayer 121 is higher than that of the second sublayer 122, the active layer 12 includes a first conductive channel 12a, and second conductive channels 12b located on both sides of the first conductive channel 12a along a direction Y perpendicular to the substrate 11, and the carrier concentration of the first conductive channel 12a is greater than the carrier concentration of the second conductive channel 12b.

[0073] That is, the carriers of the active layer 12 are concentrated in the first conductive channel 12a. If the first conductive channel 12a can be relatively far away from the gate insulating layer 13, the carriers of the first conductive channel 12a will not be captured by defects at the interface of the gate insulating layer 13, which is beneficial to improving the electrical stability of the thin film transistor 10.

[0074] Exemplarily, factors affecting the position of the first conductive channel 12a in the active layer 12 include: the electric field strength of the gate layer 14, the difference in mobility between the first sublayer 121 and the second sublayer 122, and the difference in average thickness between the first sublayer 121 and the second sublayer 122.

[0075] For example, since the electric field of the gate layer 14 is strong, the gate layer 14 will pull the first conductive channel 12a toward the gate insulating layer 13. The second sublayer 122 with a relatively large average thickness d2 can pull the first conductive channel 12a away from the gate insulating layer 13. The mobility of the first sublayer 121 is higher than that of the second sublayer 122, and carriers tend to be transmitted at a position with high mobility. Therefore, the high mobility of the first sublayer 121 will pull the first conductive channel 12a away from the gate insulating layer 13.

[0076] In the embodiment of the present disclosure, by setting the mobility of the first sub-layer 121 to be greater than the mobility of the second sub-layer 122, and the average thickness d1 of the first sub-layer 121 to be less than the average thickness d2 of the second sub-layer 122, it is possible to make the ratio of the distance d3 between the first conductive channel 12a and the surface m1 of the active layer 12 away from the substrate 11 in the direction Y perpendicular to the substrate 11 to the average thickness d2 of the second sub-layer 122 to be greater than 1 / 2, that is, d3 / d2>1 / 2.

[0077] When the ratio of the distance d3 between the first conductive channel 12a and the surface m1 of the active layer 12 away from the substrate 11 to the average thickness d2 of the second sublayer 122 is greater than 1 / 2, the capture of carriers of the first conductive channel 12a by interface defects of the gate insulating layer 13 can be reduced, so that the first conductive channel 12a maintains a high carrier concentration, thereby improving the electrical stability of the thin film transistor 10, thereby extending the switching capability and service life of the thin film transistor 10.

[0078] For example, Figure 3 As shown, the first conductive channel 12a is located near the interface between the first sublayer 121 and the second sublayer 122. For example, in the direction Y perpendicular to the substrate 11, the size d5 of the portion of the first conductive channel 12a located in the first sublayer 121 accounts for a ratio of the first sublayer 121 that is approximately equal to the size d6 of the portion of the first conductive channel 12a located in the second sublayer 122 accounts for a ratio of the second sublayer 122, that is, d6 / d2≈d5 / d1.

[0079] On the other hand, when in the direction Y perpendicular to the substrate 11, the ratio of the size d5 of the portion of the first conductive channel 12a located in the first sub-layer 121 to the first sub-layer 121 is approximately equal to the ratio of the size d6 of the portion of the first conductive channel 12a located in the second sub-layer 122 to the second sub-layer 122, a portion of the first conductive channel 12a is located in the first sub-layer 121 having higher mobility, which increases the mobility of the thin film transistor 10.

[0080] Moreover, the second sublayer 122 can provide carriers to the first sublayer 121 having higher mobility, so as to increase the carrier concentration of the first sublayer 121 , thereby increasing the mobility of the thin film transistor 10 .

[0081] Therefore, the embodiment of the present disclosure sets the mobility of the first sublayer 121 to be greater than the mobility of the second sublayer 122, and the average thickness d1 of the first sublayer 121 is less than the average thickness d2 of the second sublayer 122, so that a part of the first conductive channel 12a can be located in the first sublayer 121 with higher mobility, which is beneficial to the transmission of carriers, and the second sublayer 122 can provide carriers to the first sublayer 121, so that the thin film transistor 10 has a higher mobility. Moreover, the first conductive channel 12a can be relatively far away from the gate insulating layer 13, reducing the capture of carriers of the first conductive channel 12a by the interface defects of the gate insulating layer 13, so that the first conductive channel 12a maintains a higher carrier concentration, so as to improve the electrical stability of the thin film transistor 10, thereby extending the switching capability and service life of the thin film transistor 10. Therefore, the embodiment of the present disclosure improves the electrical stability of the thin film transistor 10 while ensuring that the thin film transistor 10 has a higher mobility, thereby achieving the purpose of enhancing the switching capability and extending the service life of the thin film transistor 10.

[0082] In some embodiments, Figure 2 As shown, the ratio of the average thickness d1 of the first sub-layer 121 to the average thickness d2 of the second sub-layer 122 is in the range of 0.1 to 0.85, that is, the ratio d1 / d2 is in the range of 0.1 to 0.85.

[0083] Exemplarily, the ratio of the average thickness d1 of the first sublayer 121 to the average thickness d2 of the second sublayer 122 is 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.85, etc., which is not limited here.

[0084] By setting the ratio of the average thickness d1 of the first sublayer 121 to the average thickness d2 of the second sublayer 122 to be in the range of 0.1 to 0.85, the average thickness d1 of the first sublayer 121 is smaller than the average thickness d2 of the second sublayer 122 .

[0085] In some embodiments, Figure 3 As shown, the average thickness d1 of the first sublayer 121 ranges from 5 nm to 25 nm, and the average thickness d2 of the second sublayer 122 ranges from 30 nm to 50 nm.

[0086] Exemplarily, the average thickness d1 of the first sub-layer 121 is 5 nm, 10 nm, 15 nm, 20 nm or 25 nm, etc., which is not limited here.

[0087] Exemplarily, the average thickness d2 of the second sub-layer 122 is 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc., which is not limited here.

[0088] likeFigure 3 As shown, by setting the average thickness d1 of the first sublayer 121 to be less than or equal to 25 nm, the average thickness d1 of the first sublayer 121 is relatively small compared with the average thickness d2 of the second sublayer 122, which effectively solves the problem of degradation of the turn-off performance of the thin film transistor 10 caused by excessive photo-induced defects due to the excessive average thickness d2 of the first sublayer 121, thereby improving the electrical stability of the thin film transistor 10.

[0089] Moreover, by setting the average thickness d1 of the first sublayer 121 to be greater than or equal to 5 nm, it can be effectively ensured that the first sublayer 121 has a higher carrier concentration.

[0090] like Figure 3 As shown, by setting the average thickness d2 of the second sublayer 122 to be greater than or equal to 30 nm, the setting of the second sublayer 122 can move the first conductive channel 12a away from the gate insulating layer 13, thereby reducing the capture of carriers of the first conductive channel 12a by interface defects of the gate insulating layer 13.

[0091] For example, Figure 4 As shown, Figure 4 1 is another conduction principle diagram of the thin film transistor 10 according to some embodiments. If the average thickness d2 of the second sublayer 122 is too small, the first conductive channel 12a will be close to the gate insulating layer 13, resulting in a more serious problem of the interface defects of the gate insulating layer 13 capturing the carriers of the first conductive channel 12a, causing the electrical stability of the thin film transistor 10 to deteriorate.

[0092] Therefore, the setting of the average thickness d2 of the second sublayer 122 being greater than or equal to 30 nm can reduce the capture of carriers of the first conductive channel 12a by interface defects of the gate insulation layer 13, so as to improve the electrical stability of the thin film transistor 10, thereby extending the switching capability and service life of the thin film transistor 10.

[0093] For example, Figure 5 As shown, Figure 5 1 is another conduction principle diagram of the thin film transistor 10 according to some embodiments. If the average thickness d2 of the second sublayer 122 is too large, for example, the average thickness d2 of the second sublayer 122 is greater than 50 nm, the first conductive channel 12a will be concentrated in the second sublayer 122, that is, the first conductive channel 12a will be far away from the first sublayer 121 with higher mobility, which will cause the mobility of the thin film transistor 10 to decrease.

[0094] Therefore, by setting the average thickness d2 of the second sublayer 122 to be less than or equal to 50 nm, the problem of the first conductive channel 12 a being concentrated in the second sublayer 122 can be effectively prevented from occurring, thereby improving the mobility of the thin film transistor 10 .

[0095] Please see again Figure 3 Under the combined effect of the electric field strength of the gate layer 14, the mobility of the first sublayer 121 being higher than the mobility of the second sublayer 122, the average thickness d1 of the first sublayer 121 being in the range of 5nm to 25nm, and the average thickness d2 of the second sublayer 122 being in the range of 30nm to 50nm, in the direction Y perpendicular to the substrate 11, the size d5 of the portion of the first conductive channel 12a located in the first sublayer 121 accounts for a ratio of the first sublayer 121 to the size d6 of the portion of the first conductive channel 12a located in the second sublayer 122 accounts for a ratio of the second sublayer 122 to the second sublayer 122 is approximately equal.

[0096] This arrangement allows the first conductive channel 12a to be away from the interface of the gate insulating layer 13, effectively solving the problem of carrier capture of the first conductive channel 12a by the interface defects of the gate insulating layer 13, thereby improving the electrical stability of the thin film transistor 10, and extending the switching capability and service life of the thin film transistor 10. Moreover, in the direction Y perpendicular to the substrate 11, the proportion of the size d5 of the portion of the first conductive channel 12a located in the first sublayer 121 to the first sublayer 121 is substantially equal to the proportion of the size d6 of the portion of the first conductive channel 12a located in the second sublayer 122 to the second sublayer 122. The second sublayer 122 can provide carriers to the first sublayer 121, so as to further increase the concentration of carriers in the first sublayer 121 and improve the mobility of the thin film transistor 10.

[0097] Figure 6 is a basic characteristic curve diagram of the thin film transistor 10 according to some embodiments. The horizontal axis represents the gate-source voltage of the thin film transistor 10, which is expressed as V GS , in V; the ordinate represents the logarithmic coordinate of the drain current of the thin film transistor 10, expressed as I DS , the unit is A. The structure of the thin film transistor 10 provided in Example 1 is as follows Figure 3 As shown, in Example 1, the average thickness d1 of the first sublayer 121 ranges from 5 nm to 25 nm, and the average thickness d2 of the second sublayer 122 ranges from 30 nm to 50 nm. The structure of the thin film transistor 10 provided in Example 2 is as shown in FIG. Figure 5 As shown, in Example 2, the average thickness d1 of the first sublayer 121 ranges from 5 nm to 25 nm, and the average thickness d2 of the second sublayer 122 is greater than 50 nm, that is, the average thickness d2 of the second sublayer 122 is too large. Examples 1 and 2 are multiple curves obtained by testing the basic characteristics of multiple thin film transistors 10.

[0098] from Figure 6It can be seen that there is a difference N between the basic characteristic curve of the thin film transistor 10 represented by Example 1 and the basic characteristic curve of the thin film transistor 10 represented by Example 2. That is, under the same gate-source voltage, the drain current of the thin film transistor 10 represented by Example 2 is smaller than the drain current of the thin film transistor 10 represented by Example 1. Therefore, Figure 6 It can be seen that the thin film transistor 10 represented by Example 1 has a higher mobility.

[0099] Figure 7 is a graph showing electrical stability of the thin film transistor 10 according to some embodiments, Figure 8 is another electrical stability curve diagram of the thin film transistor 10 according to some embodiments. The abscissa represents the gate-source voltage of the thin film transistor 10, which is expressed as V GS , in V; the ordinate represents the logarithmic coordinate of the drain current of the thin film transistor 10, expressed as I DS , unit is A. Figure 7 The structure of the corresponding thin film transistor 10 is as follows: Figure 3 As shown, it is represented as Example 1; Figure 8 The structure of the corresponding thin film transistor 10 is as follows: Figure 5 As shown, it is represented as Example 2. Different curves represent the voltage V applied to the gate 141 of the thin film transistor 10. GS And the V obtained for different durations GS The durations of the curves are 0s, 100s, 600s, 1800s and 3600s. DS When the value gradually increases, it means that the thin film transistor 10 is turned on. Different curves represent the V GS The difference between the threshold voltage and the threshold voltage of the thin film transistor 10 is △V th .

[0100] from Figure 7 It can be seen that the threshold voltage shift ΔV of the thin film transistor 10 shown in Example 1 th Less than 2V; from Figure 8 It can be seen that the threshold voltage shift ΔV of the thin film transistor 10 shown in Example 2 th is greater than 5 V, therefore, the thin film transistor 10 shown in Example 1 has good electrical stability.

[0101] Therefore, by Figures 6 to 8 It can be seen that the thin film transistor 10 provided in the embodiment of the present disclosure not only has a higher mobility, but also has better electrical stability.

[0102] In some embodiments, Figure 2 and Figure 3As shown, the mobility of the first sublayer 121 is greater than or equal to 20 cm 2 / V*s. So that the first sub-layer 121 has a higher mobility,

[0103] In some embodiments, Figure 2 and Figure 3 As shown, the mobility of the second sublayer 122 ranges from 5 cm 2 / V*s~15cm 2 / V*s.

[0104] For example, the mobility of the second sublayer 122 is 5 cm 2 / V*s、7cm 2 / V*s、8cm 2 / V*s、10cm 2 / V*s、12cm 2 / V*s, 13cm 2 / V*s or 15cm 2 / V*s, etc., there is no limitation here.

[0105] The range of mobility through the second sublayer 122 is 5 cm 2 / V*s~15cm 2 / V*s is set so that the mobility of the second sublayer 122 is lower than that of the first sublayer 121, and the second sublayer 122 can provide carriers to the first sublayer 121 to increase the concentration of carriers in the first sublayer 121. Moreover, compared with the first sublayer 121, the second sublayer 122 with relatively low mobility has stable light-sensing performance to reduce the generation of photo-induced defects, which is beneficial to improving the electrical stability of the thin film transistor 10.

[0106] In some embodiments, Figure 2 and Figure 3 As shown, the optical band gap Eg1 of the material of the first sublayer 121 is smaller than the optical band gap Eg2 of the material of the second sublayer 122, that is, Eg1 <Eg2。

[0107] Exemplarily, the optical band gap Eg1 of the material of the first sublayer 121 is less than or equal to 2.9 eV, that is, Eg1≤2.9 eV.

[0108] Exemplarily, the optical band gap Eg2 of the material of the second sublayer 122 is greater than or equal to 3 eV, that is, Eg2 ≥ 3 eV.

[0109] By setting the optical band gap Eg1 of the material of the first sublayer 121 to be smaller than the optical band gap Eg2 of the material of the second sublayer 122 , the second sublayer 122 has better light stability, which is beneficial to improving the electrical stability of the thin film transistor 10 .

[0110] Figure 9 FIG. 1 is a cross-sectional microscopic morphology image of a thin film transistor 10 according to some embodiments, taken using a transmission electron microscope (TEM). Figure 10 is an element energy spectrum (EDX) of the active layer 12 of the thin film transistor 10 according to some embodiments. Figure 9 It can be seen that the active layer 12 includes a first sublayer 121 and a second sublayer 122. Figure 10 As shown, the material of the active layer 12 includes: indium (In), gallium (Ga) and zinc (Zn). Figure 10 The reddish brown color in the graph represents indium. The density of indium in the first sublayer 121 and the density of indium in the second sublayer 122 are substantially equal. Therefore, the indium content in the first sublayer 121 and the indium content in the second sublayer 122 are substantially equal. Figure 10 The purple color in the figure represents zinc. The density of zinc in the first sublayer 121 is greater than the density of zinc in the second sublayer 122 . Therefore, the zinc content of the first sublayer 121 is greater than the zinc content of the second sublayer 122 . Figure 10 The blue color in represents gallium. The density of gallium in the first sublayer 121 is less than the density of gallium in the second sublayer 122 . Therefore, the gallium content of the first sublayer 121 is less than the gallium content of the second sublayer 122 .

[0111] It should be noted that the element content in the embodiments of the present disclosure may refer to the mass percentage of the element, or may be the atomic percentage, or may refer to the proportion of the element in the entire film layer.

[0112] Exemplarily, the tin content of the first sub-layer 121 is greater than the tin content of the second sub-layer 122 .

[0113] Exemplarily, the ratio of the zinc content of the first sublayer 121 to the zinc content of the second sublayer 122 is in the range of 1.1 to 2. For example, the ratio of the zinc content of the first sublayer 121 to the zinc content of the second sublayer 122 is 1.1, 1.2,

[0114] 1.3, 1.4, 1.5, 1.7, 1.8, 1.9 or 2, etc., there is no limitation here.

[0115] Exemplarily, the ratio of the gallium content of the second sublayer 122 to the gallium content of the first sublayer 121 ranges from 2 to 5. For example, the ratio of the gallium content of the second sublayer 122 to the gallium content of the first sublayer 121 is 2, 3, 4 or 5, etc., which is not limited here.

[0116] By setting different contents of zinc, gallium, tin and other elements in the first sub-layer 121 and the second sub-layer 122 , the mobility of the first sub-layer 121 is set higher than the mobility of the second sub-layer 122 .

[0117] In some examples, such as Figure 2As shown, the material of the first sublayer 121 includes at least one of indium gallium oxide, indium tin zinc oxide and indium gallium zinc tin oxide, and the material of the second sublayer 122 includes indium gallium zinc oxide.

[0118] For example, the atomic ratio of indium gallium zinc oxide in the second sub-layer 122 is In:Ga:Zn=1:1:1.

[0119] When the material of the second sub-layer 122 is indium gallium zinc oxide, the material of the second sub-layer 122 does not include tin, so that the tin content of the first sub-layer 121 is greater than the tin content of the second sub-layer 122 .

[0120] It should be noted that the material of the second sublayer 122 in the embodiment of the present disclosure includes but is not limited to indium gallium zinc oxide, that is, if there is a material with properties very close to indium gallium zinc oxide, it can also be used to make the second sublayer 122. As long as the second sublayer 122 can work together with the first sublayer 121 with high mobility, the thin film transistor 10 can have high mobility and good electrical stability.

[0121] In some embodiments, Figure 2 , Figure 11 and Figure 12 As shown, the thin film transistor 10 further includes: an interlayer dielectric layer 15, which is located on the side of the gate layer 14 away from the substrate 11. The interlayer dielectric layer 15 includes: a first interlayer dielectric layer 151 and a second interlayer dielectric layer 152 arranged in a direction away from the substrate 11. The content of hydrogen atoms in the first interlayer dielectric layer 151 is less than that in the second interlayer dielectric layer 152; the density of the first interlayer dielectric layer 151 is less than that of the second interlayer dielectric layer 152.

[0122] Exemplarily, the material of the first interlayer dielectric layer 151 is silicon oxide, and the material of the second interlayer dielectric layer 152 is silicon nitride.

[0123] It should be noted that if Figure 4 As shown, the active layer 12 includes: a channel region and a conductive region. For example, the region of the active layer 12 covered by the gate layer 14 is the channel region, and the region of the active layer 12 not covered by the gate layer 14 is the conductive region. By bringing the first interlayer dielectric layer 151 having a smaller content of hydrogen atoms into contact with the active layer 12, the problem of conductive channel region caused by hydrogen atoms entering the active layer 12 can be effectively avoided.

[0124] However, the first interlayer dielectric layer 151 formed of silicon oxide with a low content of hydrogen atoms has low compactness, which can also be understood as the first interlayer dielectric layer 151 having a porous characteristic and being easily corroded by water and oxygen. The second interlayer dielectric layer 152 formed of silicon nitride has good compactness and a strong barrier capability to water and oxygen in the second interlayer dielectric layer 152. By providing the interlayer dielectric layer 15 including the second interlayer dielectric layer 152, the barrier capability of the interlayer dielectric layer 15 to water and oxygen is improved.

[0125] In some embodiments, Figure 12 As shown, the thin film transistor 10 also includes: a first via hole H1, the first via hole H1 passes through the interlayer dielectric layer 15; the first via hole H1 includes: a first hole H11 passing through the first interlayer dielectric layer 151 and a second hole H12 passing through the second interlayer dielectric layer 152; wherein, the boundary L1 of the first hole H1 enclosed by the first interlayer dielectric layer 151 is located on the inner side of the boundary L2 of the second hole H12 enclosed by the second interlayer dielectric layer 152.

[0126] That is to say, the hole wall of the first via hole H1 is in a step shape at the interlayer dielectric layer 15. Since the second interlayer dielectric layer 152 is easier to etch, when the first interlayer dielectric layer 151 and the second interlayer dielectric layer 152 are formed, the second interlayer dielectric layer 152 will shrink relative to the first interlayer dielectric layer 151, so that the hole wall of the first via hole H1 is in a step shape at the interlayer dielectric layer 15.

[0127] From the above introduction about the source-drain metal layer 16, it can be seen that the source 161 and the drain 162 are connected to the active layer 12 through the first via H1 penetrating the interlayer dielectric layer 15. The hole wall of the first via H1 is stepped at the interlayer dielectric layer 15, which facilitates the deposition of the source-drain metal layer 16 in the first via H1 and is beneficial to the overlap of the source 161 and the drain 162 with the active layer 12.

[0128] In some examples, such as Figure 11 and Figure 12 As shown, in the orthographic projection onto the substrate 11 , the distance d7 between the boundary L1 of the first interlayer dielectric layer 151 and the boundary L2 of the second interlayer dielectric layer 152 ranges from 0.5 μm to 1.5 μm.

[0129] For example, in the orthographic projection onto the substrate 11 , a distance d7 between a boundary L1 of the first interlayer dielectric layer 151 and a boundary L2 of the second interlayer dielectric layer 152 is 0.5 μm, 0.6 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.3 μm or 1.5 μm, etc., which is not limited here.

[0130] In the orthographic projection onto the substrate 11 , a distance d7 between a boundary L1 of the first interlayer dielectric layer 151 and a boundary L2 of the second interlayer dielectric layer 152 ranges from 0.5 μm to 1.5 μm, which is beneficial for the overlap of the source electrode 161 and the drain electrode 162 with the active layer 12 .

[0131] In some embodiments, Figure 11 and Figure 12 As shown, the second interlayer dielectric layer 152 has a first surface m3 close to the substrate 11 and a second surface m4 away from the substrate 11 , and the first surface m3 of the second interlayer dielectric layer 152 is retracted relative to the second surface m4 of the second interlayer dielectric layer 152 .

[0132] That is, in the second direction X, the size of the first surface m3 of the second interlayer dielectric layer 152 is smaller than the size of the second surface m4 of the second interlayer dielectric layer 152. The second direction X is parallel to the plane where the substrate 11 is located.

[0133] Exemplarily, the connection between the boundary L2 of the second interlayer dielectric layer 152 and the first surface m3 of the second interlayer dielectric layer 152 is an arc shape K, that is, the connection between the side surface of the second interlayer dielectric layer 152 and the first surface m3 of the second interlayer dielectric layer 152 is an arc surface.

[0134] In some embodiments, Figure 2 As shown, the gate layer 14 covers the gate insulating layer 13 .

[0135] Exemplarily, the gate insulating layer 13 may be formed by using the gate layer 14 as a mask, and the active layer 12 may be subjected to conductor processing. For details, refer to the introduction of the preparation method of the array substrate 100 , which will not be described in detail here.

[0136] In some embodiments, Figure 2 As shown, the source-drain metal layer 16 is located on a side of the active layer 12 away from the substrate 11 , and the source-drain metal layer 16 is connected to the second sub-layer 122 .

[0137] That is to say, Figure 2 The thin film transistor 10 shown is a top-gate thin film transistor 10 with a top-contact structure.

[0138] In other embodiments, Figure 13 As shown, the source-drain metal layer 16 is located on a side of the active layer 12 close to the substrate 11 , and the source-drain metal layer 16 is connected to the first sub-layer 121 .

[0139] That is to say, Figure 2 The thin film transistor 10 shown is a top-gate thin film transistor 10 with a bottom contact structure.

[0140] By configuring the active layer 12 to include: a first sublayer 121 and a second sublayer 122 located on the side of the first sublayer 121 away from the substrate 11, and the mobility of the first sublayer 121 is higher than the mobility of the second sublayer 122, and the average thickness d1 of the first sublayer 121 is less than the average thickness d2 of the second sublayer 122, a thin film transistor 10 with higher mobility and better electrical stability can be obtained. The thin film transistor 10 can be a thin film transistor 10 with a top gate top contact structure, or a thin film transistor 10 with a top gate bottom contact structure.

[0141] like Figure 2 As shown, some embodiments of the present disclosure further provide an array substrate 100, comprising: a substrate 11 and a plurality of thin film transistors 10 disposed on the substrate 11, wherein at least one thin film transistor 10 among the plurality of thin film transistors 10 is the thin film transistor 10 described in any of the above embodiments.

[0142] In some embodiments, Figure 2 As shown, the array substrate 100 further includes a light shielding layer 17 and a buffer layer 18 . The light shielding layer 17 is located on a side of the active layer 12 close to the substrate 11 , and the buffer layer 18 is located between the active layer 12 and the light shielding layer 17 .

[0143] The light shielding layer 17 can protect the active layer 12 of the thin film transistor 10 from being affected by ambient light.

[0144] In some embodiments, Figure 2 and Figure 3 As shown, the thin film transistor 10 further includes a gate insulating layer 13, which is located between the active layer 12 and the gate layer 14. The average thickness d8 of the buffer layer 18 between the light shielding layer 17 and the active layer 12 is greater than the average thickness d9 of the gate insulating layer 13, that is, d8>d9.

[0145] It can be understood that the thickness of the buffer layer 18 between the light shielding layer 17 and the active layer 12 is the size of the buffer layer 18 between the light shielding layer 17 and the active layer 12 in the direction Y perpendicular to the substrate 11. The thickness of the gate insulating layer 13 is the size of the gate insulating layer 13 in the direction Y perpendicular to the substrate 11.

[0146] The light-shielding layer 17 has an electric field strength, and the electric field strength of the light-shielding layer 17 is less than that of the gate layer 14. By setting the average thickness d8 of the buffer layer 18 between the light-shielding layer 17 and the active layer 12 to be greater than the average thickness d9 of the gate insulating layer 13, the influence of the electric field strength of the light-shielding layer 17 on the position of the first conductive channel 12a is reduced. The position of the first conductive channel 12a is mainly affected by the electric field strength of the gate layer 14 and the mobilities and average thicknesses of the first sub-layer 121 and the second sub-layer 122, so that the position of the first conductive channel 12a is maintained near the interface between the first sub-layer 121 and the second sub-layer 122, thereby improving the mobility and electrical stability of the thin film transistor 10.

[0147] In some embodiments, as Figure 2 shown, the array substrate 100 further includes: a first passivation layer 19, a planarization layer 21, a first electrode layer 22, a second passivation layer 23, and a second electrode layer 24. The first passivation layer 19 is located on the side of the source-drain metal layer 16 away from the substrate 11, and the planarization layer 21 is located on the side of the first passivation layer 19 away from the substrate 11. The first electrode layer 22 is located on the side of the planarization layer 21 away from the substrate 11, and the first electrode layer 22 can be a common electrode. The second passivation layer 23 is located on the side of the first electrode layer 22 away from the substrate 11, and the second electrode layer 24 is located on the side of the second passivation layer 23 away from the substrate 11. The second electrode layer 24 is connected to the drain 162 through a second via hole H2 penetrating through the second passivation layer 23, the planarization layer 21, and the first passivation layer 19.

[0148] In some embodiments, as Figure 2 shown, the electrical stability of the thin film transistor 10 can be improved by enhancing the passivation ability of the gate insulating layer 13.

[0149] Since the gate insulating layer 13 with a higher passivation ability has relatively fewer interface defects, the trapping of carriers in the first conductive channel 12a by the interface defects of the gate insulating layer 13 can be reduced, so that the first conductive channel 12a maintains a high carrier concentration, thereby improving the electrical stability of the thin film transistor 10.

[0150] In some embodiments, as Figure 2 shown, the size of the thin film transistor 10 can be increased to increase the size of the channel region of the thin film transistor. The increase in the size of the channel region can reduce the current density and improve the electrical stability of the thin film transistor 10.

[0151] As Figure 14 shown, an embodiment of the present disclosure provides a method for manufacturing an array substrate, and the method includes steps:

[0152] R1 to R12.

[0153] R1, asFigure 15 As shown, a substrate 11 is provided.

[0154] Exemplarily, the substrate 11 includes but is not limited to a glass substrate, and the embodiments of the present disclosure will be described by taking the substrate 11 as a glass substrate as an example.

[0155] R2, such as Figure 15 As shown, a light-shielding layer 17 is formed on one side of the substrate 11.

[0156] Exemplarily, the step of forming the light-shielding layer 17 includes: forming a light-shielding metal layer on the substrate 11, and patterning the light-shielding metal layer to form the final light-shielding layer 17. Among them, the method of forming the light-shielding layer 17 includes but is not limited to magnetron sputtering, and the patterning method includes but is not limited to lithography, imprinting and other means, and the etching transfer means is not limited to wet etching, dry reaction, etc.

[0157] It should be noted that since the thin-film transistor 10 in the embodiments of the present disclosure is a top-gate thin-film transistor, in order to ensure that the active layer 12 of the thin-film transistor 10 is not affected by ambient light, it is necessary to prepare the light-shielding layer 17. Among them, the material of the light-shielding layer 17 includes but is not limited to Mo-based alloys of molybdenum Mo and corresponding composite metal structures of copper Cu and aluminum Al.

[0158] R3, such as Figure 15 As shown, a buffer layer 18 is formed on the side of the light-shielding layer 17 away from the substrate 11.

[0159] Exemplarily, the material of the buffer layer 18 is silicon oxide, or a composite film layer of silicon nitride and silicon oxide, and the thickness of the buffer layer 18 is 200 nm to 500 nm. For example, the thickness of the buffer layer 18 is 200 nm, 300 nm, 400 nm or 500 nm, etc., and there is no limitation here.

[0160] Exemplarily, as Figure 11 and Figure 12 shown, the buffer layer 18 includes: a first film layer 181 and a second film layer 182, wherein the material of the first film layer 181 is silicon oxide, and the material of the second film layer 182 is silicon nitride.

[0161] The first film layer 181 formed of silicon oxide has the characteristic of being porous and is easily eroded by water and oxygen. The second film layer 182 formed of silicon nitride has a strong barrier ability to water and oxygen. By providing the buffer layer 18 including the first film layer 181 and the second film layer 182, the barrier ability of the buffer layer 18 to water and oxygen is improved.

[0162] R4, such as Figure 15 As shown, an active layer 12 is formed on the side of the buffer layer 18 away from the substrate 11.

[0163] Exemplarily, the active layer 12 includes: a first sub-layer 121 and a second sub-layer 122 located on a side of the first sub-layer 121 away from the substrate 11.

[0164] For example, the material of the first sub-layer 121 includes at least one of indium gallium oxide, indium tin zinc oxide, and indium gallium zinc tin oxide. The material of the second sub-layer 122 is indium gallium zinc oxide, and the atomic ratio of indium gallium zinc oxide is In:Ga:Zn = 1:1:1. The mobility of the first sub-layer 121 is greater than that of the second sub-layer 122, and the average thickness d1 of the first sub-layer 121 is less than the average thickness d2 of the second sub-layer 122. While improving the mobility of the thin-film transistor 10, the stability of the thin-film transistor 10 under electrical stress can be improved.

[0165] It should be noted that the material of the second sub-layer 122 in the embodiments of the present disclosure includes but is not limited to indium gallium zinc oxide, that is, if there is a material with properties very close to indium gallium zinc oxide, it can also be used to fabricate the second sub-layer 122. As long as the second sub-layer 122 can cooperate with the first sub-layer 121 with high mobility to improve the mobility of the thin-film transistor 10 and improve the stability of the thin-film transistor 10 under electrical stress.

[0166] In some examples, the average thickness d1 of the first sub-layer 121 ranges from 5 nm to 25 nm. For example, the average thickness d1 of the first sub-layer 121 is 5 nm, 10 nm, 15 nm, 20 nm, or 25 nm, etc., and there is no limitation here. The average thickness d2 of the second sub-layer 122 ranges from 30 nm to 50 nm. For example, the average thickness d2 of the second sub-layer 122 is 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm, etc., and there is no limitation here.

[0167] In some examples, the steps of forming the active layer 12 include: forming a stacked first conductive layer and second conductive layer on a side of the buffer layer 18 away from the substrate 11, and patterning the first conductive layer and the second conductive layer to form the first sub-layer 121 and the second sub-layer 122, and the first sub-layer 121 and the second sub-layer 122 form the final active layer 12.

[0168] In some examples, the steps of forming the active layer 12 further include depositing a channel. An indium tin zinc oxide layer with an average thickness of 30 nm can be deposited by magnetron sputtering as the channel of the thin-film transistor 10, and then the channel is annealed to obtain the active layer 12.

[0169] R5, as Figure 15 As shown, a gate insulating layer 13 is formed on a side of the active layer 12 away from the substrate 11, and a gate electrode layer 14 is formed on a side of the gate insulating layer 13 away from the substrate 11.

[0170] Exemplarily, the steps of forming the gate insulating layer 13 and the gate layer 14 include: forming a first insulating layer on the side of the active layer 12 away from the substrate 11, forming a gate metal layer on the side of the first insulating layer away from the substrate 11, patterning the gate metal layer to form the gate layer 14. Using the gate layer 14 as a mask to etch the first insulating layer to form the gate insulating layer 13, and the gate insulating layer 13 exposes a part of the active layer 12, and the exposed part of the active layer 12 by the gate insulating layer 13 is made conductive. Specifically, the conductivity process can select at least one gas plasma such as helium (He), argon (Ar), hydrogen (H 2 ) and ammonia (NH 3 ) for processing.

[0171] All of the gate insulating layer 13 around the gate layer 14 is removed, and the exposed active layer 12 is made conductive, so as to obtain a thin film transistor 10 with self-aligned gate layer 14 and conductive channel, which can simplify the process steps, improve the reliability of the preparation of the thin film transistor 10, and is beneficial to reducing the size of the thin film transistor 10.

[0172] Exemplarily, the gate layer 14 may include a buffer dielectric layer, a main conductive layer and a top protective layer arranged in a stacked manner. Specifically, the buffer dielectric layer is located on the side close to the substrate 11, and the materials of the buffer dielectric layer include but are not limited to titanium (Ti) and molybdenum (Mo) based alloys, etc., the materials of the main conductive layer include but are not limited to at least one of aluminum (Al) and copper (Cu), etc., and the materials of the top protective layer include but are not limited to titanium (Ti) and molybdenum (Mo) based alloys, etc.

[0173] Exemplarily, the material of the gate insulating layer 13 includes silicon oxide, and the average thickness range of the gate insulating layer 13 is 10nm - 30nm. For example, the average thickness of the gate insulating layer 13 is 10nm, 15nm, 20nm, 25nm or 30nm, etc., and there is no limitation here.

[0174] R6. As Figure 15 shown, an interlayer dielectric layer 15 is formed on the side of the gate layer 14 away from the substrate 11.

[0175] Exemplarily, the interlayer dielectric layer 15 is deposited and formed on the side of the gate layer 14 away from the substrate 11. Among them, the material of the interlayer dielectric layer 15 includes but is not limited to silicon oxide, or a composite film layer of silicon nitride and silicon oxide.

[0176] Exemplarily, the average thickness range of the interlayer dielectric layer 15 is 300nm - 600nm. For example, the average thickness of the interlayer dielectric layer 15 is 300nm, 350nm, 400nm, 450nm or 500nm, etc., and there is no limitation here.

[0177] For example, photolithography and etching are performed on the interlayer dielectric layer 15 to form a first via hole H1 that exposes a part of the active layer 12.

[0178] R7. As Figure 15 shown, a source-drain metal layer 16 is formed.

[0179] Exemplarily, the source electrode 161 and the drain electrode 162 of the thin film transistor 10 are located in the source-drain metal layer 16.

[0180] Exemplarily, the source electrode 161 and the drain electrode 162 are connected to the active layer 12 through different first via holes H1 that penetrate the interlayer dielectric layer 15.

[0181] R8. As Figure 15 shown, a first passivation layer 19 is formed on the side of the source-drain metal layer 16 away from the substrate 11.

[0182] Exemplarily, the material of the first passivation layer 19 includes silicon oxide. The average thickness range of the first passivation layer 19 is 300 nm to 400 nm. For example, the average thickness of the first passivation layer 19 is 300 nm, 320 nm, 340 nm, 360 nm, 400 nm, etc., and there is no limitation here.

[0183] R9. As Figure 16 shown, a planarization layer 21 is formed on the side of the first passivation layer 19 away from the substrate 11.

[0184] Exemplarily, a second via hole H21 is provided on the planarization layer 21. In the orthographic projection onto the substrate 11, the second via hole H21 overlaps with the drain electrode 162 of the thin film transistor 10.

[0185] R10. As Figure 16 shown, a first electrode layer 22 is formed on the side of the planarization layer 21 away from the substrate 11.

[0186] Exemplarily, the material of the first electrode layer 22 is a transparent conductive material. For example, the material of the first electrode layer 22 is indium tin oxide.

[0187] Exemplarily, the first electrode layer 22 can be a common electrode.

[0188] R11. As Figure 16 shown, a second passivation layer 23 is formed on the side of the first electrode layer 22 away from the substrate 11.

[0189] Exemplarily, a second via hole H2 is formed that penetrates the second passivation layer 23 and the first passivation layer 19, and the second via hole H2 also penetrates the planarization layer 21. The second via hole H2 overlaps with the second via hole H21. The second via hole H2 exposes a part of the drain electrode 162.

[0190] R12. As Figure 2As shown, a second electrode layer 24 is formed on a side of the second passivation layer 23 away from the substrate 11, and the array substrate 100 is obtained.

[0191] Exemplarily, the second electrode layer 24 is connected to the drain 162 through a second via hole H2 penetrating through the second passivation layer 23, the planarization layer 21, and the first passivation layer 19.

[0192] Exemplarily, the second electrode layer 24 is a pixel electrode. The pixel electrode is connected to the drain 162 and forms an electric field with the first electrode layer 22 (common electrode) in a Slit shape.

[0193] In the embodiment of the present disclosure, the array substrate 100 in which the active layer 12 of the thin film transistor 10 includes a first sub-layer 121 and a second sub-layer 122 is prepared through the above steps R1 to R12. In the thin film transistor 10, due to the fact that the mobility of the first sub-layer 121 is greater than that of the second sub-layer 122, and the average thickness d1 of the first sub-layer 121 is less than the average thickness d2 of the second sub-layer 122, a part of the first conductive channel 12a is located in the first sub-layer 121 with a higher mobility, which is beneficial to the transport of carriers. Moreover, the second sub-layer 122 can provide carriers to the first sub-layer 121, so that the thin film transistor 10 has a higher mobility. In addition, the first conductive channel 12a can be relatively far from the gate insulating layer 13, reducing the capture of carriers in the first conductive channel 12a by the interface defects of the gate insulating layer 13, so that the first conductive channel 12a maintains a high carrier concentration, improving the electrical stability of the thin film transistor 10, thereby extending the switching ability and service life of the thin film transistor 10. Therefore, in the embodiment of the present disclosure, while ensuring that the thin film transistor 10 has a high mobility, the electrical stability of the thin film transistor 10 is improved, achieving the purpose of extending the switching ability and service life of the thin film transistor 10.

[0194] The array substrate 100 includes the thin film transistor 10 provided in any one of the above embodiments. Therefore, the array substrate 100 provided in the embodiment of the present disclosure has all the beneficial effects of the thin film transistor 10 provided in any one of the above embodiments, which will not be elaborated herein.

[0195] As Figure 17 shown, some embodiments of the present disclosure further provide a display panel 1000. The display panel 1000 includes the array substrate 100 described in any one of the above embodiments. The display panel 1000 further includes a plurality of light-emitting devices 200. The array substrate 100 is used to drive the plurality of light-emitting devices 200 to emit light.

[0196] Exemplarily, as Figure 17 shown, the array substrate 100 further includes a plurality of scan signal lines GL and a plurality of data signal lines DL. The plurality of scan signal lines GL and the plurality of data signal lines DL are connected to the plurality of thin film transistors 10.

[0197] Exemplarily, the array substrate 100 includes a plurality of pixel driving circuits 101. The pixel driving circuit 101 includes a plurality of thin film transistors 10. For example, the thin film transistor 10 includes a driving transistor. The driving transistor is connected to the light emitting device 200 and is configured to drive the light emitting device 200 to emit light.

[0198] Exemplarily, the array substrate 100 further includes: a plurality of light emission control lines EL, a plurality of initialization signal lines Vinit, and a plurality of first voltage signal lines VDD. The scan signal line GL, the data signal line DL, the light emission control line EL, the initialization signal line Vinit, and the first voltage signal line VDD are connected to the pixel driving circuit 101. The scan signal line GL, the data signal line DL, the light emission control line EL, the initialization signal line Vinit, and the first voltage signal line VDD are configured to provide electrical signals to the pixel driving circuit 101 to enable the pixel driving circuit 101 to drive the light emitting device 200 to emit light.

[0199] The display panel 1000 includes the array substrate 100 provided in any of the above embodiments. Therefore, the display panel 1000 provided by the embodiments of the present disclosure has all the beneficial effects of the array substrate 100 provided in any of the above embodiments, which will not be elaborated herein.

[0200] As Figure 18 shown, some embodiments of the present disclosure further provide another display panel 1000. The display panel 1000 includes the array substrate 100 described in any of the above embodiments. The display panel 1000 further includes: a counter substrate 300 and a liquid crystal layer 400. The counter substrate is disposed opposite to and spaced apart from the array substrate 100. The liquid crystal layer 400 is disposed between the array substrate 100 and the counter substrate 300.

[0201] Exemplarily, a liquid crystal material is disposed in the liquid crystal layer 400. The counter substrate 300 is, for example, a color filter substrate. The array substrate 100 controls the degree of rotation of the liquid crystal material to implement the display operation of the display panel 1000.

[0202] The display panel 1000 includes the array substrate 100 provided in any of the above embodiments. Therefore, the display panel 1000 provided by the embodiments of the present disclosure has all the beneficial effects of the array substrate 100 provided in any of the above embodiments, which will not be elaborated herein.

[0203] As Figure 19 shown, some embodiments of the present disclosure provide a display device 2000. The display device 2000 includes: the display panel 1000 described in any of the above embodiments. The display device 2000 further includes: a driving chip, and the driving chip is configured to drive the display panel 1000 to perform display.

[0204] As Figure 19 shown, the display device 2000 can be any device that displays whether it is moving (e.g., video) or stationary (e.g., still image), and whether it is text or image. More specifically, it is contemplated that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones (e.g., cell phones), wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rear view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 19 In [reference] 5, the display device 2000 is taken as an example of a mobile phone for illustration.

[0205] As described above, this is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A thin film transistor, characterized in that: include: An active layer located on one side of a substrate, and a gate layer located on a side of the active layer away from the substrate; The active layer includes: a first sublayer and a second sublayer located on a side of the first sublayer away from the substrate, the mobility of the first sublayer is higher than the mobility of the second sublayer; and the average thickness of the first sublayer is smaller than the average thickness of the second sublayer.

2. The thin film transistor according to claim 1, characterized in that: The ratio of the average thickness of the first sub-layer to the average thickness of the second sub-layer is in the range of 0.1 to 0.

85.

3. The thin film transistor according to claim 2, characterized in that: The average thickness of the first sublayer is in the range of 5 nm to 25 nm.

4. The thin film transistor according to claim 3, characterized in that: The average thickness of the second sublayer is in the range of 30 nm to 50 nm.

5. The thin film transistor according to claim 1, characterized in that: The mobility of the first sublayer is greater than or equal to 20 cm 2 / V*s.

6. The thin film transistor according to claim 4, characterized in that: The mobility of the second sublayer is in the range of 5 cm 2 / V*s~15cm 2 / V*s.

7. The thin film transistor according to claim 1, characterized in that: The first sublayer and the second sublayer meet at least one of the following conditions: The zinc content of the first sublayer is greater than the zinc content of the second sublayer; The gallium content of the first sublayer is less than the gallium content of the second sublayer; The tin content of the first sub-layer is greater than the tin content of the second sub-layer.

8. The thin film transistor according to claim 7, characterized in that: The ratio of the zinc content of the first sublayer to the zinc content of the second sublayer is in the range of 1.1-2; and / or the ratio of the gallium content of the second sublayer to the gallium content of the first sublayer is in the range of 2-5.

9. The thin film transistor according to claim 1, characterized in that: The material of the first sublayer includes: at least one of indium gallium oxide, indium tin zinc oxide and indium gallium zinc tin oxide; and / or the material of the second sublayer includes: indium gallium zinc oxide.

10. The thin film transistor according to claim 1, characterized in that: Also includes: an interlayer dielectric layer, the interlayer dielectric layer being located on a side of the gate layer away from the substrate; The interlayer dielectric layer comprises: a first interlayer dielectric layer and a second interlayer dielectric layer arranged in a direction away from the substrate; The content of hydrogen atoms in the first interlayer dielectric layer is less than that in the second interlayer dielectric layer; and the compactness of the first interlayer dielectric layer is less than that of the second interlayer dielectric layer.

11. The thin film transistor according to claim 10, characterized in that: Also includes: a first via hole, the first via hole penetrating the interlayer dielectric layer; The first via hole comprises: a first hole penetrating the first interlayer dielectric layer and a second hole penetrating the second interlayer dielectric layer; The boundary of the first hole formed by the first interlayer dielectric layer is located inside the boundary of the second hole formed by the second interlayer dielectric layer.

12. The thin film transistor according to claim 11, characterized in that: The distance between the boundary of the first hole formed by the first interlayer dielectric layer and the boundary of the second hole formed by the second interlayer dielectric layer is in the range of 0.5 μm to 1.5 μm.

13. The thin film transistor according to any one of claims 1 to 12, characterized in that: Also includes: Source and drain metal layers; The source-drain metal layer is located at a side of the active layer away from the substrate, and the source-drain metal layer is connected to the second sub-layer; or, The source-drain metal layer is located on a side of the active layer close to the substrate, and the source-drain metal layer is connected to the first sub-layer.

14. An array substrate, characterized in that: include: substrate; A plurality of thin film transistors are disposed on the substrate, wherein at least one of the plurality of thin film transistors is the thin film transistor according to any one of claims 1 to 13.

15. The array substrate according to claim 14, characterized in that: Also includes: a light shielding layer and a buffer layer, wherein the light shielding layer is located between the substrate and the active layer of the thin film transistor, and the buffer layer is located between the light shielding layer and the active layer; The thin film transistor comprises: a gate insulating layer, wherein the gate insulating layer is located between the active layer and the gate layer of the thin film transistor; Wherein, an average thickness of a portion of the buffer layer located between the light shielding layer and the active layer is greater than an average thickness of the gate insulating layer.

16. A method for preparing an array substrate, characterized in that: include: An active layer is formed on one side of the substrate, the active layer comprising: a first sublayer and a second sublayer located on a side of the first sublayer away from the substrate, wherein the mobility of the first sublayer is higher than the mobility of the second sublayer; and an average thickness of the first sublayer is less than an average thickness of the second sublayer; A gate layer is formed on a side of the active layer away from the substrate.

17. The method for preparing an array substrate according to claim 16, characterized in that: Also includes: forming an interlayer dielectric layer on a side of the gate layer away from the substrate; The interlayer dielectric layer includes: a first interlayer dielectric layer and a second interlayer dielectric layer arranged in a direction away from the substrate; wherein the content of hydrogen atoms in the first interlayer dielectric layer is less than that in the second interlayer dielectric layer; and the density of the first interlayer dielectric layer is less than that of the second interlayer dielectric layer.

18. The method for preparing an array substrate according to claim 17, characterized in that: Also includes: forming a first via hole on the interlayer dielectric layer; The first via comprises: a first hole penetrating the first interlayer dielectric layer and a second hole penetrating the second interlayer dielectric layer; wherein the boundary of the first hole enclosed by the first interlayer dielectric layer is located inside the boundary of the second hole enclosed by the second interlayer dielectric layer.

19. The method for preparing an array substrate according to any one of claims 16 to 18, characterized in that: Before forming the active layer on one side of the substrate, the method further includes: forming a light shielding layer on one side of the substrate, and forming a buffer layer on a side of the light shielding layer away from the substrate; Before forming the gate layer on the side of the active layer away from the substrate, the method further comprises: forming a gate insulating layer on the side of the active layer away from the substrate; Wherein, an average thickness of a portion of the buffer layer located between the light shielding layer and the active layer is greater than an average thickness of the gate insulating layer.

20. A display panel, characterized in that: include: The array substrate according to claim 14 or 15; An opposing substrate, opposite to the array substrate and spaced apart from the array substrate; The liquid crystal layer is arranged between the array substrate and the counter substrate.

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