Power device

Abstract

The invention discloses a power device which comprises a frame, a power tube chip, a surge protection device and a diode chip, the power tube chip, the surge protection device and the diode chip are packaged in the frame, and the surge protection device and the diode chip are connected between the first end of the power tube chip and the second end of the power tube chip in series. According to the power device, the surge protection device and the diode are connected in series between the first end and the second end of the power tube, and when surge voltage is applied to the device, the surge protection device can absorb energy and protect the power tube. Meanwhile, the diode can prevent the normal performance of the power tube from being influenced by the repeated discharge of the parasitic capacitance of the surge protection device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a power device. Background Art

[0002] With the development of power devices towards high frequency and miniaturization, the size of power device chips is getting smaller and smaller. However, smaller chip sizes often lead to a reduction in the application surge capability. As the chip size decreases, its heat dissipation area also decreases accordingly. If the heat generated during the avalanche process cannot be dissipated in time, the chip temperature will rise. Since the avalanche energy has a direct relationship with the initial temperature of the chip, the higher the temperature, the smaller the avalanche energy (EAS).

[0003] At the same time, in miniaturized semiconductor power devices, parasitic effects become more significant. For example, parasitic resistance, parasitic capacitance, and parasitic inductance, etc. will all affect the performance of the device. During the avalanche process, these parasitic effects may cause additional power consumption and heat generation, thereby further reducing the avalanche energy.

[0004] As the chip size decreases, its physical structure becomes more compact. This may lead to a more uneven electric field distribution during the avalanche process, with too high a local electric field intensity, thus making it easier to trigger avalanche breakdown. At the same time, the carrier concentration and mobility in small-sized chips may also be affected, resulting in an increase in the avalanche current and a decrease in the avalanche energy.

[0005] These problems will all lead to a risk of application lightning surge failure when miniaturized power devices replace the original VDMOS (Vertical Double Diffused Metal Oxide Semiconductor device).

[0006] The information disclosed in this background art section is only intended to increase the understanding of the overall background of the present invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art already known to those of ordinary skill in the art. Summary of the Invention

[0007] The purpose of the present invention is to provide a power device with good surge resistance.

[0008] To achieve the above purpose, the technical solution provided by a specific embodiment of the present invention is as follows:

[0009] A power device includes a frame and a power transistor chip, a surge protection device, and a diode chip encapsulated in the frame. The surge protection device and the diode chip are connected in series between the first end and the second end of the power transistor chip.

[0010] In one or more embodiments of the present invention, the first end and the control end of the power transistor chip are located on the front side of the power transistor chip, the second end of the power transistor chip is located on the back side of the power transistor chip, the back side of the power transistor chip abuts against the frame, and the second end of the power transistor chip is fixed to the frame through a conductive material.

[0011] In one or more embodiments of the present invention, the first end of the surge protection device is located on the front side of the surge protection device, the second end of the surge protection device is located on the back side of the surge protection device, the back side of the surge protection device abuts against the frame, and the second end of the surge protection device is fixed to the frame through a conductive material.

[0012] In one or more embodiments of the present invention, the cathode of the diode chip is located on the back side of the diode chip, the anode of the diode chip is located on the front side of the diode chip, the back side of the diode chip abuts against the front side of the power transistor chip, the cathode of the diode chip is fixed to the first end of the power transistor chip through a conductive material, and the anode of the diode chip is connected to the first end of the surge protection device through a lead; or the anode of the diode chip is located on the back side of the diode chip, the cathode of the diode chip is located on the front side of the diode chip, the back side of the diode chip abuts against the front side of the surge protection device, the anode of the diode chip is fixed to the first end of the surge protection device through a conductive material, and the cathode of the diode chip is connected to the first end of the power transistor chip through a lead.

[0013] In one or more embodiments of the present invention, the cathode of the diode chip is located on the front side of the diode chip, the anode of the diode chip is located on the back side of the diode chip, the back side of the diode chip abuts against the frame, and the anode of the diode chip is fixed to the frame through a conductive material.

[0014] In one or more embodiments of the present invention, the first end of the surge protection device is located on the front side of the surge protection device, the second end of the surge protection device is located on the back side of the surge protection device, the back side of the surge protection device abuts against the front side of the power transistor chip, the second end of the surge protection device is fixed to the first end of the power transistor chip through a conductive material, and the first end of the surge protection device is connected to the cathode of the diode chip through a lead; or the second end of the surge protection device is located on the front side of the surge protection device, the first end of the surge protection device is located on the back side of the surge protection device, the back side of the surge protection device abuts against the front side of the diode chip, the first end of the surge protection device is fixed to the cathode of the diode chip through a conductive material, and the second end of the surge protection device is connected to the first end of the power transistor chip through a lead.

[0015] In one or more embodiments of the present invention, the power device further includes a first pin insulated from the frame, and the control end of the power transistor chip is connected to the first pin through a lead.

[0016] In one or more embodiments of the present invention, the power device further includes a second pin insulated from the frame, and the first end of the power transistor chip is connected to the second pin through a lead.

[0017] In one or more embodiments of the present invention, the power transistor chip includes one or more of an IGBT chip, a MOSFET chip, a SiC MOS chip, or a GaNFET chip.

[0018] In one or more embodiments of the present invention, the surge protection device includes a TVS diode and / or a varistor.

[0019] Compared with the prior art, the power device of the present invention connects a surge protection device and a diode in series between the first end and the second end of the power transistor. When a surge voltage hits the device, the surge protection device can absorb energy to protect the power transistor. At the same time, the diode can prevent the normal performance of the power transistor from being affected due to the repeated discharge of the parasitic capacitance of the surge protection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a schematic structural diagram of the power device in Embodiment 1 of the present invention.

[0022] Figure 2 It is a schematic circuit diagram of the power device in Embodiment 1 of the present invention.

[0023] Figure 3 It is a schematic circuit diagram of the power device in Embodiment 2 of the present invention.

[0024] Figure 4 It is a schematic structural diagram of the power device in Embodiment 3 of the present invention.

[0025] Figure 5 It is a schematic circuit diagram of the power device in Embodiment 3 of the present invention.

[0026] Figure 6 It is a schematic circuit diagram of the power device in Embodiment 4 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] To enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] "Coupled", "connected", or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches, follower circuits, etc. Additionally, in the invention, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0029] In the detailed description of the specification, reference is made to the accompanying drawings that form a part thereof, in which the same reference numerals always represent the same components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. Therefore, the following detailed description should not be construed as having a limiting meaning.

[0030] The various operations in the specification can be described as a plurality of discrete actions or operations in the order that is most helpful for understanding the claimed subject matter. However, the described order should not be construed as implying that these operations must be order-related. Specifically, these operations can be performed in an order different from the presented order. The described operations can be performed in an order different from the described embodiments. Various additional operations can be performed in additional embodiments and / or the described operations can be omitted.

[0031] For the purposes of the present application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present application, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0032] Various components and devices can be mentioned or shown in the singular form herein (e.g., "MOS transistor", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element mentioned in the singular form can include a plurality of such elements according to the teachings herein.

[0033] The specification describes the use of the phrases "in one embodiment", "in other embodiments", or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present application are synonymous.

[0034] Embodiment 1

[0035] As Figure 1 shown, a power device in one embodiment of the present invention includes a frame 10, a power transistor chip Q1 encapsulated in the frame 10, a surge protection device U1 and a diode chip D1, and a first pin 20 and a second pin 30 that are insulated from the frame 10. The surge protection device U1 and the diode chip D1 are connected in series between the first end and the second end of the power transistor chip Q1.

[0036] In one embodiment, the frame 10 is a flat metal frame 10, and the power transistor chip Q1, the surge protection device U1, and the diode chip D1 are all disposed on the upper surface of the frame 10.

[0037] As Figure 1 shown, the first end and the control end of the power transistor chip Q1 are located on the front surface (i.e., the upper surface) of the power transistor chip Q1. The second end of the power transistor chip Q1 is located on the back surface (i.e., the lower surface, not shown in the figure) of the power transistor chip Q1. The back surface of the power transistor chip Q1 abuts against the upper surface of the frame 10, and the second end of the power transistor chip Q1 is fixed to the frame 10 through a conductive material.

[0038] It should be noted that the front surface, back surface, upper surface, and lower surface of each chip and device mentioned in this specification only refer to the positional relationship, and do not represent the specifically designated "front surface" and "back surface" in the actual preparation and application of the chip or device. For example, the back surface of the above-mentioned power transistor chip Q1 only represents one surface of the power transistor chip Q1, and this surface is opposite to the other surface (i.e., its front surface) of the power transistor chip Q1, without specifically meaning that this surface is the mounting surface, connection surface, or the surface prepared by the semiconductor backside process of the power transistor chip Q1.

[0039] As Figure 1 shown, the first end of the surge protection device U1 is located on the front surface (i.e., the upper surface) of the surge protection device U1. The second end of the surge protection device U1 is located on the back surface (i.e., the lower surface, not shown in the figure) of the surge protection device U1. The back surface of the surge protection device U1 abuts against the frame 10, and the second end of the surge protection device U1 is fixed to the frame 10 through a conductive material.

[0040] In one embodiment, the surge protection device U1 is a TVS diode. The first end of the surge protection device U1 is the anode, and the second end of the surge protection device U1 is the cathode.

[0041] In other embodiments, multiple surge protection devices U1 can also be arranged in parallel. The surge protection device U1 can also include a varistor or include a varistor and a TVS diode.

[0042] As Figure 1 shown, the anode of the diode chip D1 is located on the front surface (i.e., the upper surface) of the diode chip D1, and the cathode of the diode chip D1 is located on the back surface (i.e., the lower surface, not shown in the figure) of the diode chip D1. The back surface of the diode chip D1 abuts against the front surface of the power transistor chip Q1. The cathode of the diode chip D1 and the first end of the power transistor chip Q1 are fixed by a conductive material. The anode of the diode chip D1 is connected to the first end of the surge protection device U1 through a lead.

[0043] In one embodiment, the conductive material can be conductive adhesive, conductive solder or other materials. The above-mentioned chips, devices or frames can be fixed by conductive adhesive bonding, conductive solder welding or other fixing methods.

[0044] As Figure 1 shown, the control end of the power transistor chip Q1 is connected to the first pin 20 through a lead. The first end of the power transistor chip Q1 is connected to the second pin 30 through a lead.

[0045] In one embodiment, two PADs of the first end can be provided on the power transistor chip Q1, which are respectively used to connect the cathode of the diode chip D1 and the second pin 30. In other embodiments, one larger PAD of the first end can also be provided on the power transistor chip Q1. The diode chip D1 partially covers this PAD, leaving a part of the area for bonding the lead to be connected to the second pin 30.

[0046] During actual packaging, the chips and the frame 10, the first pin 20 and the second pin 30 can be packaged by a plastic housing or other packaging housings. Among them, the frame 10, the first pin 20 and the second pin 30 are partially exposed outside the housing to form three contacts of the power device.

[0047] In other embodiments, the first pin 20 and / or the second pin 30 can also be not provided. The first end and / or the control end of the power transistor chip Q1 can also be led out through a substrate.

[0048] In one embodiment, the power transistor chip Q1 is an N-channel MOSFET chip. The second end of the power transistor chip Q1 is the source, the first end of the power transistor chip Q1 is the drain, and the control end of the power transistor chip Q1 is the gate.

[0049] In other embodiments, the power transistor chip Q1 may also include one or more of an IGBT chip, a MOSFET chip, a SiC MOS chip, or a GaNFET chip. The power transistor chip Q1 may also be a P-type semiconductor device, and the connection and positional relationship between the first end and the second end of the power transistor chip Q1 and the diode chip D1, the surge protection device U1, and the first pin 20 and the second pin 30 are adjusted adaptively.

[0050] As Figure 1 shown, by placing the power transistor chip Q1 on the frame 10 and making the second end of the power transistor chip Q1 in electrical contact with the frame 10, the entire frame 10 forms a contact point of the power device. Compared with using pins as the device contact points in conventional power devices, the frame 10 has a larger area, which is beneficial to improving the heat dissipation capacity of the power device. By stacking the diode chip D1 on the power transistor chip Q1 or the surge protection device U1, the area of the power device can be further reduced, the number of leads is reduced at the same time, and the packaging volume is reduced while the packaging strength can be improved.

[0051] As Figure 2 shown, in the power device of this embodiment, the second end of the power transistor chip Q1 is connected to the second end of the surge protection device U1 to form the drain of the entire power device. The first end of the surge protection device U1 is connected to the anode of the diode chip D1, and the cathode of the diode chip D1 is connected to the first end of the power transistor chip Q1 to form the source of the entire power device. The control end of the power transistor chip Q1 forms the gate of the entire power device.

[0052] When a surge voltage hits the device, the surge protection device U1 can absorb energy and protect the power transistor chip Q1. At the same time, the diode chip D1 can prevent the normal performance of the power transistor from being affected due to the repeated discharge of the parasitic capacitance of the surge protection device U1.

[0053] Embodiment 2

[0054] As Figure 3 shown, the difference between the power device of this embodiment and the power device of Embodiment 1 lies only in the specific setting of the diode chip D1. The positional, installation, and connection relationships between the power transistor chip Q1, the surge protection device U1, the frame 10, and the first pin 20 and the second pin 30 in this embodiment are the same as those in Embodiment 1, and their realized functional effects are also the same, which will not be described in detail below.

[0055] Specifically, in this embodiment, the anode of the diode chip D1 is located on the back surface of the diode chip D1, and the cathode of the diode chip D1 is located on the front surface of the diode chip D1. The back surface of the diode chip D1 abuts against the front surface of the surge protection device U1. The anode of the diode chip D1 and the first end of the surge protection device U1 are fixed by a conductive material, and the cathode of the diode chip D1 is connected to the first end of the power transistor chip Q1 through a lead.

[0056] By stacking the diode chip D1 on the front surface of the surge protection device U1, the area of the power device can be further reduced, the number of leads can be reduced, and the package volume can be reduced while the package strength can be improved.

[0057] It can be seen that the circuit connection relationship among the power transistor chip Q1, the surge protection device U1, and the diode in this embodiment is the same as that in Embodiment 1. The power device in this embodiment can also achieve the same surge protection function as the power device in Embodiment 1, and will not be elaborated here.

[0058] Embodiment 3

[0059] As Figure 4 shown, the difference between the power device in this embodiment and the power device in Embodiment 1 lies in the exchange of the positions and connection relationships of the diode chip D1 and the surge protection device U1. The positions, installation, and connection relationships among the power transistor chip Q1, the frame 10, the first pin 20, and the second pin 30 in this embodiment are the same as those in Embodiment 1, and their achieved functional effects are also the same, and will not be described in detail below.

[0060] Specifically, in this embodiment, the cathode of the diode chip D1 is located on the front surface of the diode chip D1, and the anode of the diode chip D1 is located on the back surface of the diode chip D1. The back surface of the diode chip D1 abuts against the frame 10, and the anode of the diode chip D1 is fixed to the frame 10 by a conductive material.

[0061] The first end of the surge protection device U1 is located on the front surface of the surge protection device U1, and the second end of the surge protection device U1 is located on the back surface of the surge protection device U1. The back surface of the surge protection device U1 abuts against the front surface of the power transistor chip Q1. The second end of the surge protection device U1 and the first end of the power transistor chip Q1 are fixed by a conductive material, and the first end of the surge protection device U1 is connected to the cathode of the diode chip D1 through a lead.

[0062] In one embodiment, the surge protection device U1 is a TVS diode, the first end of the surge protection device U1 is the cathode, and the second end of the surge protection device U1 is the anode.

[0063] In other embodiments, multiple surge protection devices U1 may also be provided in parallel. The surge protection device U1 may also include a varistor or include a varistor and a TVS diode.

[0064] As Figure 5 shown, in the power device of this embodiment, the second end of the power transistor chip Q1 is connected to the anode of the diode chip D1 to form the drain of the entire power device. The cathode of the diode chip D1 is connected to the first end of the surge protection device U1, and the second end of the surge protection device U1 is connected to the first end of the power transistor chip Q1 to form the source of the entire power device. The control end of the power transistor chip Q1 forms the gate of the entire power device.

[0065] When a surge voltage hits the device, the surge protection device U1 can absorb energy to protect the power transistor chip Q1. At the same time, the diode chip D1 can prevent the normal performance of the power transistor from being affected due to the repeated discharge of the parasitic capacitance of the surge protection device U1.

[0066] Embodiment 4

[0067] As Figure 6 shown, the difference between the power device of this embodiment and the power device of Embodiment 3 lies only in the specific setting of the surge protection device U1. The positions, installations, and connection relationships between the power transistor chip Q1, the diode chip D1, the frame 10, the first pin 20, and the second pin 30 in this embodiment are the same as those in Embodiment 3, and their achieved functional effects are also the same, so they will not be described in detail below.

[0068] Specifically, in this embodiment, the second end of the surge protection device U1 is located on the front side of the surge protection device U1, the first end of the surge protection device U1 is located on the back side of the surge protection device U1. The back side of the surge protection device U1 abuts against the front side of the diode chip D1. The first end of the surge protection device U1 is fixed to the cathode of the diode chip D1 through a conductive material, and the second end of the surge protection device U1 is connected to the first end of the power transistor chip Q1 through a lead.

[0069] In one embodiment, the surge protection device U1 is a TVS diode. The first end of the surge protection device U1 is the cathode, and the second end of the surge protection device U1 is the anode.

[0070] In other embodiments, multiple surge protection devices U1 may also be provided in parallel. The surge protection device U1 may also include a varistor or include a varistor and a TVS diode.

[0071] By stacking the surge protection device U1 on the front side of the diode chip D1, the area of the power device can be further reduced, the number of leads can be reduced, the package volume can be reduced, and the package strength can be improved at the same time.

[0072] It will be apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, in all respects, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present invention is defined by the appended claims rather than the above description. Accordingly, all changes that fall within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims concerned.

[0073] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment contains only one independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in the various embodiments can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A power device, characterized in that: The invention comprises a frame and a power tube chip, a surge protection device and a diode chip which are packaged in the frame. The surge protection device and the diode chip are connected in series between a first end of the power tube chip and a second end of the power tube chip.

2. The power device according to claim 1, characterized in that: The first end of the power tube chip and the control end of the power tube chip are located on the front side of the power tube chip, the second end of the power tube chip is located on the back side of the power tube chip, the back side of the power tube chip is abutted against the frame, and the second end of the power tube chip is fixed to the frame by a conductive material.

3. The power device according to claim 2, characterized in that: The first end of the surge protection device is located on the front side of the surge protection device, the second end of the surge protection device is located on the back side of the surge protection device, the back side of the surge protection device abuts against the frame, and the second end of the surge protection device is fixed to the frame through a conductive material.

4. The power device according to claim 3, characterized in that: The anode of the diode chip is located on the front side of the diode chip, the cathode of the diode chip is located on the back side of the diode chip, the back side of the diode chip abuts against the front side of the power tube chip, the cathode of the diode chip is fixed to the first end of the power tube chip by a conductive material, and the anode of the diode chip is connected to the first end of the surge protection device by a lead; or The anode of the diode chip is located on the back of the diode chip, the cathode of the diode chip is located on the front of the diode chip, the back of the diode chip is in contact with the front of the surge protection device, the anode of the diode chip is fixed to the first end of the surge protection device by a conductive material, and the cathode of the diode chip is connected to the first end of the power tube chip by a lead.

5. The power device according to claim 2, characterized in that: The cathode of the diode chip is located on the front side of the diode chip, the anode of the diode chip is located on the back side of the diode chip, the back side of the diode chip abuts against the frame, and the anode of the diode chip is fixed to the frame via a conductive material.

6. The power device according to claim 5, characterized in that: The first end of the surge protection device is located on the front side of the surge protection device, the second end of the surge protection device is located on the back side of the surge protection device, the back side of the surge protection device abuts against the front side of the power tube chip, the second end of the surge protection device is fixed to the first end of the power tube chip by a conductive material, and the first end of the surge protection device is connected to the cathode of the diode chip by a lead; or The second end of the surge protection device is located on the front side of the surge protection device, the first end of the surge protection device is located on the back side of the surge protection device, the back side of the surge protection device abuts against the front side of the diode chip, the first end of the surge protection device is fixed to the cathode of the diode chip by a conductive material, and the second end of the surge protection device is connected to the first end of the power tube chip by a lead.

7. The power device according to claim 2, characterized in that: The power device further comprises a first pin which is insulated from the frame, and the control end of the power tube chip is connected to the first pin via a lead.

8. The power device according to claim 2, characterized in that: The power device further comprises a second pin which is insulated from the frame, and the first end of the power tube chip is connected to the second pin via a lead.

9. The power device according to claim 1, characterized in that: The power tube chip includes one or more of an IGBT chip, a MOSFET chip, a SiC MOS chip or a GaNFET chip.

10. The power device according to claim 1, characterized in that: The surge protection device includes a TVS diode and / or a varistor.

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