Preparation method of stacked transistor, stacked transistor, device and electronic equipment

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor, a device and electronic equipment. The method comprises the following steps: forming an active structure on a substrate; forming a first gate structure, a first source-drain metal and a first associated electronic gate dielectric layer of the first transistor; reversing the wafer and thinning the substrate; forming a second gate structure, a second source-drain metal and a second associated electronic gate dielectric layer of a second transistor; forming a second gate through hole which penetrates through the second associated electronic gate dielectric layer and is connected with the first gate structure; forming a second back-end interconnection layer of a second transistor; the second gate through hole is connected with a first layer of metal interconnection line in the second back-end interconnection layer; the wafer where the second transistor is located is inverted; forming a first gate through hole which penetrates through the first associated electronic gate dielectric layer and is connected with the second gate structure; forming a first back-end interconnection layer of the first transistor; and the first gate through hole is connected with a first layer of metal interconnection line in the first back-end interconnection layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular, to a method for manufacturing a stacked transistor, a stacked transistor, a device, and an electronic device. Background Art

[0002] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size has become a hot issue in the current industry research and development. By integrating two or more layers of transistors in the vertical space, stacked transistors can further improve the transistor integration density, and thus become one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some solutions for manufacturing a stacked transistor, the active regions of upper and lower layers of homologous transistors are formed by etching, and the stacked transistor is fabricated on the front and back sides of the wafer through flipping the wafer. This can also be called the "self-aligned flip transistor" solution. However, in the process of forming a decoupling capacitor based on the "self-aligned flip transistor", the internal wiring of the transistor is complex and the manufacturing difficulty is extremely high, which is not conducive to the miniaturization of integrated circuits. Summary of the Invention

[0004] The present application provides a method for manufacturing a stacked transistor, a stacked transistor, a device, and an electronic device, which can simplify the implementation manner of the decoupling capacitor.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked transistor. The method includes: forming an active structure on a substrate; the active structure includes a first active structure and a second active structure stacked in a first direction; forming a first source / drain epitaxy, a first gate structure, a first source / drain metal, and a first associated electron gate dielectric layer of a first transistor based on the first active structure; the first gate structure and the first associated electron gate dielectric layer are jointly located in a first gate region of the first transistor; flipping the wafer and thinning the substrate; forming a second source / drain epitaxy, a second gate structure, a second source / drain metal, and a second associated electron gate dielectric layer of a second transistor based on the second active structure; the second gate structure and the second associated electron gate dielectric layer are jointly located in a second gate region of the second transistor; the first transistor and the second transistor are stacked in the first direction; forming a second gate via penetrating the second associated electron gate dielectric layer; the second gate via extends to a first surface of the first gate structure and contacts the first gate structure; the first surface is a surface of the first gate structure close to the second gate structure; through post-process treatment, forming a second post-interconnection layer of the second transistor; connecting the second gate via to a first-layer metal interconnection line in the second post-interconnection layer; flipping the wafer where the second transistor is located;

[0006] Form a first gate via hole penetrating the first associated electron gate dielectric layer; the first gate via hole extends to the second surface of the second gate structure and contacts the second gate structure; the second surface is the surface of the second gate structure close to the first gate structure; through back-end process treatment, form a first back-end interconnect layer of the first transistor; the first gate via hole is connected to the first metal interconnect line in the first back-end interconnect layer.

[0007] In some possible implementation manners, forming the first source-drain epitaxy, the first gate structure, the first source-drain metal, and the first associated electron gate dielectric layer of the first transistor based on the first active structure includes: performing source-drain epitaxial growth in the first source-drain region of the first transistor to form the first source-drain epitaxy; depositing a metal material in the first gate region to form the first gate structure; etching a first portion of the first gate structure to form a first groove; the first portion is the portion of the first gate structure on one side of the first active structure; filling the first groove with a first dielectric material to form the first associated electron gate dielectric layer; depositing a metal material on the first source-drain epitaxy to form the first source-drain metal.

[0008] In some possible implementation manners, forming the second source-drain epitaxy, the second gate structure, the second source-drain metal, and the second associated electron gate dielectric layer of the second transistor based on the second active structure includes: performing source-drain epitaxial growth in the second source-drain region of the second transistor to form the second source-drain epitaxy; depositing a metal material in the second gate region to form the second gate structure; etching a second portion of the second gate structure to form a second groove; the second portion is the portion of the second gate structure on one side of the second active structure; filling the second groove with a first dielectric material to form the second associated electron gate dielectric layer; depositing a metal material on the second source-drain epitaxy to form the second source-drain metal.

[0009] In some possible implementation manners, forming a second gate via hole penetrating the second associated electron gate dielectric layer includes: depositing a second dielectric material on the second gate structure and the second source-drain metal to form a second back-end dielectric layer; performing photolithography on the second back-end dielectric layer and the second associated electron gate dielectric layer, and stopping the photolithography at the first gate structure to form a second gate via hole groove; the second gate via hole groove penetrates the second back-end dielectric layer and the second associated electron gate dielectric layer; depositing a metal material in the second gate via hole groove to form the second gate via hole.

[0010] In some possible embodiments, forming a first gate via hole penetrating a first associated electron gate dielectric layer includes: depositing a first dielectric material on a first gate structure and a first source / drain metal to form a first back-end dielectric layer; performing photolithography on the first back-end dielectric layer and the first associated electron gate dielectric layer, with the photolithography stopping at the first gate structure to form a first gate via hole groove; the first gate via hole groove penetrating the first back-end dielectric layer and the first associated electron gate dielectric layer, and depositing a metal material in the first gate via hole groove to form a first gate via hole.

[0011] In some possible embodiments, a first power rail is provided in a first back-end interconnect layer; the first power rail is electrically connected to the first source / drain metal; a second power rail is provided in a second back-end interconnect layer; the second power rail is electrically connected to the second source / drain metal.

[0012] In some possible embodiments, a first metal interconnect line in the first back-end interconnect layer is electrically connected to the first source / drain metal; a first metal interconnect line in the second back-end interconnect layer is electrically connected to the second source / drain metal.

[0013] In some possible embodiments, the stacked transistor further includes a third transistor and a fourth transistor; the third transistor and the fourth transistor are stacked in a first direction; the above method further includes: synchronously preparing the third transistor during the process of forming the first transistor; the first transistor is arranged side by side with the third transistor in a second direction; the second direction is perpendicular to the first direction; synchronously preparing the fourth transistor during the process of forming the second transistor; the second transistor is arranged side by side with the fourth transistor in the second direction.

[0014] In a second aspect, an embodiment of the present application provides a stacked transistor prepared by the method as in the first aspect. The stacked transistor includes: a first transistor; a second transistor; the first transistor and the second transistor are stacked in a first direction; a first gate via hole; the first gate via hole penetrates a first gate region of the first transistor and is connected to a second gate structure of the second transistor; the first gate via hole is connected to a first metal interconnect line in a first back-end interconnect layer of the first transistor; a second gate via hole; the second gate via hole penetrates a second gate region of the second transistor and is connected to a first gate structure of the first transistor; the second gate via hole is connected to a first metal interconnect line in a second back-end interconnect layer of the second transistor.

[0015] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: the stacked transistor as in the above embodiment.

[0016] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and the semiconductor device as in the above embodiment, and the semiconductor device is disposed on the circuit board.

[0017] In this application, by forming the first gate via hole and the second gate via hole with a large aspect ratio, the implementation manner of the decoupling capacitor can be simplified.

[0018] Furthermore, the first gate structure and the second gate structure are vertically aligned and distributed, which can cancel the influence of the parasitic capacitance on the stacked transistors; and simplify the internal interconnection manner of the stacked transistors.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application. Brief Description of the Drawings

[0020] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0021] Figure 1 The first circuit diagram of the stacked transistors in the embodiments of this application;

[0022] Figure 2 The first design layout of the stacked transistors in the embodiments of this application;

[0023] Figure 3 The schematic structural diagram of the stacked transistors in the embodiments of this application;

[0024] Figure 4 A schematic flow chart of an implementation of the manufacturing method of the stacked transistors in the embodiments of this application;

[0025] Figures 5A to 5F A schematic diagram of the manufacturing process of the stacked transistors in the embodiments of this application;

[0026] Figure 6 The second schematic diagram of the circuit diagram and the design layout of the stacked transistors in the embodiments of this application;

[0027] Figure 7 The third schematic diagram of the circuit diagram and the design layout of the stacked transistors in the embodiments of this application;

[0028] Figure 8 The fourth schematic diagram of the circuit diagram and the design layout of the stacked transistors in the embodiments of this application;

[0029] Figure 9 The fifth schematic diagram of the circuit diagram and the design layout of the stacked transistors in the embodiments of this application;

[0030] Figure 10 The sixth schematic diagram of the circuit diagram and the design layout of the stacked transistors in the embodiments of this application;

[0031] Figure 11This is the seventh schematic diagram of the circuit diagram and design layout of the stacked transistor in the embodiment of the present application;

[0032] Figure 12 This is the eighth schematic diagram of the circuit diagram and design layout of the stacked transistor in the embodiment of the present application;

[0033] Figure 13 This is the ninth schematic diagram of the circuit diagram and design layout of the stacked transistor in the embodiment of the present application;

[0034] In the above figures:

[0035] 10. Stacked transistor; 11. First transistor; 111. First source / drain epitaxy; 112. First interlayer dielectric layer; 113. First gate dielectric layer; 114. First gate structure; 115. First associated electron gate dielectric layer; 116. First source / drain metal; 117. First back-end dielectric layer; 118. First gate via; 119. First back-end interconnect layer; 12. Second transistor; 121. Second source / drain epitaxy; 122. Second interlayer dielectric layer; 123. Second gate dielectric layer; 124. Second gate structure; 125. Second associated electron gate dielectric layer; 126. Second source / drain metal; 127. Second back-end dielectric layer; 128. Second gate via; 129. Second back-end interconnect layer; 13. First insulating layer; 14. First carrier wafer; 15. Second insulating layer; 16. Second carrier wafer; 21. Substrate; 22. Active structure; 221. First active structure; 222. Second active structure; 23. Shallow trench isolation structure; 231. Shallow trench isolation layer; 241. First dummy gate structure; 242. Second dummy gate structure; 251. First electrical isolation structure; 252. Second electrical isolation structure; 31. First source / drain metal via; 32. Second source / drain metal via. Detailed implementation manners

[0036] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application.

[0037] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. Through three-dimensional transistor stacking, stacked transistors can achieve the integration of two or more layers of transistors in the vertical space, which helps to further improve the transistor integration density and circuit performance, and is considered one of the important technologies to continue the miniaturization of integrated circuit size.

[0038] In one embodiment, there are two schemes for the manufacturing process of stacked transistors. The first is the monolithic scheme, and the second is the sequential scheme.

[0039] For the first scheme, N field effect transistors (NFETs) and P field effect transistors (PFETs) are fabricated on the same substrate without using wafer bonding technology. This determines that the transistors in the same layer must be of the same type, i.e., NFETs or PFETs. Moreover, the upper and lower layer transistors must be strictly in the same planar space with no alignment deviation. The advantage of this scheme is better integration density. The disadvantages of this scheme include the following two points: (1) The process is complex and requires a large amount of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and a basic complementary metal-oxide-semiconductor (CMOS) circuit must rely on two layers of transistors, resulting in poor design flexibility.

[0040] For the second scheme, it is based on wafer bonding and processed layer by layer. Specifically, the upper layer transistors are fabricated by bonding a wafer on top of the previously fabricated lower layer transistors, stacking two transistors vertically. However, during the thermal process of fabricating the upper layer transistors, the temperature needs to be strictly controlled to avoid affecting the lower layer transistors and interconnect lines. The advantage of this scheme is that due to wafer bonding, the device structures, channel crystal orientations, and even channel materials used for the upper and lower layer transistors can be optimized accordingly to obtain better and more matched device performance.

[0041] To solve the technical problems existing in the above two schemes, a "self-aligned flip-chip transistor" scheme is proposed. This "self-aligned flip-chip transistor" scheme forms the active regions of the upper and lower layer homologous transistors through etching, and realizes the fabrication of stacked transistors on the front and back sides of the wafer by flipping the wafer to overcome the disadvantages of the above two schemes.

[0042] In some embodiments, a decoupling capacitor is a capacitor installed at the power supply terminal of a component in a circuit. This capacitor can provide a more stable power supply, and at the same time, it can also reduce the noise coupled from the component to the power supply terminal, indirectly reducing the influence of the noise of this component on other components.

[0043] For the complementary field-effect transistor (CFET) formed by the above-mentioned "self-aligned flip-chip transistor" solution, the power line and the signal line are both arranged on the front side of the transistor, and the gates and source / drains of the upper and lower transistors are aligned, which makes it difficult to route the self-aligned flip-chip transistor, especially the relatively complex metal interconnection. Therefore, it is impossible to simply implement the decoupling capacitor design through the contact vias or the through layer vias (TLVs) between the gates.

[0044] To solve the above technical problems, an embodiment of the present application provides a method for manufacturing a stacked transistor, which can simplify the implementation manner of the decoupling capacitor.

[0045] In some embodiments, the stacked transistor may include a first transistor and a second transistor that are stacked and arranged "back to back". The first transistor includes basic structures such as a first source / drain epitaxy, a first source / drain metal, and a first gate structure; the second transistor includes basic structures such as a second source / drain epitaxy, a second source / drain metal, and a second gate structure.

[0046] In some embodiments, a first associated electron gate dielectric layer filled with a first dielectric material is disposed in the gate region of the first transistor (i.e., the first gate region), and the first associated electron gate dielectric layer and the first gate structure are both located in the first gate region. The first associated electron gate dielectric layer and the first gate structure have the same height in the first direction.

[0047] In some embodiments, a second associated electron gate dielectric layer filled with a first dielectric material is disposed in the gate region of the second transistor (i.e., the second gate region), and the second associated electron gate dielectric layer and the second gate structure are both located in the second gate region. The second associated electron gate dielectric layer and the second gate structure have the same height in the second direction.

[0048] In some embodiments, a first gate via penetrating the first gate region is disposed in the first associated electron gate dielectric layer, and the first gate via extends to the second gate structure of the second transistor and contacts the second gate structure. A second gate via penetrating the second gate region is disposed in the second associated electron gate dielectric layer, and the second gate via extends to the first gate structure of the first transistor and contacts the first gate structure.

[0049] In some embodiments, the VSS (voltage source supply) in the stacked transistors, which is abbreviated as the first power rail in the embodiments of the present application, and the VDD (voltage drain drain) in the stacked transistors, which is abbreviated as the second power rail in the embodiments of the present application. The first power rail is located in the first transistor and is electrically connected to the first source-drain metal. The second power rail is located in the second transistor and is electrically connected to the second source-drain metal.

[0050] In some embodiments, one end of the first gate via is connected to the second gate structure, and the other end is connected to the first metal interconnect line in the first back-end interconnect layer of the first transistor. One end of the second gate via is connected to the first gate structure, and the other end is connected to the first metal interconnect line in the second back-end interconnect layer of the second transistor. Among them, the first metal interconnect line is M0 (metal 0). In this way, the electrical connection between the second gate structure and the first back-end interconnect layer can be realized through the first gate via, and the electrical connection between the first gate structure and the second back-end interconnect layer can be realized through the second gate via.

[0051] In some embodiments, the first metal interconnect line in the first back-end interconnect layer can also be electrically connected to the first source-drain metal, and the first metal interconnect line in the second back-end interconnect layer can also be electrically connected to the second source-drain metal.

[0052] Figure 1 This is the first circuit diagram of the stacked transistors in the embodiments of the present application. Figure 1 In (a) is the circuit diagram of the stacked transistors, Figure 1 In (b) is the combined schematic diagram of the structure and circuit of the stacked transistors. Refer to Figure 1 As shown in (a) therein, VSS and node 2 correspond to the first transistor in the stacked transistors, and VDD and node 1 correspond to the second transistor in the stacked transistors; among them, the first transistor is an N-type field-effect transistor, and the second transistor is a P-type field-effect transistor. Refer to Figure 1 As shown in (b) therein, electrical isolation structures are provided on both sides of the stacked transistors. The electrical isolation structures can be realized by the single diffusion break (SDB) technology. The electrical isolation structures are used to achieve electrical isolation between adjacent units, which can reduce leakage and improve performance.

[0053] It can be understood that the interconnection methods among the first gate via, the second gate via, the first gate structure, the second gate structure, the first source-drain metal, the second source-drain metal, the first back-end interconnect layer, and the second back-end interconnect layer in the embodiments of the present application realize a cross-coupled decoupling capacitor unit (cross coupled ecap cell), so as to achieve high-frequency decoupling and reduce power supply noise.

[0054] Figure 2 This is the first design layout of the stacked transistor in the embodiment of the present application. Among them, Figure 2 (a) in it is the first design layout of the first transistor in the stacked transistor, Figure 2 and (b) in it is the first design layout of the second transistor in the stacked transistor. Figure 3 This is the structural schematic diagram of the stacked transistor in the embodiment of the present application. Figure 3 The design layout of the stacked transistor shown is Figure 2 the design layout shown. Figure 3 (a) in it is the sectional view of the stacked transistor taken along the A-A' direction in the design layout; Figure 3 and (b) in it is the sectional view of the stacked transistor taken along the B-B' direction in the design layout; Figure 3 and (c) in it is the sectional view of the stacked transistor taken along the C-C' direction in the design layout; Figure 3 and (d) in it is the sectional view of the stacked transistor taken along the D-D' direction in the design layout, Figure 3 and (e) in it is the sectional view of the stacked transistor taken along the E-E' direction in the design layout. In some embodiments, the design layout of the first transistor can also be called the front design layout of the stacked transistor, and the design layout of the second transistor can also be called the back design layout of the stacked transistor.

[0055] Refer to Figure 1 、 Figure 2 and Figure 3 As shown, in the sectional view in the D-D' direction, the first source-drain metal is connected to VSS, the second source-drain metal is electrically connected to M0 of the second transistor, and the first gate structure is electrically connected to M0 of the second transistor through the second gate via, corresponding to node 2 in the circuit diagram. In the sectional view in the E-E' direction, the second source-drain metal is connected to VDD, the second gate structure is connected to M0 in the first transistor through the first gate via, and the first source-drain metal is connected to M0 in the first transistor, corresponding to node 1 in the circuit diagram.

[0056] Next, the preparation method of the stacked transistor provided in the embodiment of the present application will be described in conjunction with Figure 2 and Figure 3 as follows.

[0057] Figure 4 This is a schematic flowchart of an implementation process of the preparation method of the stacked transistor in the embodiment of the present application. Refer to Figure 4 As shown, the preparation method of the above-mentioned stacked transistor may include:

[0058] Step S401, forming an active structure on the substrate; the active structure includes a first active structure and a second active structure stacked in the first direction.

[0059] Understandably, at the beginning of fabricating a stacked transistor, a substrate (also referred to as a wafer) is provided first. The active structure is patterned on the substrate, and then through an etching process, the active structure is etched out on the substrate. Since the stacked transistor includes at least two stacked transistors (i.e., the first transistor and the second transistor), and the active structures of the first transistor and the second transistor are formed in the same process, therefore, by controlling the etching depth, it can be ensured that the height of the active structure can fabricate two stacked transistors simultaneously. For example, the height of the etched active structure can be greater than 100 nm. The active structure can be composed of a first active structure and a second active structure. The first active structure is used to fabricate the first transistor, and the second active structure is used to fabricate the second transistor.

[0060] In some embodiments, since the first active structure and the second active structure are formed in the same process, the active regions of the first transistor corresponding to the first active structure and the second transistor corresponding to the second active structure are self-aligned.

[0061] In some embodiments, Figure 3 The stacked transistor shown is composed of two fin field-effect transistors (FinFETs). It should be noted that the fin field-effect transistor is only one example. The stacked transistor described in the embodiments of the present application can also be formed by stacking other types of transistors, such as; gate-all-around field-effect transistors (GAAFETs), planar metal-oxide-semiconductor field-effect transistors, etc.

[0062] Step S402: Form a first source / drain epitaxy, a first gate structure, a first source / drain metal, and a first associated electron gate dielectric layer of the first transistor based on the first active structure; the first gate structure and the first associated electron gate dielectric layer are both located in the first gate region of the first transistor.

[0063] Understandably, each structure in the first transistor, such as the first source / drain epitaxy, the first gate structure, the first source / drain metal, etc., can be formed according to the standard process for fabricating transistors.

[0064] It should be noted that in the embodiments of the present application, the source / drain is an abbreviation for the source electrode and / or the drain electrode. For example, the first source / drain epitaxy can represent the first source electrode epitaxy and / or the first drain electrode epitaxy.

[0065] In some embodiments, the first associated electronic gate dielectric layer is formed after the formation of the first gate structure through processes such as photolithography, etching, and deposition. The first associated electronic gate dielectric layer and the unetched first gate structure are both located in the first gate region.

[0066] In some possible implementation manners, the above step S402 may include: performing source-drain epitaxial growth on the first source-drain region of the first transistor to form a first source-drain epitaxy; depositing a metal material in the first gate region to form a first gate structure; etching a first portion of the first gate structure to form a first groove; the first portion is the portion of the first gate structure located on one side of the first active structure; filling a first dielectric material in the first groove to form a first associated electronic gate dielectric layer; depositing a metal material on the first source-drain epitaxy to form a first source-drain metal.

[0067] In some embodiments, by etching a portion of the first active structure, a first source-drain groove is formed, and source-drain epitaxial growth is performed in the first source-drain groove to form a first source-drain epitaxy.

[0068] In some embodiments, photolithography is used to open the first gate region, and a semiconductor material (such as polysilicon (poly Si)) is deposited in the first gate region to form a first dummy gate structure. Then, the first dummy gate structure is removed to expose the first gate region, and a metal material is deposited in the first gate region to form a first gate structure.

[0069] In some embodiments, through photolithography, a first portion of the first gate structure is removed to form a first groove, and a first dielectric material (such as vanadium oxide (VO 2 )、nickel oxide (NiO), etc.) is filled in the first groove to form a first associated electronic gate dielectric layer.

[0070] Step S403, flip the wafer and thin the substrate.

[0071] It can be understood that the wafer is flipped and the substrate is thinned until the second active structure is exposed, so that the second active structure is placed upward, which is convenient for fabricating the second transistor.

[0072] In some embodiments, the substrate can be thinned by a chemical-mechanical planarization (CMP) process.

[0073] In some possible implementation manners, before the above step S403, the method for fabricating the stacked transistor may further include: depositing an insulating material on the surface of the first transistor away from the second active structure to form a first insulating layer; bonding the first insulating layer to a first carrier wafer.

[0074] In the embodiments of the present application, after the first carrier wafer is bonded and flipped, it can provide physical support for the flipped first transistor, effectively preventing the first transistor from being broken by external forces during the process of fabricating the second transistor.

[0075] Step S404: Form the second source / drain epitaxy, the second gate structure, the second source / drain metal, and the second associated electron gate dielectric layer of the second transistor based on the second active structure; the second gate structure and the second associated electron gate dielectric layer are both located in the second gate region of the second transistor. The first transistor and the second transistor are stacked in the first direction.

[0076] It can be understood that each structure in the second transistor, such as the second source / drain epitaxy, the second gate structure, the second source / drain metal, etc., can be formed according to the standard process for fabricating transistors.

[0077] In some embodiments, the second associated electron gate dielectric layer is formed after the second gate structure is formed through processes such as photolithography, etching, and deposition. The second associated electron gate dielectric layer and the unetched second gate structure are both located in the second gate region.

[0078] In some embodiments, the first gate structure is formed in the first gate region, and the second gate structure is formed in the second gate region. The first gate region and the second gate region are vertically aligned, such that the formed first gate structure and the second gate structure are also vertically aligned. The vertically aligned gate structures can simplify the internal interconnection method of the stacked transistors and cancel out the parasitic capacitance.

[0079] In some possible implementation manners, the above step S404 may include: performing source / drain epitaxial growth in the second source / drain region of the second transistor to form the second source / drain epitaxy; depositing a metal material in the second gate region to form the second gate structure; etching a second portion of the second gate structure to form a second groove; the second portion is the portion of the second gate structure on one side of the second active structure; filling a first dielectric material in the second groove to form the second associated electron gate dielectric layer; depositing a metal material on the second source / drain epitaxy to form the second source / drain metal.

[0080] In some embodiments, a second source / drain groove is formed by etching a portion of the second active structure, and source / drain epitaxial growth is performed in the second source / drain groove to form the second source / drain epitaxy.

[0081] In some embodiments, the second gate region is opened by photolithography, and a semiconductor material (such as polysilicon) is deposited in the second gate region to form a second dummy gate structure. Then, the second dummy gate structure is removed to expose the second gate region, and a metal material is deposited in the second gate region to form the second gate structure.

[0082] In some embodiments, through photolithography, a second part of the second gate structure is removed to form a second groove, and a first dielectric material is filled in the second groove to form a second associated electron gate dielectric layer.

[0083] Step S405: Form a second gate via hole penetrating the second associated electron gate dielectric layer; the second gate via hole extends to the first surface of the first gate structure and contacts the first gate structure; the first surface is the surface of the first gate structure close to the second gate structure.

[0084] It can be understood that the second gate via hole can be formed in the second associated electron gate dielectric layer through processes such as photolithography, etching, and deposition. The second gate via hole contacts the first gate structure and is electrically connected to the first gate structure.

[0085] In some possible implementation manners, the above step S405 may include: depositing a second dielectric material on the second gate structure and the second source / drain metal to form a second BEOL dielectric layer; photolithographing the second BEOL dielectric layer and the second associated electron gate dielectric layer, and stopping photolithography at the first gate structure to form a second gate via hole groove; the second gate via hole groove penetrates the second BEOL dielectric layer and the second associated electron gate dielectric layer, and a metal material is deposited in the second gate via hole groove to form a second gate via hole.

[0086] In some embodiments, a layer of second dielectric material is deposited on the second gate structure, the second source / drain metal, and the second associated electron gate dielectric to form a second BEOL dielectric layer. The second BEOL dielectric layer is used to connect the core structure inside the transistor to the second BEOL interconnect layer. The second BEOL dielectric layer and the second associated electron gate dielectric layer are photolithographed, and etching is stopped at the surface (i.e., the first surface) of the first gate structure to form a second gate via hole groove. A metal material is deposited in the second gate via hole groove to form a second gate via hole. The second gate via hole penetrates the second BEOL dielectric layer and the second associated electron gate dielectric layer.

[0087] Step S406: Through BEOL processing, form a second BEOL interconnect layer of the second transistor; the second gate via hole is connected to the first metal interconnect line in the second BEOL interconnect layer.

[0088] It can be understood that through BEOL (back end of line), a second BEOL interconnect layer can be formed on the second BEOL dielectric layer. The second BEOL interconnect layer may include multiple dielectric layers, and metal interconnect lines can be provided in each dielectric layer according to actual situations. Among them, the first metal interconnect line (i.e., M0) in the second BEOL interconnect layer is connected to the second gate via hole.

[0089] In some embodiments, the second back-end interconnect layer may further include a second metal interconnect line (metal 1, M1) and a second power rail (i.e., VDD).

[0090] Step S407: Invert the wafer where the second transistor is located.

[0091] It can be understood that after the second crystal is formed, the second transistor can be inverted so that the first transistor is placed upward.

[0092] In some embodiments, after inverting the second transistor, the first insulating layer and the first carrier wafer on the surface of the first transistor can be removed.

[0093] In some possible implementation manners, before the above step S407, the method for manufacturing the stacked transistors may further include: depositing an insulating material on the surface of the second transistor away from the first active structure to form a second insulating layer; bonding the second insulating layer to the second carrier wafer.

[0094] In the embodiments of the present application, the bonded second carrier wafer can provide physical support for the inverted second transistor after inverting, effectively preventing the second transistor from being broken by external force during the manufacturing process of the first transistor.

[0095] Step S408: Form a first gate via hole penetrating the first associated electron gate dielectric layer; the first gate via hole extends to the second surface of the second gate structure and contacts the second gate structure; the second surface is the surface of the second gate structure close to the first gate structure.

[0096] It can be understood that the first gate via hole can be formed in the first associated electron gate dielectric layer through processes such as photolithography, etching, and deposition. The first gate via hole contacts the second gate structure and is electrically connected to the second gate structure.

[0097] In some possible implementation manners, the above step S408 may include: depositing a first dielectric material on the first gate structure and the first source-drain metal to form a first back-end dielectric layer; photolithographing the first back-end dielectric layer and the first associated electron gate dielectric layer, and stopping photolithography at the first gate structure to form a first gate via hole groove; the first gate via hole groove penetrates the first back-end dielectric layer and the first associated electron gate dielectric layer, and depositing a metal material in the first gate via hole groove to form a first gate via hole.

[0098] In some embodiments, a layer of second dielectric material is deposited on the first gate structure, the first source / drain metal, and the first associated electron gate dielectric to form a first back-end dielectric layer. The first back-end dielectric layer is used to connect the core structure inside the transistor to the first back-end interconnect layer. The first back-end dielectric layer and the first associated electron gate dielectric layer are lithographed, and the etching is stopped at the surface of the second gate structure (i.e., the second surface) to form a first gate via groove. A metal material is deposited in the first gate via groove to form a first gate via. The first gate via penetrates through the first back-end dielectric layer and the first associated electron gate dielectric layer.

[0099] It should be noted that the first back-end dielectric layer can also be formed before the above step S403, that is, before forming the first insulating layer, a layer of second dielectric material is deposited on the first gate structure, the first source / drain metal, and the first associated electron gate dielectric to form the first back-end dielectric layer.

[0100] Step S409, through back-end processing, form the first back-end interconnect layer of the first transistor; the first gate via is connected to the first metal interconnect line in the first back-end interconnect layer.

[0101] It can be understood that through back-end processing, the first back-end interconnect layer can be formed on the first back-end dielectric layer. The first back-end interconnect layer can include multiple dielectric layers, and according to the actual situation, metal interconnect lines can be arranged in each dielectric layer. Among them, the first metal interconnect line (i.e., M0) in the first back-end interconnect layer is connected to the first gate via.

[0102] In some embodiments, the first back-end interconnect layer may further include a second metal interconnect line (metal 1, M1) and a first power rail (i.e., VSS).

[0103] In some possible implementation manners, a first power rail is provided in the first back-end interconnect layer; the first power rail is electrically connected to the first source / drain metal; a second power rail is provided in the second back-end interconnect layer; the second power rail is electrically connected to the second source / drain metal.

[0104] In some embodiments, in addition to M0, a first power rail (i.e., VSS) can also be provided in the first dielectric layer of the first back-end interconnect layer. The first power rail is electrically connected to the first source / drain metal through a metal via located in the first back-end dielectric layer. In addition to M0, a second power rail (i.e., VDD) can also be provided in the first dielectric layer of the second back-end interconnect layer. The second power rail is electrically connected to the second source / drain metal through a metal via located in the second back-end dielectric layer.

[0105] In some possible implementation manners, the first metal interconnect line in the first back-end interconnect layer is electrically connected to the first source / drain metal; the first metal interconnect line in the second back-end interconnect layer is electrically connected to the second source / drain metal.

[0106] It is understandable that the first source-drain metal is connected to the first-layer metal interconnection line through the source-drain metal via hole, realizing the interconnection between the source-drain and the subsequent process in the first transistor. The second source-drain metal is connected to the first-layer metal interconnection line through the source-drain metal via hole, realizing the interconnection between the source-drain and the subsequent process in the second transistor.

[0107] In some possible embodiments, the stacked transistors may further include a third transistor and a fourth transistor; the third transistor and the fourth transistor are stacked in a first direction; the above method may further include: during the process of forming the first transistor, synchronously preparing the third transistor; the first transistor and the third transistor are arranged side by side in a second direction; the second direction is perpendicular to the first direction; during the process of forming the second transistor, synchronously preparing the fourth transistor; the second transistor and the fourth transistor are arranged side by side in the second direction.

[0108] It is understandable that the stacked transistors may include more than one pair of stacked transistors. In addition to the first transistor and the second transistor, they may further include stacked third transistor and fourth transistor. The third transistor is adjacent to the first transistor, and the fourth transistor is adjacent to the second transistor. The first transistor and the third transistor are prepared synchronously, and the second transistor and the fourth transistor are prepared synchronously. The first transistor and the third transistor are located on the front side and can be called front-side transistors, and the second transistor and the fourth transistor are located on the back side and can be called back-side transistors.

[0109] In some embodiments, in addition to one pair or two pairs of stacked transistors, the stacked transistors can also be designed as four pairs of stacked transistors. It should be noted that in order to form the structure of the cross-coupled decoupling capacitor, the number of mutually stacked transistors in the stacked transistors is a multiple of 2. The embodiments of the present application can be designed according to the actual situation, and no specific limitation is made thereto.

[0110] Next, taking the first transistor and the second transistor as fin field-effect transistors as an example, the stacked transistors provided by the embodiments of the present application will be described.

[0111] Figure 3 The stacked transistor 10 shown can be prepared through Figures 5A to 5F the process shown, Figures 5A to 5F which is a schematic diagram of the preparation process of the stacked transistors in the embodiments of the present application.

[0112] The first step: providing a substrate 21. Etching an active structure 22 on the substrate 21. The active structure 22 includes a first active structure 221 and a second active structure 222 (see Figure 5A (a)).

[0113] Step 2: Deposit an insulating material on the substrate 21 and the active structure 22 to form a shallow trench isolation (STI) structure 23. The shallow trench isolation structure 23 wraps the active structure 22 and covers the substrate 21. Etch back the shallow trench isolation structure 23 to expose the first active structure 221 (see Figure 5A of (b)).

[0114] Step 3: Use photolithography to open the first gate region of the first transistor 11, and deposit polysilicon in the first gate region to form a first dummy gate structure 241 (see Figure 5A of (c)).

[0115] Step 4: Etch the first active structure 221 to form a first source / drain groove, and perform source / drain epitaxial growth in the first source / drain groove to form a first source / drain epitaxy 111. Deposit a dielectric material on the shallow trench isolation structure 23 to form a first interlayer dielectric (ILD) layer 112 (see Figure 5B of (a)).

[0116] Step 5: Remove the first dummy gate structure 241 to expose the first gate region. Deposit an insulating material on the surfaces of the first gate region, the shallow trench isolation structure 23, and the first active structure 221 to form a first gate dielectric layer 113. Deposit a metal material in the first gate region to form a first gate structure 114 (see Figure 5B of (b)).

[0117] Step 6: Through photolithography, remove the first part of the first gate structure 114 to form a first groove. Deposit a first dielectric material in the first groove to form a first associated electron gate dielectric layer 115 (see Figure 5B of (c)).

[0118] Step 7: Etch the first interlayer dielectric layer 112 to form a first source / drain metal groove, and deposit a metal material in the first source / drain metal groove to form a first source / drain metal 116 (see Figure 5C of (a)).

[0119] In one example, during the process of Step 7, a first electrical isolation structure 251 is formed on both sides of the first transistor 11 through processes such as etching and deposition ( Figure 5C not shown in Figure 3 ).

[0120] Step 8: Deposit a second dielectric material on the first source / drain metal 116, the first interlayer dielectric layer 112, the first gate structure 114, and the first associated electron gate dielectric layer 115 to form a first back-end dielectric layer 117 (see Figure 5C(b) of

[0121] Ninth step: Deposit an insulating material on the first post-channel dielectric layer 117 to form a first insulating layer 13, and bond the first insulating layer 13 to the first carrier wafer 14. Then, flip the wafer and thin the substrate 21 so that one end of the second active structure 222 away from the first active structure 221 faces upward (see Figure 5C (c) of

[0122] Tenth step: Etch a part of the shallow trench isolation structure 23 so that the second active structure 222 is exposed, and at the same time retain the shallow trench isolation structure 23 with a preset height. The retained shallow trench isolation structure 23 is the shallow trench isolation layer 231 (see Figure 5D (a) of

[0123] Eleventh step: Form the second dummy gate structure 242 of the second transistor 12 (see Figure 5D (b) of

[0124] Twelfth step: Form the second source / drain epitaxy 121 and the second interlayer dielectric layer 122 (see Figure 5D (c) of

[0125] Thirteenth step: Form the second gate dielectric layer 123 and the second gate structure 124 (see Figure 5E (a) of

[0126] Fourteenth step: Form the second correlated electron gate dielectric layer 125 (see Figure 5E (b) of

[0127] Fifteenth step: Form the second source / drain metal 126 (see Figure 5E (c) of. And form the second electrical isolation structure 252 ( Figure 5E not shown in Figure 3 ), see

[0128] Sixteenth step: Form the second post-channel dielectric layer 127. Lithograph the second post-channel dielectric layer 127 and the second correlated electron gate dielectric layer 125, and stop etching at the first gate structure 114 to form a second gate via groove; deposit a metal material in the second gate via groove to form a second gate via 128. Perform post-channel processes on the second post-channel dielectric layer 127 to form a second post-channel interconnect layer 129. M0 in the second post-channel interconnect layer 129 is electrically connected to the second source / drain metal 126 through the second source / drain metal via 32 in the second post-channel dielectric layer 127, and M0 in the second post-channel interconnect layer 129 is also connected to the second gate via 128. VDD in the second post-channel interconnect layer 129 is electrically connected to the second source / drain metal 126 through a metal via in the second post-channel dielectric layer 127 (see Figure 5F (a) of

[0129] Step 17: Deposit an insulating material on the second BEOL interconnect layer 129 to form the second insulating layer 15, and bond the second insulating layer 15 to the second carrier wafer 16. Then, flip the wafer and remove the first insulating layer 13 and the first carrier wafer 14 so that the first BEOL dielectric layer 117 faces upward (see Figure 5F (b) of

[0130] Step 18: Photolithograph the first BEOL dielectric layer 117 and the first associated electron gate dielectric layer 115, etch until reaching the second gate structure 124 to form the first gate via trench; deposit a metal material in the first gate via trench to form the first gate via 118. Perform BEOL processes on the first BEOL dielectric layer 117 to form the first BEOL interconnect layer 119. M0 in the first BEOL interconnect layer 119 is electrically connected to the first source / drain metal 116 through the first source / drain metal via 31 in the first BEOL dielectric layer 117, and M0 in the first BEOL interconnect layer 119 is also connected to the first gate via 118. VDD in the first BEOL interconnect layer 119 is electrically connected to the first source / drain metal 116 through a metal via in the first BEOL dielectric layer 117 (see Figure 5F (c) of

[0131] So far, the stacked transistor 10 has been fabricated according to the above fabrication method.

[0132] In some embodiments, Figure 6 FIG. is the second schematic diagram of the circuit diagram and design layout of the stacked transistor in the embodiments of the present application. Figure 6 (a) in Figure 6 is the second circuit diagram of the stacked transistor, Figure 6 (b) in Figure 6 is the second design layout of the front transistor in the stacked transistor,

[0133] In some embodiments, Figure 7 FIG. is the third schematic diagram of the circuit diagram and design layout of the stacked transistor in the embodiments of the present application. Figure 7 (a) in Figure 7 is the third circuit diagram of the stacked transistor, Figure 7In (c), it is the third design layout of the back transistor in the stacked transistor. Refer to Figure 7 As shown, the stacked transistor is formed by stacking two transistors on the front and two transistors on the back. In the third design layout of the front transistor, the two source-drain metal vias are respectively located above the source-drain metals of the two front transistors in the E-E' direction. In the third design layout of the back transistor, one source-drain metal via is located above the shared source-drain metal of the two back transistors in the D-D' direction.

[0134] In some embodiments, Figure 8 This is the fourth schematic diagram of the circuit diagram and design layout of the stacked transistor in the embodiments of the present application. Figure 8 In (a), it is the fourth circuit diagram of the stacked transistor, Figure 8 In (b), it is the fourth design layout of the front transistor in the stacked transistor, Figure 8 In (c), it is the fourth design layout of the back transistor in the stacked transistor. Refer to Figure 8 As shown, the stacked transistor is formed by stacking two transistors on the front and two transistors on the back. In the fourth design layout of the front transistor, the two source-drain metal vias are respectively located above the source-drain metals of the two front transistors in the E-E' direction. In the fourth design layout of the back transistor, one source-drain metal via is located above the shared source-drain metal of the two back transistors in the D-D' direction.

[0135] In some embodiments, Figure 8 This is the fourth schematic diagram of the circuit diagram and design layout of the stacked transistor in the embodiments of the present application. Figure 8 In (a), it is the fourth circuit diagram of the stacked transistor, Figure 8 In (b), it is the fourth design layout of the front transistor in the stacked transistor, Figure 8 In (c), it is the fourth design layout of the back transistor in the stacked transistor. Refer to Figure 8 As shown, the stacked transistor is formed by stacking two transistors on the front and two transistors on the back. In the fourth design layout of the front transistor, the two source-drain metal vias are respectively located above the source-drain metals of the two front transistors in the E-E' direction. In the fourth design layout of the back transistor, one source-drain metal via is located above the shared source-drain metal of the two back transistors in the D-D' direction.

[0136] In some embodiments, Figure 9 This is the fifth schematic diagram of the circuit diagram and design layout of the stacked transistor in the embodiments of the present application. Figure 9 In (a), it is the fifth circuit diagram of the stacked transistor, Figure 9 In (b), it is the fifth design layout of the front transistor in the stacked transistor,Figure 9 In (c), it is the fifth layout of the back transistor in the stacked transistor. Refer to Figure 9 As shown, the stacked transistor is formed by stacking two transistors on the front and two transistors on the back. In the fifth layout of the front transistor, a source / drain metal via is located above the source / drain metal shared by the two back transistors in the E-E' direction. In the fifth layout of the back transistor, two source / drain metal vias are respectively located above the source / drain metals of the two front transistors in the D-D' direction.

[0137] In some embodiments, Figure 10 This is the sixth schematic diagram of the circuit diagram and layout of the stacked transistor in the embodiments of the present application. Figure 10 In (a), it is the sixth circuit diagram of the stacked transistor, Figure 10 In (b), it is the sixth layout of the front transistor in the stacked transistor, Figure 10 In (c), it is the sixth layout of the back transistor in the stacked transistor. Refer to Figure 10 As shown, the stacked transistor is formed by stacking four transistors on the front and four transistors on the back. In the sixth layout of the front transistor, two source / drain metal vias are distributed above the source / drain metal in the E-E' direction. In the sixth layout of the back transistor, three source / drain metal vias are distributed above the source / drain metal in the D-D' direction.

[0138] In some embodiments, Figure 11 This is the seventh schematic diagram of the circuit diagram and layout of the stacked transistor in the embodiments of the present application. Figure 11 In (a), it is the seventh circuit diagram of the stacked transistor, Figure 11 In (b), it is the seventh layout of the front transistor in the stacked transistor, Figure 11 In (c), it is the seventh layout of the back transistor in the stacked transistor. Refer to Figure 11 As shown, the stacked transistor is formed by stacking four transistors on the front and four transistors on the back. In the seventh layout of the front transistor, three source / drain metal vias are distributed above the source / drain metal in the E-E' direction. In the seventh layout of the back transistor, two source / drain metal vias are distributed above the source / drain metal in the D-D' direction.

[0139] In some embodiments, Figure 12 This is the eighth schematic diagram of the circuit diagram and layout of the stacked transistor in the embodiments of the present application. Figure 12 In (a), it is the eighth circuit diagram of the stacked transistor, Figure 12 In (b), it is the eighth layout of the front transistor in the stacked transistor, Figure 12Among them, (c) is the eighth design layout of the back transistor in the stacked transistor. Refer to Figure 12 As shown, the stacked transistor is formed by stacking four transistors on the front and four transistors on the back. In the eighth design layout of the front transistor, two source-drain metal vias are distributed above the source-drain metal in the E-E' direction. In the eighth design layout of the back transistor, three source-drain metal vias are distributed above the source-drain metal in the D-D' direction.

[0140] In some embodiments, Figure 13 This is the ninth schematic diagram of the circuit diagram and design layout of the stacked transistor in the embodiments of the present application. Figure 13 Among them, (a) is the ninth circuit diagram of the stacked transistor, Figure 13 Among them, (b) is the ninth design layout of the front transistor in the stacked transistor, Figure 13 Among them, (c) is the ninth design layout of the back transistor in the stacked transistor. Refer to Figure 13 As shown, the stacked transistor is formed by stacking four transistors on the front and four transistors on the back. In the ninth design layout of the front transistor, three source-drain metal vias are distributed above the source-drain metal in the E-E' direction. In the ninth design layout of the back transistor, two source-drain metal vias are distributed above the source-drain metal in the D-D' direction.

[0141] In the embodiments of the present application, by forming the first gate via and the second gate via with a large aspect ratio, the implementation manner of the decoupling capacitor can be simplified.

[0142] Furthermore, the first gate structure and the second gate structure are vertically aligned and distributed, which can offset the influence of the parasitic capacitance on the stacked transistor; and simplify the internal interconnection manner of the stacked transistor.

[0143] Furthermore, the stacked transistors provided in the embodiments of the present application can be detected using detection and analysis instruments, such as: scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the stacked transistors provided in the embodiments of the present application can be detected by means of TEM sectioning. For example, the first gate via is respectively connected to the second gate structure and M0 in the first transistor, the second gate via is respectively connected to the first gate structure and M0 in the second transistor, the first source-drain metal is connected to M0 in the first transistor through the metal via in the first back-end dielectric layer, and the second source-drain metal is connected to M0 in the second transistor through the metal via in the second back-end dielectric layer.

[0144] The embodiments of the present application provide a semiconductor device, including: the stacked transistor as described in the above embodiments. For the specific definition of the stacked transistor, reference can be made to the above Figure 3 shown structure, which will not be elaborated here.

[0145] The embodiments of the present application provide an electronic device, including: a circuit board and the semiconductor device as described in the above embodiments, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above-mentioned stacked transistor. For the specific definition of the stacked transistor, reference can be made to the above Figure 3 , which will not be elaborated here.

[0146] In the description of the present application, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine the different embodiments or examples described in the present application and the features of different embodiments or examples.

[0147] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: An active structure is formed on a substrate; the active structure comprises a first active structure and a second active structure stacked in a first direction; Based on the first active structure, a first source-drain epitaxy, a first gate structure, a first source-drain metal and a first associated electronic gate dielectric layer of a first transistor are formed; the first gate structure and the first associated electronic gate dielectric layer are located together in a first gate region of the first transistor; Flipping and thinning the substrate; Based on the second active structure, a second source-drain epitaxy, a second gate structure, a second source-drain metal and a second associated electronic gate dielectric layer of a second transistor are formed; the second gate structure and the second associated electronic gate dielectric layer are located together in a second gate region of the second transistor; the first transistor and the second transistor are stacked in the first direction; A second gate through hole is formed that penetrates the second associated electron gate dielectric layer; the second gate through hole extends to the first surface of the first gate structure and contacts the first gate structure; the first surface is a surface of the first gate structure that is close to the second gate structure; Through a back-end process, a second back-end interconnection layer of the second transistor is formed; the second gate through hole is connected to the first layer of metal interconnection line in the second back-end interconnection layer; Flipping the wafer where the second transistor is located; A first gate through hole is formed that penetrates the first associated electron gate dielectric layer; the first gate through hole extends to a second surface of the second gate structure and contacts the second gate structure; the second surface is a surface of the second gate structure that is close to the first gate structure; A first back-end interconnection layer of the first transistor is formed through back-end process processing; the first gate through hole is connected to a first layer of metal interconnection lines in the first back-end interconnection layer.

2. The method according to claim 1, characterized in that The method of forming a first source-drain epitaxy, a first gate structure, a first source-drain metal and a first associated electronic gate dielectric layer of a first transistor based on the first active structure includes: Performing source-drain epitaxial growth in the first source-drain region of the first transistor to form the first source-drain epitaxy; Depositing a metal material in the first gate region to form a first gate structure; Etching a first portion of the first gate structure to form a first groove; the first portion is a portion of the first gate structure located on one side of the first active structure; Filling the first groove with a first dielectric material to form the first associated electron gate dielectric layer; A metal material is deposited on the first source / drain epitaxy to form the first source / drain metal.

3. The method according to claim 1, characterized in that Forming a second source-drain epitaxy, a second gate structure, a second source-drain metal, and a second associated electronic gate dielectric layer of a second transistor based on the second active structure includes: Performing source-drain epitaxial growth in the second source-drain region of the second transistor to form the second source-drain epitaxy; Depositing a metal material in the second gate region to form a second gate structure; Etching a second portion of the second gate structure to form a second groove; the second portion is a portion of the second gate structure located on one side of the second active structure; Filling the second groove with a first dielectric material to form the second associated electron gate dielectric layer; A metal material is deposited on the second source / drain epitaxy to form the second source / drain metal.

4. The method according to claim 1, characterized in that: The forming of a second gate through hole penetrating the second associated electron gate dielectric layer comprises: Depositing a second dielectric material on the second gate structure and the second source / drain metal to form a second back-end dielectric layer; The second back-end dielectric layer and the second associated electronic gate dielectric layer are photolithographically processed, and the photolithography stops at the first gate structure to form a second gate through hole groove; the second gate through hole groove penetrates the second back-end dielectric layer and the second associated electronic gate dielectric layer, A metal material is deposited in the second gate through hole groove to form the second gate through hole.

5. The method according to claim 1, characterized in that: The forming of a first gate through hole penetrating the first associated electron gate dielectric layer comprises: Depositing a first dielectric material on the first gate structure and the first source-drain metal to form a first back-end dielectric layer; The first back-end dielectric layer and the first associated electronic gate dielectric layer are photolithographically processed, and the photolithography stops at the first gate structure to form a first gate through hole groove; the first gate through hole groove penetrates the first back-end dielectric layer and the first associated electronic gate dielectric layer, A metal material is deposited in the first gate through hole groove to form the first gate through hole.

6. The method according to claim 1, characterized in that A first power rail is provided in the first back-end interconnect layer; the first power rail is electrically connected to the first source-drain metal; A second power rail is disposed in the second back-end interconnect layer; the second power rail is electrically connected to the second source-drain metal.

7. The method according to claim 1, characterized in that The first layer of metal interconnection lines in the first back-end interconnection layer are electrically connected to the first source and drain metal; The first layer of metal interconnection lines in the second back-end interconnection layer is electrically connected to the second source-drain metal.

8. The method according to claim 1, characterized in that The stacked transistor further includes a third transistor and a fourth transistor; the third transistor and the fourth transistor are stacked in the first direction; The method further comprises: In the process of forming the first transistor, the third transistor is prepared simultaneously; the first transistor is arranged side by side with the third transistor in a second direction; the second direction is perpendicular to the first direction; During the process of forming the second transistor, the fourth transistor is prepared simultaneously; the second transistor is arranged side by side with the fourth transistor in the second direction.

9. A stacked transistor, characterized in that: Prepared by the method according to any one of claims 1 to 8, the stacked transistor comprises: a first transistor; a second transistor; the first transistor and the second transistor are stacked in a first direction; a first gate through hole; the first gate through hole passes through a first gate region of the first transistor and is connected to a second gate structure of the second transistor; the first gate through hole is connected to a first layer of metal interconnection line in a first back-end interconnection layer of the first transistor; A second gate through hole; the second gate through hole passes through the second gate region of the second transistor and is connected to the first gate structure of the first transistor; the second gate through hole is connected to the first layer of metal interconnection line in the second back-end interconnection layer of the second transistor.

10. A semiconductor device, characterized in that: include: The stacked transistor as claimed in claim 9.

11. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 10, wherein the semiconductor device is arranged on the circuit board.

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