Manufacturing method of semiconductor structure

Abstract

The manufacturing method of the semiconductor structure comprises the following steps. A substrate is received, wherein a top electrode of the buried capacitor is exposed from the substrate. An oxide layer is formed on the substrate. A patterned sacrificial layer is formed on the oxide layer and exposes a portion of the oxide layer. And forming a metal layer to cover the part of the oxide layer. Forming a patterned dielectric layer on the metal layer; a spacer is formed on a sidewall of the patterned dielectric layer. The metal layer is patterned to form a gap using the spacer and the patterned dielectric layer as a mask. The gap is filled with a filler. The patterned sacrificial layer is removed to expose a top electrode of the buried capacitor. A gate structure is formed on a top electrode of the embedded capacitor. The method can reduce the production cost.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor structure. Background Art

[0002] For many modern applications, semiconductor components are indispensable. With the progress of electronic technology, the size of semiconductor components has become smaller and smaller, while providing better functions and including a larger number of integrated circuits. Due to the miniaturization of the specifications of semiconductor components, different types and size scales of semiconductor components with different functions are integrated and packaged in a single module. Furthermore, many manufacturing steps are performed in the integration of various types of semiconductor devices.

[0003] However, the manufacturing and integration of such semiconductor components involve many complex steps and operations. The integration in such semiconductor components has become more and more complex. The increase in the complexity of the manufacturing and integration of such semiconductor components can cause multiple defects. Accordingly, there is a need to continuously improve the manufacturing process of such semiconductor components in order to address such defects and enhance their performance. Summary of the Invention

[0004] One aspect of the present invention is to provide a method for manufacturing a semiconductor structure. This method includes the following steps. Receive a substrate, wherein the top electrode of the buried capacitor is exposed from the substrate. Form an oxide layer on the substrate. Form a patterned sacrificial layer on the oxide layer and expose a part of the oxide layer. Form a metal layer covering the said part of the oxide layer. Form a patterned dielectric layer on the metal layer, wherein the top surface of the patterned dielectric layer is flush with the top surface of the patterned sacrificial layer. Form spacers on the sidewalls of the patterned dielectric layer. Use the spacers and the patterned dielectric layer as masks to pattern the metal layer to form a gap. Fill the gap with a filler. Remove the patterned sacrificial layer to expose the top electrode of the buried capacitor. Form a gate structure on the top electrode of the buried capacitor.

[0005] In one or more embodiments, the patterned sacrificial layer and the top electrode of the buried capacitor are substantially flush.

[0006] In one or more embodiments, forming the patterned sacrificial layer includes: forming a sacrificial layer covering the oxide layer; forming a patterned photoresist layer on the sacrificial layer; and patterning the sacrificial layer to form the patterned sacrificial layer by using the patterned photoresist layer as a mask.

[0007] In one or more embodiments, forming the metal layer covering the said part of the oxide layer includes: depositing a metal material covering the said part of the oxide layer and the patterned sacrificial layer; etching back the metal material; and recessing the metal material to form a metal layer, wherein the height of the metal layer is lower than the height of the patterned sacrificial layer.

[0008] In one or more embodiments, forming a patterned dielectric layer on a metal layer includes: depositing an oxide material layer to cover the metal layer and a patterned sacrificial layer; etching back and recessing the oxide material layer such that a top surface of the oxide material layer is lower than a top surface of the patterned sacrificial layer; depositing a nitride material layer to cover the oxide material layer and the patterned sacrificial layer; etching back the nitride material layer such that a top surface of the nitride material layer is flush with the top surface of the patterned sacrificial layer; depositing a carbon layer to cover the nitride material layer and the patterned sacrificial layer; forming a patterned photoresist layer on the carbon layer; using the patterned photoresist layer as a mask to pattern the carbon layer, the nitride material layer, and the oxide material layer; and removing the patterned photoresist layer and the patterned carbon layer to form the patterned dielectric layer.

[0009] In one or more embodiments, forming a patterned dielectric layer on a metal layer includes: forming the patterned dielectric layer between patterned sacrificial layers, wherein sidewalls of the patterned dielectric layer are spaced apart from sidewalls of the closest patterned sacrificial layer.

[0010] In one or more embodiments, spacers located on the patterned dielectric layer are spaced apart from spacers located on the closest patterned sacrificial layer.

[0011] In one or more embodiments, a gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer, and the gate electrode includes indium gallium zinc oxide.

[0012] In one or more embodiments, a method of manufacturing a semiconductor structure further includes forming a landing pad on the gate structure.

[0013] Another aspect of the present invention is to provide a method of manufacturing a semiconductor structure. The method includes the following steps. Receiving a substrate, wherein top electrodes of a plurality of buried capacitors are exposed from the substrate. Depositing a metal layer on the substrate, wherein lower portions of a plurality of dummy pillars are surrounded by the metal layer. Forming a patterned dielectric layer on the metal layer and between two adjacent dummy pillars. Forming spacers on sidewalls of the patterned dielectric layer and on upper portions of each of these dummy pillars. Using the spacers and the patterned dielectric layer as a mask to pattern the metal layer to form gaps. Filling the gaps with a filler. Removing the dummy pillars to expose the top electrodes of the buried capacitors. Forming a plurality of gate structures on the top electrodes of the buried capacitors.

[0014] In one or more embodiments, a method of manufacturing a semiconductor structure further includes forming an oxide layer between the substrate and the dummy pillars.

[0015] In one or more embodiments, the dummy pillars are arranged at intervals.

[0016] In one or more embodiments, each of the virtual pillars has a circular profile in a top view.

[0017] In one or more embodiments, the vertical projection of each of the virtual pillars on the substrate substantially overlaps with the vertical projection of each of the top electrodes on the substrate.

[0018] In one or more embodiments, the thickness of each of the virtual pillars is greater than the thickness of the metal layer.

[0019] In one or more embodiments, in a top view, the width of the patterned dielectric layer is substantially the same as the diameter of each of the virtual pillars.

[0020] In one or more embodiments, in a top view, the edges of the patterned dielectric layer are surrounded by spacers.

[0021] In one or more embodiments, the filler includes an oxide.

[0022] In one or more embodiments, each of the gate structures includes a gate dielectric layer and a gate electrode located on the gate dielectric layer, and the gate electrode includes indium gallium zinc oxide.

[0023] In one or more embodiments, a method of manufacturing a semiconductor structure further includes: forming a plurality of landing pads on the gate structures.

[0024] With reference to the following description and the appended claims, these and other features, aspects, and advantages of the present invention will become better understood.

[0025] It should be understood that the foregoing general description and the following detailed description are merely exemplary and explanatory and are intended to provide further explanation of the claimed invention. Brief Description of the Drawings

[0026] The present invention can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings.

[0027] Figure 1A is a cross-sectional schematic diagram of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0028] Figure 1B is Figure 1A a top view schematic diagram of

[0029] Figure 2A is a cross-sectional schematic diagram of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0030] Figure 2B is Figure 2A a top view schematic diagram of

[0031] Figure 3A is a cross-sectional schematic view of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0032] Figure 3B is Figure 3A a top view schematic of

[0033] Figure 4A is a cross-sectional schematic view of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0034] Figure 4B is Figure 4A a top view schematic of

[0035] Figure 5A is a cross-sectional schematic view of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0036] Figure 5B is Figure 5A a top view schematic of

[0037] Figure 6A is a cross-sectional schematic view of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0038] Figure 6B is Figure 6A a top view schematic of

[0039] Figure 7A is a cross-sectional schematic view of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0040] Figure 7B is Figure 7A a top view schematic of

[0041] Figure 8A is a cross-sectional schematic view of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0042] Figure 8B is Figure 8A a top view schematic of

[0043] Figure 9A is a cross-sectional schematic view of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0044] Figure 9B is Figure 9A a top view schematic of

[0045] Figure 10A is a cross-sectional schematic view of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0046] Figure 10B is Figure 10A a top view schematic diagram of

[0047] Figure 11A a cross-sectional schematic diagram of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0048] Figure 11B is Figure 11A a top view schematic diagram of

[0049] Figure 12A a cross-sectional schematic diagram of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0050] Figure 12B is Figure 12A a top view schematic diagram of

[0051] Figure 13A a cross-sectional schematic diagram of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0052] Figure 13B is Figure 13A a top view schematic diagram of

[0053] Figure 14A a cross-sectional schematic diagram of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0054] Figure 14B is Figure 14A a top view schematic diagram of

[0055] Figure 15A a cross-sectional schematic diagram of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0056] Figure 15B is Figure 15A a top view schematic diagram of

[0057] Figure 16A a cross-sectional schematic diagram of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0058] Figure 16B is Figure 16A a top view schematic diagram of

[0059] Figure 17A a cross-sectional schematic diagram of an exemplary semiconductor structure during various manufacturing stages according to some embodiments.

[0060] Figure 17B is Figure 17A a top view schematic diagram of

[0061] Figure 18Partial perspective view of a semiconductor structure at various manufacturing stages according to some embodiments. Detailed Description

[0062] Embodiments of the present invention will now be described in detail, and examples thereof are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or similar components.

[0063] Examples of the present invention are specifically given below and will be described in detail with reference to the accompanying drawings. The elements and designs of the following examples are for simplifying the disclosed invention and are not intended to limit the present invention. When it is mentioned in the specification that a first structural feature is formed above a second structural feature, it includes embodiments in which the first structural feature and the second structural feature are in direct contact, and also includes embodiments in which there are other structural features between the first structural feature and the second structural feature, that is, the first structural feature and the second structural feature are not in direct contact. In addition, the present invention may use repeated reference symbols and / or words in various embodiments. These repeated symbols or words are for the purpose of simplification and clarity and are not intended to limit the relationship between various embodiments and / or the described structures.

[0064] In addition, for ease of description, spatial relative terms, such as "beneath", "below", "lower", "above", "on", "upper" and the like, may be used herein to describe the relationship of one element or feature to another or other elements or features illustrated in the figures. In addition to the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the present invention belong. It should be understood that terms defined in common dictionaries, for example, should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of the present invention, and should not be interpreted as having an overly formal meaning unless explicitly defined herein.

[0066] Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B are various schematic diagrams of intermediate stages of forming a semiconductor structure according to some embodiments of the present invention.

[0067] First, referring to Figure 1A and Figure 1B , a substrate 100 is received as a basis for forming a device, component, or circuit. In some embodiments, the substrate 100 may be a semiconductor substrate. The substrate 100 may include silicon (Si), gallium (Ga), gallium arsenide (GaAs), gallium nitride (GaN), strained silicon, silicon germanium (SiGe), silicon carbide (SiC), diamond, an epitaxial layer, or a combination thereof, but the present invention is not limited thereto. The substrate 100 may include single-crystalline silicon, consist essentially of single-crystalline silicon, or be composed of single-crystalline silicon, and may be referred to as a semiconductor substrate or a part of a semiconductor substrate. In some embodiments, a well region (not shown) may be formed in the substrate 100. The well region may be neutral, or an n-type or p-type doped region, depending on the conduction type of the transistor structure to be formed later. An isolation structure (not shown), such as a shallow trench isolation (hereinafter referred to as STI) structure, is formed in the substrate 100 to define at least one active region (not shown).

[0068] The terms "semiconductive substrate", "semiconductor construction", and "semiconductor substrate" refer to any structure that includes semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or as a component composed of other materials), and regions of semiconductor material (alone or as a component composed of other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above. Although the substrate 100 in the embodiments of the present invention is shown as homogenous, in some embodiments, the substrate may include multiple materials. For example, the substrate 100 may correspond to a semiconductor substrate that includes one or more materials related to integrated circuit manufacturing. In such embodiments, such materials may correspond to one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0069] Figure 1A is a cross-sectional schematic view along Figure 1B line A-A in. As Figure 1A and Figure 1B shown, the top electrode 104 of the buried capacitor 102 is exposed from the substrate 100. In some embodiments, the upper surface of the top electrode 104 is substantially flush with the top surface 101 of the substrate 100, as Figure 1A shown. It is worth noting that Figure 1A only shows a partial structure of the buried capacitor 102. It can be understood that the buried capacitor 102 at least includes a top electrode 104, a bottom electrode (not shown), and a dielectric layer (not shown) between the top electrode 104 and the bottom electrode. In some embodiments, the top electrode 104 exposed from the top surface 101 of the substrate 100 has a substantially circular profile in a top view, as Figure 1B shown. In some embodiments, in Figure 1B , the top electrodes 104 are spaced in a column in the Y direction and are staggered from each other in the X direction. In addition, the number of buried capacitors 102 can also be multiple.

[0070] Next, referring to Figure 2A and Figure 2B, an oxide layer 110 is formed on the substrate 100. Specifically, the oxide layer 110 completely covers the top surface 101 of the substrate 100. In other words, the oxide layer 110 also covers the top electrode 104 of the buried capacitor 102. The oxide layer 110 is conformally formed on the top surface 101 of the substrate 100. In some embodiments, the oxide layer 110 is an insulating oxide layer. The insulating oxide layer is made of any suitable dielectric material, such as silicon oxide, boro - phospho silicate glass (BPSG), or tetraethyl orthosilicate (TEOS), but the present invention is not limited to the above materials.

[0071] Refer to Figure 4A and Figure 4B , and then a patterned sacrificial layer 125 is formed on the oxide layer 110, and a part 112 of the oxide layer 110 is exposed. In some embodiments, the patterned sacrificial layer 125 is substantially flush with the top electrode 104 of the buried capacitor 102. The patterned sacrificial layer 125 can be considered as a plurality of dummy pillars disposed on the oxide layer 110 as shown in Figure 4A . In some embodiments, these dummy pillars are arranged at intervals. It can be understood that the vertical projection of each of these dummy pillars on the substrate 100 substantially overlaps with the vertical projection of each of the top electrodes 104 on the substrate 100. That is to say, the arrangement of the dummy pillars is the same as the arrangement of the top electrodes 104 of the buried capacitor 102. Therefore, these dummy pillars are substantially aligned with the top electrodes 104 of the buried capacitor 102. In some embodiments, each of these dummy pillars has a circular profile in a top view, as shown in Figure 4B .

[0072] Please refer to Figure 2A , Figure 2B , Figure 3A and Figure 3B to understand the formation of the patterned sacrificial layer 125 (also referred to as dummy pillars). The patterned sacrificial layer 125 (or dummy pillars) can be formed by a lithography process. The formation of the patterned sacrificial layer 125 includes the following steps. First, a sacrificial layer 120 is deposited to cover the substrate 100, as shown in Figure 2A and Figure 2B . In some embodiments, the sacrificial layer 120 may include polysilicon and the like. Then, a patterned photoresist layer 300 is formed on the sacrificial layer 120, as shown in Figure 3A and Figure 3BAs shown, the sacrificial layer 120 is patterned using the patterned photoresist layer 300 as a mask to form the patterned sacrificial layer 125. The patterned sacrificial layer 125 can be formed using a photolithography process.

[0073] Refer to Figure 5A and Figure 5B , a metal layer 135 is formed to cover the portion 112 of the oxide layer 110. The lower part of the patterned sacrificial layer 125 (or dummy pillar) is surrounded by the metal layer 135. In some embodiments, the thickness of the patterned sacrificial layer 125 is greater than the thickness of the metal layer 135. More specifically, the formation of the metal layer 135 includes the following steps. A metal material (not shown) is deposited to cover the portion 112 of the oxide layer 110 and the patterned sacrificial layer 125. In some embodiments, the metal material may include tungsten (W). Then, the metal material is etched back and recessed to form the metal layer 135. It should be noted that the height of the metal layer 135 is lower than the height of the patterned sacrificial layer 125.

[0074] Refer to Figure 8A and Figure 8B , a patterned dielectric layer 145 is formed on the metal layer 135. In some embodiments, the patterned dielectric layer 145 is formed between the patterned sacrificial layers 125. That is, the patterned dielectric layer 145 is formed between two adjacent dummy pillars, as Figure 8A shown. Specifically, the top surface 147 of the patterned dielectric layer 145 is flush with the top surface 127 of the patterned sacrificial layer 125. In some embodiments, as Figure 8B shown, in a top view, the width 146 of the patterned dielectric layer 145 is substantially the same as the diameter 126 of each of the plurality of dummy pillars. In some embodiments, the sidewall of the patterned dielectric layer 145 is spaced apart from the sidewall of the nearest patterned sacrificial layer 125. In other words, there is a first distance D1 between the sidewall of the patterned dielectric layer 145 and the sidewall of the nearest patterned sacrificial layer 125, and the first distance D1 is greater than 0.

[0075] Please refer to Figure 6A , Figure 6B , Figure 7A and Figure 7BTo understand the formation of the patterned dielectric layer 145. In some embodiments, the formation of the patterned dielectric layer 145 includes the following steps. First, a layer of oxide material 141 is deposited to cover the metal layer 135 and the patterned sacrificial layer 125. Next, the oxide material layer 141 is etched back and recessed such that the top surface of the oxide material layer is lower than the top surface of the patterned sacrificial layer. Next, a patterned nitride material layer 142 is deposited to cover the oxide material layer 141 and the patterned sacrificial layer 125. Then, the patterned nitride material layer 142 is etched such that the top surface of the patterned nitride material layer 142 is flush with the top surface of the patterned sacrificial layer 125. Then a carbon layer 143 is deposited to cover the patterned nitride material layer 142 and the patterned sacrificial layer 125. A patterned photoresist layer 400 is formed on the carbon layer 143. Using the patterned photoresist layer 400 as a mask, the carbon layer 143, the patterned nitride material layer 142, and the oxide material layer 141 are patterned. Finally, the patterned photoresist layer 400 and the patterned carbon layer 143 are removed to form the patterned dielectric layer 145. In some embodiments, the patterned photoresist layer 400 and the patterned carbon layer 143 are removed by a strip process such that the patterned oxide material layer 141 and the patterned nitride material layer 142 remain on the metal layer 135. In other words, the patterned dielectric layer 145 includes the patterned oxide material layer 141 and the patterned nitride material layer 142.

[0076] Refer to Figure 9A and Figure 9B , spacers 155 are formed on the sidewalls of the patterned dielectric layer 145. More specifically, the spacers 155 are formed on the sidewalls of the patterned dielectric layer 145 and on the upper portions of each of the plurality of dummy pillars. In some embodiments, as viewed from a top view, the edges of the patterned dielectric layer 145 are surrounded by the spacers 155, as Figure 9B shown. In some embodiments, the spacers 155 on the patterned dielectric layer 145 are spaced apart from the spacers 155 on the nearest patterned sacrificial layer 125. In other words, the second distance D2 is greater than 0 and less than the first distance D1. In some embodiments, the spacers 155 may include silicon nitride, SiCO, silicon oxide (SiO 2 ) and the like.

[0077] In some embodiments, the formation of the spacer 155 may include conformally forming an insulating layer (not shown) on the top surface 127 and sidewalls of the patterned sacrificial layer 125, the metal layer 135, and the top surface 147 and sidewalls of the patterned dielectric layer 145. In some embodiments, the insulating layer may be formed by any suitable deposition method, such as chemical vapor deposition (CVD) techniques, atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques. Then, a portion of the insulating layer on the top surface 127 of the patterned sacrificial layer 125, the metal layer 135, and the top surface 147 of the patterned dielectric layer 145 is removed by an anisotropic etching process.

[0078] Refer to Figure 10A and Figure 10B , using the spacer 155 and the patterned dielectric layer 145 as masks, the metal layer 135 is patterned to form the gap 160. In some embodiments, the width of the gap 160 is the same as the second distance D2.

[0079] Refer to Figure 11A and Figure 11B , the filler 170 is filled in the gap 160. In some embodiments, the filler 170 may include an oxide. In some embodiments, the filler 170 may include an insulating oxide, such as silicon oxide, etc. The formation of the filler 170 may include the following steps. In some embodiments, the filler 170 may be formed by a single gap-filling process based on a fluid oxide layer. In some other embodiments, the filler 170 may be configured in a combined form (e.g., a stacked form) of a fluid oxide layer and a deposited oxide layer. For example, the fluid oxide layer may include spin-on dielectric (SOD), and the deposited oxide layer may include a high-density plasma (HDP) oxide layer. Then, the filler 170 is polished by chemical mechanical polishing (CMP) such that the top surface 177 of the filler 170 is flush with the top surface 127 of the patterned sacrificial layer 125.

[0080] Refer to Figure 12A and Figure 12B , the patterned sacrificial layer 125 (dummy pillar) is removed. Refer to Figure 13A and Figure 13B, a portion of the oxide layer 110 is removed to form an opening 500, and the top electrode 104 of the embedded capacitor 102 is exposed from the opening 500. In addition, the patterned nitride material layer 142 of the patterned dielectric layer 145 is also removed. In some embodiments, the removal of the portion of the oxide layer 110 and the removal of the patterned nitride material layer 142 can be performed in the same process or different processes.

[0081] Refer to Figure 16A and Figure 16B , a gate structure 180 is formed on the top electrode 104 of the embedded capacitor 102. In some embodiments, the gate structure 180 includes a gate dielectric layer 182 and a gate electrode 184 disposed on the gate dielectric layer 182. In some embodiments, the gate electrode 184 may include indium gallium zinc oxide (IGZO).

[0082] The formation of the gate structure 180 can refer to Figure 14A , Figure 14B , Figure 15A and Figure 15B . In some embodiments, the gate dielectric layer 182 can be formed by conformally depositing a gate dielectric material (not shown) in the opening 500 and CMPing the gate dielectric material, as Figure 14A and Figure 14B shown.

[0083] In some embodiments, the gate dielectric material includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-K dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-K dielectric materials include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium dioxide, hafnium oxide-aluminum oxide (HfO 2 -Al 2 O 3 ) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The gate dielectric material can be formed by CVD, ALD, or any suitable deposition technique.

[0084] Next, the gate electrode 184 can be formed on the gate dielectric layer 182 in the opening 500 using CVD, ALD, electroplating, or other suitable deposition techniques, as Figure 15A and Figure 15B shown.

[0085] Figure 18 is a partial perspective view of a semiconductor structure at various manufacturing stages according to some embodiments. Refer to Figure 18 , a landing pad 200 is formed on the gate structure 180. The formation of the landing pad 200 can refer toFigure 16A , Figure 16B , Figure 17A and Figure 17B . In some embodiments, the landing pad 200 is substantially aligned with the gate structure 180.

[0086] Referring Figure 16A and Figure 16B , a first conductive material 210 is formed over the gate structure 180, the filler 170, the oxide material layer 141, and the spacer 155. That is, the first conductive material 210 completely covers Figure 15A and Figure 15B the surfaces of the structures shown. In some embodiments, the first conductive material 210 may include indium tin oxide (ITO). In some embodiments, CVD, ALD, PVD, or other suitable deposition processes may be used to deposit the first conductive material 210.

[0087] Referring Figure 17A and Figure 17B , a second conductive material 220 is formed over the first conductive material 210. In some embodiments, the second conductive material 220 includes a conductive material. For example, the conductive material is a void-free structure. To achieve a void-free structure, forming the conductive material may include several deposition processes and etching processes. In some embodiments, a deposition / etch / dep (dep / etch / dep) process is used to deposit the conductive material into a gap (not shown) between two adjacent bit line structures 110. The deposition-etch-deposition process includes depositing the conductive material, then etching a portion of the conductive material to widen the opening of the gap (not shown), and then redepositing the conductive material. In some embodiments, the second conductive material 220 may include stacked materials that include metal nitrides or metals such as tungsten, tungsten nitride, and / or titanium nitride. In some embodiments, CVD, ALD, PVD, or other suitable deposition processes may be used to deposit the second conductive material 220. In some embodiments, the deposition temperature used during the deposition process is in the range of about 280°C to about 320°C. For example, the deposition temperature employed during the deposition process may be 280°C, 290°C, 300°C, 310°C, or 320°C. The etching process performed after the deposition process includes using any suitable dry etching process and / or wet etching process.

[0088] Referring Figure 18, at least a portion of the first conductive material 210 and the second conductive material 220 is removed to form the landing pad 200. A mask pattern (not shown) may be formed on the second conductive material 220. Subsequently, with the mask pattern as an etching mask, the first conductive material 210 and the second conductive material 220 are etched. In other words, the landing pad 200 includes the patterned first conductive material 212 and the patterned second conductive material 222. In addition, the landing pad 200 is formed based on the first conductive material 210 and the second conductive material 220. Therefore, the landing pad 200 may include a void-free structure.

[0089] The present invention provides a method for manufacturing a novel semiconductor structure, which can fabricate semiconductor devices with smaller sizes. In addition, the method for manufacturing the novel semiconductor structure of the present invention can reduce production costs. In addition, the performance of the semiconductor structure can also be improved.

[0090] Although the present invention has been described in considerable detail with reference to certain embodiments, there may be other embodiments. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0091] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the present invention that fall within the appended claims.

[0092]

Symbol Description

[0093] 100: Substrate

[0094] 101: Top surface

[0095] 102: Buried capacitor

[0096] 104: Top electrode

[0097] 110: Oxide layer

[0098] 112: Portion

[0099] 120: Sacrificial layer

[0100] 125: Patterned sacrificial layer

[0101] 126: Diameter

[0102] 127: Top surface

[0103] 135: Metal layer

[0104] 141: Oxide material layer

[0105] 142: Patterned nitride material layer

[0106] 143: Carbon layer

[0107] 145: Patterned dielectric layer

[0108] 146: Width

[0109] 147: Top surface

[0110] 155: Spacer

[0111] 160: Gap

[0112] 170: Filler

[0113] 177: Top surface

[0114] 180: Gate structure

[0115] 182: Gate dielectric layer

[0116] 184: Gate electrode

[0117] 200: Landing pad

[0118] 210: First conductive material

[0119] 220: Second conductive material

[0120] 212: Patterned first conductive material

[0121] 222: Patterned second conductive material

[0122] 300: Patterned photoresist layer

[0123] 400: Patterned photoresist layer

[0124] 500: Opening

[0125] A-A: Line

[0126] D1: First distance

[0127] D2: Second distance

[0128] X: Direction

[0129] Y: Direction

[0130] Z: Direction.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: a receiving substrate, wherein a top electrode of the embedded capacitor is exposed from the substrate; forming an oxide layer on the substrate; forming a patterned sacrificial layer on the oxide layer and exposing a portion of the oxide layer; forming a metal layer covering the portion of the oxide layer; forming a patterned dielectric layer on the metal layer, wherein a top surface of the patterned dielectric layer is flush with a top surface of the patterned sacrificial layer; forming spacers on sidewalls of the patterned dielectric layer; patterning the metal layer to form a gap using the spacer and the patterned dielectric layer as a mask; filling the gap with a filler; removing the patterned sacrificial layer to expose the top electrode of the embedded capacitor; as well as A gate structure is formed on the top electrode of the buried capacitor. 2 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the patterned sacrificial layer and the top electrode of the embedded capacitor are substantially flush.

3. The method for manufacturing a semiconductor structure according to claim 1 , wherein forming the patterned sacrificial layer comprises: forming a sacrificial layer to cover the oxide layer; forming a patterned photoresist layer on the sacrificial layer; as well as The sacrificial layer is patterned by using the patterned photoresist layer as a mask to form the patterned sacrificial layer.

4. The method for manufacturing a semiconductor structure according to claim 1 , wherein forming the metal layer to cover the portion of the oxide layer comprises: depositing a metal material covering the portion of the oxide layer and the patterned sacrificial layer; Etching back the metal material; as well as The metal material is recessed to form the metal layer, wherein the height of the metal layer is lower than the height of the patterned sacrificial layer.

5. The method for manufacturing a semiconductor structure according to claim 1 , wherein forming the patterned dielectric layer on the metal layer comprises: depositing an oxide material layer to cover the metal layer and the patterned sacrificial layer; Etching back and recessing the oxide material layer so that a top surface of the oxide material layer is lower than a top surface of the patterned sacrificial layer; depositing a nitride material layer to cover the oxide material layer and the patterned sacrificial layer; Etching back the nitride material layer so that a top surface of the nitride material layer is flush with the top surface of the patterned sacrificial layer; Depositing a carbon layer to cover the nitride material layer and the patterned sacrificial layer; forming a patterned photoresist layer on the carbon layer; Using the patterned photoresist layer as a mask, patterning the carbon layer, the nitride material layer and the oxide material layer; as well as The patterned photoresist layer and the patterned carbon layer are removed to form the patterned dielectric layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein forming the patterned dielectric layer on the metal layer comprises: The patterned dielectric layer is formed between the patterned sacrificial layers, wherein the sidewall of the patterned dielectric layer is spaced apart from the sidewall of the closest patterned sacrificial layer. 7 . The method for manufacturing a semiconductor structure according to claim 6 , wherein the spacer on the patterned dielectric layer and the spacer on the closest patterned sacrificial layer are spaced apart from each other. 8 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the gate structure comprises a gate dielectric layer and a gate electrode located on the gate dielectric layer, and the gate electrode comprises indium gallium zinc oxide.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: Further including: A landing pad is formed on the gate structure.

10. A method for manufacturing a semiconductor structure, characterized in that: include: a receiving substrate, wherein a plurality of top electrodes of a plurality of embedded capacitors are exposed from the substrate; Depositing a metal layer on the substrate, wherein lower portions of the virtual pillars are surrounded by the metal layer; forming a patterned dielectric layer on the metal layer and between two adjacent dummy pillars; forming spacers on sidewalls of the patterned dielectric layer and on an upper portion of each of the plurality of dummy pillars; patterning the metal layer to form a gap using the spacer and the patterned dielectric layer as a mask; filling the gap with a filler; removing the plurality of dummy pillars to expose the plurality of top electrodes of the plurality of embedded capacitors; as well as A plurality of gate structures are formed on the plurality of top electrodes of the plurality of buried capacitors.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: Further including: An oxide layer is formed between the substrate and the plurality of dummy pillars. 12 . The method for manufacturing a semiconductor structure according to claim 10 , wherein the plurality of dummy pillars are arranged at intervals. 13 . The method for manufacturing a semiconductor structure according to claim 10 , wherein each of the plurality of dummy pillars has a circular outline in a top view. 14 . The method for manufacturing a semiconductor structure according to claim 10 , wherein a vertical projection of each of the plurality of virtual pillars on the substrate substantially overlaps with a vertical projection of each of the plurality of top electrodes on the substrate. 15 . The method for manufacturing a semiconductor structure according to claim 10 , wherein a thickness of each of the plurality of dummy pillars is greater than a thickness of the metal layer. 16 . The method for manufacturing a semiconductor structure according to claim 10 , wherein in a top view, a width of the patterned dielectric layer is substantially the same as a diameter of each of the plurality of dummy pillars. 17 . The method for manufacturing a semiconductor structure according to claim 10 , wherein in a top view, an edge of the patterned dielectric layer is surrounded by the spacer. The method for manufacturing a semiconductor structure according to claim 10 , wherein the filler comprises an oxide. 19 . The method for manufacturing a semiconductor structure according to claim 10 , wherein each of the plurality of gate structures comprises a gate dielectric layer and a gate electrode located on the gate dielectric layer, and the gate electrode comprises indium gallium zinc oxide.

20. The method for manufacturing a semiconductor structure according to claim 10, wherein: Further including: A plurality of landing pads are formed on the plurality of gate structures.

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