Electronic device

Abstract

An electronic device includes a substrate, a first fan-out line, a second fan-out line, and a multiplexer circuit. The substrate has an active region and a fan-out region. The first fan-out line is located in the fan-out area and is provided with a first section. The second fan-out line is located in the fan-out area and is provided with a second section. The first section overlaps the second section. The multiplexer circuit is located between the active region and the fan-out region and is coupled to the first fan-out line and the second fan-out line. The first fan-out line receives a first data signal, and the second fan-out line receives a second data signal. The polarity of the first data signal is opposite to that of the second data signal.

Description

Technical Field

[0001] The present invention relates to an electronic device with a display function. Background Art

[0002] A display device equipped with a multiplexer circuit has a frequency conversion function. When the display device is frequency-converted to a low frequency, the problem of gray-scale flicker being easily visible to the human eye may occur due to the low frame rate, thereby reducing the display quality of the display device. The reason is that the lengths of the fan-out lines are different, resulting in uneven voltage distribution on the data lines. Summary of the Invention

[0003] According to an embodiment of the present invention, an electronic device includes a substrate, a first fan-out line, a second fan-out line, and a multiplexer circuit. The substrate has an active area and a fan-out area. The first fan-out line is located in the fan-out area and has a first section. The second fan-out line is located in the fan-out area and has a second section. The first section and the second section overlap. The multiplexer circuit is located between the active area and the fan-out area and is coupled to the first fan-out line and the second fan-out line. The first fan-out line receives a first data signal, and the second fan-out line receives a second data signal. The polarities of the first data signal and the second data signal are opposite. Brief Description of the Drawings

[0004] Figure 1 A block diagram showing an electronic device according to an embodiment of the present invention;

[0005] Figure 2 Showing Figure 1 A detailed diagram of the electronic device according to the embodiment;

[0006] Figure 3 Showing Figure 1 A schematic diagram showing an overview of the fan-out line according to the embodiment;

[0007] Figure 4 A schematic diagram showing an overview of a partial section of the fan-out line according to an embodiment of the present invention;

[0008] Figure 5 A schematic diagram showing an overview of a partial section of the fan-out line according to another embodiment of the present invention. Detailed Description of the Embodiments

[0009] The present disclosure can be understood by referring to the following detailed description and simultaneously combining the drawings. It should be noted that, for the convenience of the reader's understanding and for the simplicity of the drawings, only a part of the electronic device is shown in multiple drawings of the present disclosure, and specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of the present disclosure.

[0010] In the following specification and claims, words such as "comprising" and "including" are open-ended terms and should therefore be construed to mean "including but not limited to...".

[0011] It should be understood that although the terms first, second, third, etc. may be used to describe various components, the components are not limited to these terms. These terms are only used to distinguish a single component in the specification from other components. The same terms may not be used in the claims, and the first, second, third, etc. may be replaced according to the order of the component declarations in the claims. Therefore, in the following specification, the first component may be the second component in the claims.

[0012] In some embodiments of the present disclosure, terms related to joining and connecting, such as "connect" and "interconnect", unless otherwise specifically defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, with other structures provided between these two structures. And these terms related to joining and connecting may also include cases where both structures are movable, or both structures are fixed. In addition, the term "coupled" includes any direct and indirect electrical connection means. In the case of direct electrical connection, the endpoints of the components on two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect electrical connection, there are switches, diodes, capacitors, inductors, resistors, other suitable components, or combinations of the above components between the endpoints of the components on two circuits, but not limited thereto.

[0013] The electronic device of the present disclosure may include, but is not limited to, a display device, an antenna device, a sensing device, a light-emitting device, or a splicing device. The electronic device may include a bendable or flexible electronic device. The electronic device may include electronic components. The electronic device includes, for example, a liquid crystal layer or a light-emitting diode (LED). The electronic components may include passive components and active components, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical system components (MEMS), liquid crystal chips, controllers, etc., but are not limited thereto. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), a miniLED, a micro LED, a quantum dot LED, fluorescence, phosphor, or other suitable materials, or a combination of the above, but is not limited thereto. The sensor may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, etc., but is not limited thereto. The controller may include, for example, a timing controller, etc., but is not limited thereto. Hereinafter, the display device will be used as the electronic device to illustrate the present disclosure, but the present disclosure is not limited thereto.

[0014] Reference will now be made in detail to exemplary embodiments of the present disclosure. Examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and the description to represent the same or similar parts.

[0015] Figure 1 A block diagram of an electronic device showing an embodiment of the present invention. Figure 2 Showing Figure 1 A detailed schematic diagram of the electronic device of the embodiment. Please refer to Figure 1 And Figure 2, the electronic device 100 is, for example, a display device with a variable refresh rate (VRR) function. The VRR function can dynamically adjust the refresh rate of the display device, which is abbreviated as frequency conversion. Therefore, the electronic device 100 can switch between multiple different refresh rates within a default time range. For example, the refresh rate of the electronic device 100 can vary within the range of 60 Hertz (Hz) to 360 Hz (such as 60 Hz, 90 Hz, 120 Hz, 240 Hz, 360 Hz, etc.). The above values are not used to limit the present invention.

[0016] Specifically, the electronic device 100 includes a substrate 110, a first fan-out line FL1, a second fan-out line FL2, and a multiplexer circuit 120. The substrate 110 has an active area AA and a fan-out area FA. The first fan-out line FL1 is located in the fan-out area FA. The second fan-out line FL2 is located in the fan-out area FA. The multiplexer circuit 120 is located between the active area AA and the fan-out area FA. The multiplexer circuit 120 is coupled to the first fan-out line FL1 and the second fan-out line FL2. The first fan-out line FL1 receives a first data signal S[m], and the second fan-out line FL2 receives a second data signal S[m + 1].

[0017] The electronic device 100 further includes data drivers 130_1 and 130_2. The data drivers 130_1 and 130_2 are connected to the active area AA through the fan-out area FA and the multiplexer circuit 120. As Figure 2 shown, the data driver 130_1 is used to output the first data signals S[m], S[m + 2], S[m + 4] and the second data signals S[m + 1], S[m + 3], S[m + 5] to drive the corresponding display units PX1, PX2, PX3. The polarities of the first data signal S[m] and the second data signal S[m + 1] are opposite. For example, the first data signals S[m], S[m + 2], S[m + 4] are data signals with a positive polarity, and the second data signals S[m + 1], S[m + 3], S[m + 5] are data signals with a negative polarity. Or, the first data signals S[m], S[m + 2], S[m + 4] are data signals with a negative polarity, and the second data signals S[m + 1], S[m + 3], S[m + 5] are data signals with a positive polarity. Wherein, m is a positive integer greater than 0.

[0018] The electronic device 100 further includes a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1, the second data line DL2, and the third data line DL3 are located in the active area AA and are arranged along a direction X perpendicular to the first data line DL1. The third data line DL3 is located between the first data line DL1 and the second data line DL2. The first data line DL1 and the second data line DL2 receive a first data signal S[m] through a first fan-out line FL1 and a multiplexer circuit 120. The third data line DL3 receives a second data signal S[m+1] through a second fan-out line FL2 and the multiplexer circuit 120.

[0019] Specifically, the multiplexer circuit 120 includes a first switching element SW1, a second switching element SW2, and a third switching element SW3. The first switching element SW1 is coupled to the first data line DL1 and the first fan-out line FL1. The second switching element SW2 is coupled to the second data line DL2 and the first fan-out line FL1. The third switching element SW3 is coupled to the third data line DL3 and the second fan-out line FL2. A first control signal CKH[1] is used to control the on / off states of the first switching element SW1 and the third switching element SW3. For example, the first switching element SW1 and the third switching element SW3 can be turned on according to a high-level or low-level first control signal CKH[1].

[0020] On the other hand, a second control signal CKH[2] is used to control the on / off state of the second switching element SW2. For example, the second switching element SW2 can be turned on according to a high-level or low-level second control signal CKH[2].

[0021] In this embodiment, since both the first data line DL1 and the second data line DL2 receive the first data signal S[m] through the first fan-out line FL1 and the multiplexer circuit 120, the first switching element SW1 and the second switching element SW2 are turned on at different times. For example, when the first data signal S[m] is to be written to the display unit coupled to the first data line DL1, the first switching element SW1 is turned on so that the first data signal S[m] can be transmitted to the first data line DL1 through the multiplexer circuit 120. At this time, the second switching element SW2 is turned off to prevent the first data signal S[m] from being transmitted to the second data line DL2. Conversely, when the first data signal S[m] is to be written to the display unit coupled to the second data line DL2, the second switching element SW2 is turned on so that the first data signal S[m] can be transmitted to the second data line DL2 through the multiplexer circuit 120. At this time, the first switching element SW1 is turned off to prevent the first data signal S[m] from being transmitted to the first data line DL1.

[0022] On the other hand, the first switching element SW1 and the third switching element SW3 can be simultaneously turned on by the first control signal CKH[1], so that the first data signal S[m] and the second data signal S[m + 1] can be respectively transmitted to the first data line DL1 and the third data line DL3 through the multiplexer circuit 120.

[0023] The electronic device 100 further includes a first display unit PX1, a second display unit PX2, and a third display unit PX3. The first display unit PX1, the second display unit PX2, and the third display unit PX3 are located in the active area AA and are respectively coupled to the first data line DL1, the second data line DL2, and the third data line DL3. The first data signal S[m] is used to drive the first display unit PX1 and the second display unit PX2 to display corresponding image contents. The second data signal S[m + 1] is used to drive the third display unit PX3 to display corresponding image contents. In an embodiment, the electronic device can be a liquid crystal display, and the display unit can be a sub-pixel of a liquid crystal panel. In another embodiment, the electronic device can be an organic light-emitting diode display, and the display unit can be a light-emitting diode, but it is not limited thereto.

[0024] The first display unit PX1, the second display unit PX2, and the third display unit PX3 can output lights of different colors. For example, the first display unit PX1, the second display unit PX2, and the third display unit PX3 are a red pixel, a green pixel, and a blue pixel respectively, and output red, green, and blue lights respectively when being driven.

[0025] In Figure 1 , it is illustrated by taking the electronic device 100 including two data drivers 130_1 and 130_2 as an example, but the present invention is not limited thereto. In an embodiment, the electronic device 100 can also include one data driver or multiple data drivers with other quantities to drive the display unit. In addition, in Figure 2 , it is illustrated by taking the layout structure in which the data driver 130_1 is connected to the active area AA through the fan-out area FA and the multiplexer circuit 120, and the layout structure in which the data driver 130_2 is connected to the active area AA through the fan-out area FA and the multiplexer circuit 120 can be analogized accordingly.

[0026] Figure 3 shows Figure 1 a schematic diagram of the outline of the fan-out lines of the embodiment. Please refer to Figure 3 , the first fan-out line FL1 has a first section 310. The second fan-out line FL2 has a second section 320. The first section 310 and the second section 320 overlap in the projection in the vertical direction of the substrate 110. Among them, the vertical direction of the substrate 110 is the Z direction.

[0027] In this embodiment, takingFigure 3 Taking the first fan-out line FL1 and the second fan-out line FL2 with equal line widths in the leftmost group in [reference] as an example, the maximum ratio of the length of the first section 310 to the length of the shorter one among the first fan-out line FL1 and the second fan-out line FL2 (for example, the first fan-out line FL1) can be 99%. Taking Figure 3 the first fan-out line FL1' and the second fan-out line FL2' with equal line widths in the rightmost group in [reference] as an example, the minimum ratio of the length of the first section 310' to the length of the shorter one among the first fan-out line FL1' and the second fan-out line FL2' (for example, the first fan-out line FL1') can be 15%. That is to say, the ratio of the length of the first section 310 to the length of the shorter one among the first fan-out line FL1 and the second fan-out line FL2 is between 15% and 99% (15% ≤ length ratio ≤ 99%). Among them, compared with the fan-out lines FL1 and FL2, the fan-out lines FL1' and FL2' are closer to the middle line C of the fan-out area FA. The closer the fan-out lines FL1' and FL2' are to the middle line C of the fan-out area FA, the smaller their length ratio is, for example, 15%. The farther the fan-out lines FL1 and FL2 are from the middle line C of the fan-out area FA, the larger their length ratio is, for example, 99%.

[0028] Figure 4 A schematic diagram showing a partial section of the fan-out lines according to an embodiment of the present invention. Please refer to Figure 3 and Figure 4 , in Figure 3 the embodiment of [reference], the fan-out lines FL1 and FL2 with equal line widths are taken as examples for illustration, but the present invention is not limited thereto. In Figure 4 the embodiment of [reference], the line widths of the fan-out lines FL1 and FL2 may also be unequal.

[0029] Specifically, in this embodiment, the first fan-out line FL1 has a smaller line width W1 in the direction D perpendicular to the first long side L1, and the second fan-out line FL2 has a larger line width W2 in the direction D perpendicular to the first long side L1. Taking the overlapping section as an example, the projection of the first section 310 in the vertical direction Z of the substrate 110 includes the first long side L1 and the second long side L2, and the projection of the second section 320 in the vertical direction Z of the substrate 110 includes the third long side L3 and the fourth long side L4. In the direction D perpendicular to the first long side L1, the first long side L1 is located between the third long side L3 and the second long side L2, and the second long side L2 is located between the first long side L1 and the fourth long side L4.

[0030] Figure 5 A schematic diagram showing a partial section of the fan-out lines according to another embodiment of the present invention. Please refer to Figure 4 and Figure 5 , in Figure 5In the embodiment, the line widths of the fan-out lines FL1 and FL2 are also not equal. Specifically, in this embodiment, in the direction D perpendicular to the first long side L1, the first long side L1 coincides with the third long side L3, and the second long side L2 is located between the first long side L1 and the fourth long side L4.

[0031] In summary, in the embodiment of the present invention, in the fan-out area, adjacent fan-out lines transmitting different polarity signals have overlapping sections to reduce the voltage difference when different polarity signals are transmitted to the data line. By increasing the area of the overlapping section, the length difference between two adjacent fan-out lines can be shortened, thereby reducing the uneven voltage distribution of the polarity signals on the data line. In addition, near the middle of the fan-out area, the shorter the lengths of two adjacent fan-out lines, the smaller the area of the overlapping section can be designed.

[0032] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic device, comprising: a substrate having an active region and a fan-out region; a first fan-out line located in the fan-out region and having a first section; a second fan-out line located in the fan-out region and having a second section, wherein the first section and the second section overlap in projection in the vertical direction of the substrate; and a multiplexer circuit located between the active region and the fan-out region and coupled to the first fan-out line and the second fan-out line, wherein the first fan-out line receives a first data signal, the second fan-out line receives a second data signal, and the first data signal and the second data signal have opposite polarities.

2. The electronic device according to claim 1, further comprising: a first data line located in the active region and receiving the first data signal through the first fan-out line and the multiplexer circuit; and a second data line located in the active region and receiving the first data signal through the first fan-out line and the multiplexer circuit.

3. The electronic device according to claim 2, wherein the multiplexer circuit comprises: a first switching element coupled to the first data line and the first fan-out line and turned on according to a first control signal; and a second switching element coupled to the second data line and the first fan-out line and turned on according to a second control signal, wherein the first switching element and the second switching element are turned on at different times.

4. The electronic device according to claim 2, further comprising: a first display unit located in the active region and coupled to the first data line; and a second display unit located in the active region and coupled to the second data line, wherein the first display unit and the second display unit output light of different colors.

5. The electronic device according to claim 2, further comprising: a third data line located in the active region and receiving the second data signal through the second fan-out line and the multiplexer circuit.

6. The electronic device according to claim 5, wherein the third data line is located between the first data line and the second data line.

7. The electronic device according to claim 5, wherein the multiplexer circuit comprises: a third switching element coupled to the third data line and the second fan-out line and turned on according to a first control signal.

8. The electronic device according to claim 1, wherein the projection of the first section in the vertical direction of the substrate includes a first long side and a second long side, and the projection of the second section in the vertical direction of the substrate includes a third long side and a fourth long side, wherein in a direction perpendicular to the first long side, the first long side is located between the third long side and the second long side, and the second long side is located between the first long side and the fourth long side.

9. The electronic device according to claim 1, wherein the projection of the first section in the vertical direction of the substrate includes a first long side and a second long side, and the projection of the second section in the vertical direction of the substrate includes a third long side and a fourth long side, Wherein, in a direction perpendicular to the first long side, the first long side coincides with the third long side, and the second long side is located between the first long side and the fourth long side.

10. The electronic device according to claim 1, wherein a ratio of a length of the first section to a length of a shorter one of the first fan-out line and the second fan-out line is between 15% and 99%.

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