Display substrate, display panel and display device

Abstract

The invention discloses a display substrate, a display panel and a display device. The display substrate comprises a substrate body (11), a display area (AA) and a frame area (BA), the display area (AA) and the frame area (BA) are located on one side of the substrate body (11), the display area (AA) comprises a plurality of scanning signal lines (GT) extending in the first direction (f1), a plurality of switching signal lines (SW) extending in the second direction (f2) and a plurality of data signal lines (DT) extending in the second direction (f2), and the first direction (f1) and the second direction (f2) intersect with each other; wherein the scanning signal lines (GT) and the data signal lines (DT) are arranged on different layers, the scanning signal lines (GT) and the switching signal lines (SW) are arranged on different layers, the data signal lines (DT) and the switching signal lines (SW) are arranged on the same layer, the scanning signal lines (GT) are connected with at least one switching signal line (SW), and different scanning signal lines (GT) are connected with different switching signal lines (SW).

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] With the continuous development of display technology, the market has higher and higher requirements for display screens, for example, requiring the border size of display screens to be smaller and smaller.

[0003] Overview

[0004] The present disclosure provides a display substrate, comprising a base substrate, and a display area and a frame area located on one side of the base substrate, wherein the display area comprises:

[0005] A plurality of scanning signal lines extending along a first direction, a plurality of transfer signal lines extending along a second direction, and a plurality of data signal lines extending along the second direction, wherein the first direction and the second direction intersect each other;

[0006] Among them, the scanning signal line and the data signal line are arranged in different layers, the scanning signal line and the transfer signal line are arranged in different layers, the data signal line and the transfer signal line are arranged in the same layer, the scanning signal line is connected to at least one transfer signal line, and different scanning signal lines are connected to different transfer signal lines.

[0007] In some embodiments, the plurality of scan signal lines include a first scan signal line and a second scan signal line, and the number of transfer signal lines connected to the first scan signal line is equal to the number of transfer signal lines connected to the second scan signal line.

[0008] In some embodiments, the plurality of transfer signal lines are divided into a plurality of transfer line groups arranged along a first direction, and the transfer line group includes one or a plurality of adjacent transfer signal lines; and

[0009] The transfer signal lines in the same transfer line group are connected to the same scan signal terminal and the same scan signal line, and the transfer signal lines in different transfer line groups are connected to different scan signal terminals and different scan signal lines.

[0010] In some embodiments, the multiple scan signal lines include a third scan signal line and a fourth scan signal line, and the same number of adapter line groups are arranged between two adjacent adapter line groups connected to the third scan signal line, and between two adjacent adapter line groups connected to the fourth scan signal line.

[0011] In some embodiments, the multiple scan signal lines include a fifth scan signal line and a sixth scan signal line, a first number of adapter line groups are arranged between two adjacent adapter line groups connected to the fifth scan signal line, and a second number of adapter line groups are arranged between two adjacent adapter line groups connected to the sixth scan signal line, and the first number is greater than or less than the second number.

[0012] In some embodiments, the plurality of scan signal lines further include a seventh scan signal line, the sixth scan signal line is located between the fifth scan signal line and the seventh scan signal line, and a third number of adapter line groups are provided between two adjacent adapter line groups connected to the seventh scan signal line;

[0013] The first number, the second number, and the third number increase or decrease sequentially.

[0014] In some embodiments, the plurality of adapter wire groups include: a first adapter wire group, a second adapter wire group, and a third adapter wire group connected to the same scan signal line and arranged sequentially along the first direction;

[0015] The number of patch cord groups arranged between the first patch cord group and the second patch cord group is equal to the number of patch cord groups arranged between the second patch cord group and the third patch cord group.

[0016] In some embodiments, the plurality of scan signal lines include an eighth scan signal line, and the plurality of adapter wire groups include: a fourth adapter wire group, a fifth adapter wire group, and a sixth adapter wire group connected to the eighth scan signal line and arranged sequentially along the first direction;

[0017] A fourth number of patch cord groups are provided between the fourth patch cord group and the fifth patch cord group, a fifth number of patch cord groups are provided between the fifth patch cord group and the sixth patch cord group, and the fourth number is greater than or less than the fifth number.

[0018] In some embodiments, the plurality of scan signal lines further include a ninth scan signal line, and the plurality of adapter wire groups further include: a seventh adapter wire group, an eighth adapter wire group, and a ninth adapter wire group connected to the ninth scan signal line and arranged sequentially along the first direction;

[0019] A sixth number of patch cord groups are provided between the seventh patch cord group and the eighth patch cord group, and a seventh number of patch cord groups are provided between the eighth patch cord group and the ninth patch cord group;

[0020] The fourth number is greater than the fifth number, and the sixth number is smaller than the seventh number, or the fourth number is smaller than the fifth number, and the sixth number is greater than the seventh number.

[0021] In some embodiments, the multiple adapter wire groups include: a tenth adapter wire group and an eleventh adapter wire group connected to the same scanning signal line, the tenth adapter wire group and the eleventh adapter wire group are axially symmetrically arranged about a first axis, and the first axis is the symmetry axis of the positive projection of the display area on the base substrate extending along the second direction.

[0022] In some embodiments, the scan signal lines are connected to the transfer signal lines via transfer holes, and the transfer holes connecting all transfer signal lines in the same transfer line group constitute a transfer hole group;

[0023] In the orthographic projection on the base substrate, the arrangement shapes of the multiple transfer hole groups include at least one of the following: V-shape, inverted V-shape, N-shape, inverted N-shape, a bar extending along a third direction, and multiple bars extending along a third direction and parallel to each other, and the third direction is respectively arranged to intersect with the first direction and the second direction.

[0024] In some embodiments, the number of transfer signal lines included in the transfer line group is M or M+1, where M is a positive integer obtained by rounding down m*3 / (2N*2n), m is the row resolution of the display area, n is the column resolution of the display area, and N is the number of transfer line groups connected to the same scan signal line; and / or

[0025] The difference in the number of transfer signal lines contained in different transfer line groups is less than or equal to 1; and / or

[0026] The number of adapter cable groups connected to different scan signal lines is the same.

[0027] In some embodiments, the scan signal lines are connected to the transfer signal lines via transfer holes, and the transfer holes connecting all transfer signal lines in the same transfer line group constitute a transfer hole group;

[0028] The multiple adapter hole groups are divided into multiple adapter units arranged along the first direction, each adapter unit includes the same number of multiple adapter hole groups, the multiple adapter units include a first adapter unit and a second adapter unit, and the first adapter unit and the second adapter unit are translationally symmetrical or axially symmetrical.

[0029] In some embodiments, the display area includes a plurality of sub-pixels arranged in an array along a row direction and a column direction, the row direction is a first direction, and the column direction is a second direction;

[0030] The plurality of scanning signal lines include: a tenth scanning signal line and an eleventh scanning signal line located on both sides of the same sub-pixel row, the tenth scanning signal line being connected to the sub-pixels in odd-numbered columns in the same sub-pixel row, and the eleventh scanning signal line being connected to the sub-pixels in even-numbered columns in the same sub-pixel row;

[0031] The data signal lines and the transfer signal lines are alternately arranged between two adjacent columns of sub-pixels. One of the data signal lines and the transfer signal lines is arranged between two adjacent columns of sub-pixels. The data signal line is connected to two adjacent columns of sub-pixels located on both sides of the data signal line.

[0032] In some embodiments, the scanning signal line is located between the transfer signal line and the base substrate, and the display area further includes:

[0033] a common electrode layer, located on a side of the transfer signal line away from the base substrate, and comprising a plurality of common electrodes;

[0034] Wherein, in the orthographic projection on the base substrate, the common electrode layer covers the switching signal line at least in the first direction.

[0035] In some embodiments, the scanning signal line is located between the transfer signal line and the base substrate, and the display area further includes:

[0036] A plurality of touch signal lines extend along the second direction, the touch signal lines are located on a side of the data signal lines away from the base substrate, and in an orthographic projection on the base substrate, the touch signal lines at least cover the data signal lines in the first direction.

[0037] In some embodiments, the display area further includes:

[0038] a common electrode layer, located between the data signal line and the touch signal line, or located on a side of the touch signal line away from the base substrate, comprising a plurality of touch blocks separated from each other, each touch block comprising a plurality of common electrodes connected to each other;

[0039] The touch block is connected to one or multiple adjacent touch signal lines through a touch hole. Multiple touch signal lines connected to the same touch block are connected to the same touch signal terminal, and touch signal lines connected to different touch blocks are connected to different touch signal terminals.

[0040] In some embodiments, the common electrode layer is located between the data signal line and the touch signal line, and the display area further includes:

[0041] a first pixel electrode layer, located on a side of the touch signal line facing away from the base substrate, comprising a plurality of first pixel electrodes separated from each other, and a transfer electrode separated from the first pixel electrodes;

[0042] The touch hole includes a half hole and a first through hole. The switching electrode is connected to the touch signal line through the half hole, and the switching electrode is connected to the touch block through the first through hole.

[0043] In some embodiments, the plurality of touch blocks are arranged in an array along a first direction and a second direction, and the plurality of touch blocks are divided into a plurality of touch areas arranged along the first direction, and the touch areas include one column or a plurality of adjacent columns of touch blocks;

[0044] The multiple touch areas include a first touch area and a second touch area, and the multiple touch holes located in the first touch area are axially symmetrical or translationally symmetrical with the multiple touch holes located in the second touch area.

[0045] In some embodiments, the border area includes:

[0046] a touch signal terminal, provided on the same layer as the touch signal line and connected to each other, for providing a touch signal to the touch signal line; and

[0047] a data signal terminal, provided on the same layer as the data signal line and connected to each other, for providing a data signal to the data signal line;

[0048] The touch signal terminal is located between the plurality of data signal terminals, and both the touch signal terminal and the data signal terminal are used to bind a source driver chip.

[0049] In some embodiments, the border area includes:

[0050] a scanning signal terminal provided on the same layer as the scanning signal line and connected to the transfer signal line via hole, for providing a scanning signal to the transfer signal line and the scanning signal line; and

[0051] a data signal terminal, provided on the same layer as the data signal line and connected to each other, for providing a data signal to the data signal line;

[0052] The scan signal terminal and the data signal terminal are located on the same side of the display area.

[0053] In some embodiments, the plurality of scan signal terminals are divided into one or more scan signal binding areas, and the scan signal binding areas are used to bind a gate driver chip;

[0054] The plurality of data signal terminals are divided into a plurality of data signal binding areas, and the data signal binding areas are used to bind the source driver chip;

[0055] The scan signal binding area is set between two adjacent data signal binding areas, and at most one scan signal binding area is set between two adjacent data signal binding areas, and at most two data signal binding areas are set between two adjacent scan signal binding areas.

[0056] In some embodiments, the plurality of data signal binding areas include a first data signal binding area and a second data signal binding area, the first data signal binding area and the second data signal binding area are arranged near a first edge or a second edge, the first edge and the second edge being two opposite edges of the display substrate in a first direction; and

[0057] The scan signal binding area is provided between the first data signal binding area and the second data signal binding area.

[0058] The present disclosure provides a display panel, comprising: a cell substrate, a liquid crystal layer, and a display substrate as described in any embodiment, wherein the liquid crystal layer is located between the cell substrate and the display substrate, and the display area is arranged close to the liquid crystal layer.

[0059] The present disclosure provides a display device, comprising:

[0060] The display substrate according to any one of the embodiments;

[0061] a source driver chip, bound and connected to the frame area, for providing data signals to the data signal lines; and one of the following:

[0062] a gate driver chip, bound and connected to the frame area, located on the same side of the display area as the source driver chip, and configured to provide scan signals to the transfer signal lines and the scan signal lines;

[0063] The gate driving circuit is located in the frame area and on the same side of the display area as the source driving chip, and is used to provide scanning signals to the switching signal lines and the scanning signal lines.

[0064] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0065] BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0067] FIG1 exemplarily shows a schematic planar structural diagram of a display substrate provided by the present disclosure;

[0068] FIG2 exemplarily shows a circuit layout diagram of a first display area;

[0069] FIG3 exemplarily shows a circuit layout diagram of a second display area;

[0070] FIG4 exemplarily shows a schematic diagram of an arrangement structure of a plurality of transfer hole groups;

[0071] FIG5 exemplarily shows another schematic diagram of an arrangement structure of a plurality of transfer hole groups;

[0072] FIG6 exemplarily shows a circuit layout diagram at the junction of the display area and the frame area;

[0073] FIG7 exemplarily shows a schematic cross-sectional structure diagram of the first display area at different positions;

[0074] FIG8 exemplarily shows a schematic cross-sectional structure diagram of the second display area at different positions;

[0075] FIG9 exemplarily shows a schematic diagram of the arrangement of touch units in the display area;

[0076] FIG10 exemplarily shows a schematic diagram of the arrangement of touch holes in a touch block;

[0077] FIG11 exemplarily shows a planar structural diagram of a first pixel electrode layer and a partial enlarged diagram of a display substrate at a touch hole location;

[0078] FIG12 exemplarily shows a schematic diagram of the preparation process of the first display area and the second display area;

[0079] FIG13 exemplarily shows a circuit layout diagram of touch signal terminals and data signal terminals;

[0080] FIG14 exemplarily shows a circuit layout diagram of a scan signal terminal;

[0081] FIG15 exemplarily shows a wiring diagram of a border area;

[0082] FIG16 exemplarily shows a circuit layout diagram of the transfer signal line and the first lead;

[0083] FIG17 exemplarily shows a schematic structural diagram of a first lead, a second lead, and a third lead;

[0084] FIG18 exemplarily shows a schematic structural diagram of a scan signal binding area and a data signal binding area.

[0085] Detailed description

[0086] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0087] 1 , a schematic planar structural diagram of a display substrate provided by the present disclosure is exemplarily shown. As shown in FIG1 , the display substrate includes a base substrate 11 (not shown in FIG1 ), and a display area AA and a frame area BA located on one side of the base substrate 11 .

[0088] 2 and 3 , circuit layout diagrams of two display areas are exemplarily shown. As shown in FIG2 or 3 , the display area AA includes: a plurality of scanning signal lines GT extending along a first direction f1, a plurality of transfer signal lines SW extending along a second direction f2, and a plurality of data signal lines DT extending along the second direction f2. The first direction f1 and the second direction f2 intersect with each other.

[0089] Among them, the scanning signal line GT and the data signal line DT are set on different layers, the scanning signal line GT and the switching signal line SW are set on different layers, the data signal line DT and the switching signal line SW are set on the same layer, the scanning signal line GT is connected to at least one switching signal line SW, and different scanning signal lines GT are connected to different switching signal lines SW.

[0090] In the display substrate provided by the present disclosure, since the scan signal lines GT are connected to the transfer signal lines SW, and both the transfer signal lines SW and the data signal lines DT extend along the second direction f2, the gate driver circuit or gate driver chip and the source driver circuit can be positioned on the same side of the display area AA, thereby reducing the size of the two opposing bezels of the display substrate in the first direction f1. The gate driver circuit and gate driver chip generate scan signals, which are transmitted to the scan signal lines GT via the transfer signal lines SW. The source driver circuit provides data signals to the data signal lines DT.

[0091] Exemplarily, as shown in FIG. 2 or FIG. 3 , the first direction f1 and the second direction f2 are perpendicular to each other.

[0092] Exemplarily, as shown in FIG. 2 or FIG. 3 , the plurality of scan signal lines GT are arranged along the second direction f2 , and the plurality of switching signal lines SW and the plurality of data signal lines DT are arranged along the first direction f1 .

[0093] Exemplarily, each scanning signal line GT in the display area AA is connected to one or more switching signal lines SW.

[0094] In some embodiments, as shown in FIG. 2 or FIG. 3 , the plurality of scan signal lines GT include a first scan signal line GT1 and a second scan signal line GT2, and the number of transfer signal lines SW connected to the first scan signal line GT1 is equal to the number of transfer signal lines SW connected to the second scan signal line GT2. This ensures that the different scan signal lines GT are driven consistently, thereby improving display uniformity.

[0095] The first scanning signal line GT1 and the second scanning signal line GT2 may be any two different scanning signal lines GT.

[0096] In some embodiments, as shown in FIG6 , the plurality of transfer signal lines SW are divided into a plurality of transfer signal lines SW arranged along a first direction f1. Each transfer signal line group 40 includes one or multiple adjacent transfer signal lines SW. Transfer signal lines SW within the same transfer signal line group 40 are connected to the same scan signal terminal PING and the same scan signal line GT, while transfer signal lines SW within different transfer signal lines groups 40 are connected to different scan signal terminals PING and different scan signal lines GT. The scan signal terminal PING is located within the border area BA.

[0097] In some embodiments, as shown in Figure 4 or 5, the multiple scan signal lines GT include a third scan signal line GT3 and a fourth scan signal line GT4, and the same number of adapter wire groups 40 are arranged between two adjacent adapter wire groups 40 connected to the third scan signal line GT3, and between two adjacent adapter wire groups 40 connected to the fourth scan signal line GT4.

[0098] The third scanning signal line GT3 and the fourth scanning signal line GT4 may be any two different scanning signal lines GT.

[0099] For example, as shown in Figure a or Figure b in Figure 4, 11 adapter wire groups 40 are arranged between two adjacent adapter wire groups 40 connected to the third scan signal line GT3, and 11 adapter wire groups 40 are also arranged between two adjacent adapter wire groups 40 connected to the fourth scan signal line GT4.

[0100] For example, as shown in Figure a or Figure b in Figure 5, 7 adapter line groups 40 are arranged between two adjacent adapter line groups 40 connected to the third scan signal line GT3, and 7 adapter line groups 40 are also arranged between two adjacent adapter line groups 40 connected to the fourth scan signal line GT4.

[0101] In some embodiments, as shown in Figure 4, the multiple scan signal lines GT include a fifth scan signal line GT5 and a sixth scan signal line GT6, a first number of adapter wire groups 40 are arranged between two adjacent adapter wire groups 40 connected to the fifth scan signal line GT5, and a second number of adapter wire groups 40 are arranged between two adjacent adapter wire groups 40 connected to the sixth scan signal line GT6, and the first number is greater than or less than the second number.

[0102] The fifth scanning signal line GT5 and the sixth scanning signal line GT6 may be any two different scanning signal lines GT.

[0103] For example, as shown in Figure c in Figure 4, 22 adapter wire groups 40 are arranged between the two adjacent adapter wire groups 40 connected to the fifth scan signal line GT5, and 20 adapter wire groups 40 are also arranged between the two adjacent adapter wire groups 40 connected to the sixth scan signal line GT6, that is, the first number is 22 and the second number is 20, and the first number is greater than the second number.

[0104] Exemplarily, as shown in Figure d in Figure 4, there are 0 adapter wire groups 40 arranged between the two adjacent adapter wire groups 40 connected to the fifth scan signal line GT5, and there are also 2 adapter wire groups 40 arranged between the two adjacent adapter wire groups 40 connected to the sixth scan signal line GT6, that is, the first number is 0, the second number is 2, and the first number is less than the second number.

[0105] In some embodiments, as shown in Figure 4, the multiple scan signal lines GT also include a seventh scan signal line GT7, the sixth scan signal line GT6 is located between the fifth scan signal line GT5 and the seventh scan signal line GT7, and a third number of adapter wire groups 40 are arranged between the two adjacent adapter wire groups 40 connected to the seventh scan signal line GT7, wherein the first number, the second number and the third number increase or decrease successively.

[0106] Exemplarily, as shown in Figure c in Figure 4, 18 adapter wire groups 40 are arranged between two adjacent adapter wire groups 40 connected to the seventh scan signal line GT7, that is, the first number is 22, the second number is 20, and the third number is 18, and the first number, the second number and the third number decrease in sequence.

[0107] Exemplarily, as shown in Figure d in Figure 4, four adapter wire groups 40 are arranged between two adjacent adapter wire groups 40 connected to the seventh scan signal line GT7, that is, the first number is 0, the second number is 2, and the third number is 4, and the first number, the second number and the third number increase sequentially.

[0108] The fifth scanning signal line GT5 , the sixth scanning signal line GT6 , and the seventh scanning signal line GT7 may be any three different scanning signal lines GT.

[0109] In some embodiments, as shown in FIG5 , the plurality of adapter wire groups 40 include: a first adapter wire group 401, a second adapter wire group 402, and a third adapter wire group 403 connected to the same scan signal line GT and arranged sequentially along the first direction f1. The number of adapter wire groups 40 disposed between the first adapter wire group 401 and the second adapter wire group 402 is equal to the number of adapter wire groups 40 disposed between the second adapter wire group 402 and the third adapter wire group 403.

[0110] The first adapter wire group 401 , the second adapter wire group 402 , and the third adapter wire group 403 may be three adjacent adapter wire groups 40 among a plurality of adapter wire groups 40 connected to the same scan signal line GT.

[0111] 5 a or b, the number of adapter wire groups 40 arranged between the first adapter wire group 401 and the second adapter wire group 402 is 7, and the number of adapter wire groups 40 arranged between the second adapter wire group 402 and the third adapter wire group 403 is also 7.

[0112] In some embodiments, as shown in Figures c to e of Figure 5 , the plurality of scan signal lines GT include an eighth scan signal line GT8, and the plurality of patch cable groups 40 include: a fourth patch cable group 404, a fifth patch cable group 405, and a sixth patch cable group 406 connected to the eighth scan signal line GT8 and arranged sequentially along the first direction f1. A fourth number of patch cable groups 40 are disposed between the fourth patch cable group 404 and the fifth patch cable group 405, and a fifth number of patch cable groups 40 are disposed between the fifth patch cable group 405 and the sixth patch cable group 406, and the fourth number may be greater than or less than the fifth number.

[0113] The fourth adapter wire group 404 , the fifth adapter wire group 405 , and the sixth adapter wire group 406 may be three adjacent adapter wire groups 40 in sequence among the plurality of adapter wire groups 40 connected to the eighth scan signal line GT8 .

[0114] In some embodiments, as shown in Figures c to e of FIG5 , the plurality of scan signal lines GT further include a ninth scan signal line GT9, and the plurality of patch cable groups 40 include a seventh patch cable group 407, an eighth patch cable group 408, and a ninth patch cable group 409 connected to the ninth scan signal line GT9 and arranged sequentially along the first direction f1. A sixth number of patch cable groups 40 are disposed between the seventh patch cable group 407 and the eighth patch cable group 408, and a seventh number of patch cable groups 40 are disposed between the eighth patch cable group 408 and the ninth patch cable group 409. The fourth number is greater than the fifth number, and the sixth number is less than the seventh number; or the fourth number is less than the fifth number, and the sixth number is greater than the seventh number.

[0115] The eighth scanning signal line GT8 and the ninth scanning signal line GT9 may be any two different scanning signal lines GT.

[0116] The seventh adapter wire group 407 , the eighth adapter wire group 408 , and the ninth adapter wire group 409 may be three adjacent adapter wire groups 40 in sequence among the plurality of adapter wire groups 40 connected to the ninth scan signal line GT9 .

[0117] For example, as shown in Figure c in Figure 5, two patch cable groups 40 are provided between the fourth patch cable group 404 and the fifth patch cable group 405, and twelve patch cable groups 40 are provided between the fifth patch cable group 405 and the sixth patch cable group 406, i.e., the fourth number is 2, the fifth number is 12, and the fourth number is less than the fifth number. Twelve patch cable groups 40 are provided between the seventh patch cable group 407 and the eighth patch cable group 408, and two patch cable groups 40 are provided between the eighth patch cable group 408 and the ninth patch cable group 409, i.e., the sixth number is 12, the seventh number is 2, and the sixth number is greater than the seventh number.

[0118] For example, as shown in Figure 5 (d), 14 patch cable groups 40 are provided between the fourth patch cable group 404 and the fifth patch cable group 405, and 0 patch cable groups 40 are provided between the fifth patch cable group 405 and the sixth patch cable group 406, i.e., the fourth number is 14 and the fifth number is 0, and the fourth number is greater than the fifth number. 4 patch cable groups 40 are provided between the seventh patch cable group 407 and the eighth patch cable group 408, and 10 patch cable groups 40 are provided between the eighth patch cable group 408 and the ninth patch cable group 409, i.e., the sixth number is 4 and the seventh number is 10, and the sixth number is less than the seventh number.

[0119] For example, as shown in Figure e in Figure 5 , 12 patch cable groups 40 are provided between the fourth patch cable group 404 and the fifth patch cable group 405, and 7 patch cable groups 40 are provided between the fifth patch cable group 405 and the sixth patch cable group 406. That is, the fourth number is 12, the fifth number is 7, and the fourth number is greater than the fifth number. Two patch cable groups 40 are provided between the seventh patch cable group 407 and the eighth patch cable group 408, and 7 patch cable groups 40 are provided between the eighth patch cable group 408 and the ninth patch cable group 409. That is, the sixth number is 2, the seventh number is 7, and the sixth number is less than the seventh number.

[0120] In some embodiments, as shown in Figure c or d in Figure 4, the multiple adapter wire groups 40 include: a tenth adapter wire group 410 and an eleventh adapter wire group 411 connected to the same scanning signal line GT, the tenth adapter wire group 410 and the eleventh adapter wire group 411 are axially symmetrically arranged about the first axis 42, and the first axis 42 is the symmetry axis of the orthographic projection of the display area AA on the base substrate 11 extending along the second direction f2.

[0121] In some embodiments, as shown in FIG. 6 , the scan signal lines GT are connected to the transfer signal lines SW via transfer holes HT1 , and the transfer holes HT1 connecting all transfer signal lines SW in the same transfer line group 40 form a transfer hole group 41 .

[0122] In some embodiments, as shown in FIG. 4 or 5 , the plurality of adapter hole groups 41 are divided into a plurality of adapter units UT arranged along the first direction f1, each adapter unit UT includes the same number of plurality of adapter hole groups 41, the plurality of adapter units UT include a first adapter unit UT1 and a second adapter unit UT2, and the first adapter unit UT1 and the second adapter unit UT2 are translationally symmetric or axially symmetric.

[0123] For example, as shown in FIG. 4 a or FIG. 4 b , the first adapter unit UT1 and the second adapter unit UT2 are translationally symmetric, that is, the first adapter unit UT1 can be roughly overlapped with the second adapter unit UT2 by translation along the first direction f1.

[0124] For example, as shown in FIG. 4 c or d , the first adapter unit UT1 is axially symmetrical to the second adapter unit UT2 , and the axis of symmetry is, for example, the first axis 42 .

[0125] For example, as shown in FIG. 5 a or FIG. 5 b , the first adapter unit UT1 and the second adapter unit UT2 are translationally symmetric, that is, the first adapter unit UT1 can be roughly overlapped with the second adapter unit UT2 by translation along the first direction f1 .

[0126] Exemplarily, as shown in Figure a or b in Figure 5, the multiple adapter units UT also include a third adapter unit UT3, the second adapter unit UT2 is located between the first adapter unit UT1 and the third adapter unit UT3, and the first adapter unit UT1 and the second adapter unit UT2 are respectively translationally symmetrical with the third adapter unit UT3, that is, the first adapter unit UT1 can roughly coincide with the third adapter unit UT3 by translation along the first direction f1, and the second adapter unit UT2 can roughly coincide with the third adapter unit UT3 by translation along the first direction f1.

[0127] Exemplarily, as shown in FIG. 5 c, d or e, the first adapter unit UT1 is axially symmetrical to the second adapter unit UT2, and the axis of symmetry is along the second direction f2.

[0128] For example, as shown in Figure c or d in Figure 5 , the multiple adapter units UT further include a fourth adapter unit UT4. The second adapter unit UT2 is located between the first adapter unit UT1 and the fourth adapter unit UT4. The second adapter unit UT2 and the fourth adapter unit UT4 are axially symmetric, with the axis of symmetry along the second direction f2. The first adapter unit UT1 and the fourth adapter unit UT4 are translationally symmetric, that is, the first adapter unit UT1 can be substantially aligned with the fourth adapter unit UT4 when translated along the first direction f1.

[0129] For example, as shown in Figure 5e, the multiple adapter units UT further include a fifth adapter unit UT5. The second adapter unit UT2 is located between the first adapter unit UT1 and the fifth adapter unit UT5. The first adapter unit UT11 is axially symmetric with the fifth adapter unit UT5, with the axis of symmetry extending along the second direction f2. The second adapter unit UT2 is translationally symmetric with the fifth adapter unit UT5, meaning that the second adapter unit UT2 can be substantially aligned with the fifth adapter unit UT5 when translated along the first direction f1.

[0130] As shown in Figure 4 or Figure 5, in the orthographic projection on the base substrate 11, the arrangement shape of the multiple transfer hole groups 41 includes at least one of the following: V-shape (as shown in Figure c in Figure 4), inverted V-shape (as shown in Figure d in Figure 4), N-shape (as shown in Figure c in Figure 5), inverted N-shape (as shown in Figure 5 d), a bar extending along the third direction f3, and multiple bars extending along the third direction f3 and parallel to each other (as shown in Figures a and b in Figures 4 and 5), and the third direction f3 is respectively arranged to intersect with the first direction f1 and the second direction f2.

[0131] For example, as shown in FIG. 5 e , the arrangement shape of the plurality of transfer hole groups 41 is a combination of a V-shape and a strip shape extending along the third direction f3 .

[0132] For example, as shown in Figure e of FIG4 , in a display substrate for an in-vehicle display, a plurality of transfer hole groups 41 are arranged in a V-shape, with the openings of the V-shape facing the long side of the display substrate.

[0133] When the arrangement shape of the plurality of transfer hole groups 41 is a plurality of bars extending along the third direction f3 and parallel to each other, the driving capabilities of the plurality of scanning signal lines GT are more uniform, and the charging difference between different scanning signal lines GT is small.

[0134] For example, in Figures a and b in Figure 4 , the arrangement shape of the multiple adapter hole groups 41 is two bars extending along the third direction f3 and parallel to each other, such as a / / shape and a \\ shape; in Figures a and b in Figure 5 , the arrangement shape of the multiple adapter hole groups 41 is three bars extending along the third direction f3 and parallel to each other, such as a \\\ shape and a / / / shape.

[0135] In a specific implementation, each scanning signal line GT can be connected to the transfer signal lines SW in N transfer line groups 40 to achieve N-point driving, where N is a positive integer. Multi-point driving can better improve the driving capability of the scanning signal line GT and reduce signal delay. The larger the N value, the stronger the driving capability of the scanning signal line GT.

[0136] For example, as shown in FIG4 , N=2, meaning each scan signal line GT is connected to two adapter wire groups 40 at different locations, achieving two-point drive. In this example, the multiple adapter hole groups 41 can be arranged in a V-shape, an inverted V-shape, or two parallel strips extending along the third direction f3, such as a / / shape or a \\ shape.

[0137] In the case of multiple transfer hole groups 41 arranged in a V-shape or inverted V-shape, the distance between two transfer line groups 40 near the vertex is relatively close, and the scan signal lines GT connected to the two transfer line groups 40 near the vertex are driven approximately at a single point. In contrast, in the case of multiple transfer hole groups 41 arranged in a / / or \\ shape, the driving capabilities of different scan signal lines GT are relatively uniform, and the charging differences between different scan signal lines GT are small.

[0138] For example, as shown in FIG5 , N=3, meaning each scanning signal line GT can be connected to a transfer signal line SW within three transfer line groups 40 to implement three-point drive. In this example, the multiple transfer hole groups 41 can be arranged in an N-shape, an inverted N-shape, or three parallel strips extending along the third direction f3, such as a \\\ shape or a / / / shape. Alternatively, a V-shape or a combination of an inverted V-shape and strips extending along the third direction f3, such as a \ / / shape, can be provided.

[0139] Specifically, in the case of multiple transfer hole groups 41 arranged in an N-shape, inverted N-shape, and / / / -shape, the distance between two transfer line groups 40 at adjacent vertices is relatively close, and the scan signal lines GT connected to the two transfer line groups 40 at adjacent vertices are approximately driven at a single point. In contrast, in the case of multiple transfer hole groups 41 arranged in a \\\-shape or / / / -shape, the driving capabilities of different scan signal lines GT are relatively more uniform, and the charging differences between different scan signal lines GT are small.

[0140] In some embodiments, the number of transfer signal lines SW included in the transfer line group 40 is M or M+1, where M is a positive integer obtained by rounding down m*3 / (2N*2n), m is the row resolution of the display area AA, n is the column resolution of the display area AA, and N is the number of transfer line groups 40 connected to the same scanning signal line GT.

[0141] In this embodiment, m is the number of sub-pixel rows included in the display area AA, and n is the number of sub-pixel columns included in the display area AA. The same pixel unit may include multiple sub-pixels of different colors arranged along the column direction, such as red sub-pixels, green sub-pixels, and blue sub-pixels.

[0142] For example, if m*3 / (2N*2n) is divisible, then M=m*3 / (2N*2n). If m*3 / (2N*2n) is not divisible, then M is a positive integer obtained by rounding down m*3 / (2N*2n). In this case, the number of transfer signal lines SW included in some patch cable assemblies 40 is M, and the number of transfer signal lines SW included in other patch cable assemblies 40 is M+1.

[0143] For example, the resolution of the display substrate is 8800*1092, that is, m=8800, n=1092, and the two-point drive is N=2. M=3 is calculated according to m*3 / (2N*2n). Therefore, the number of transfer signal lines SW included in the transfer wire group 40 is 3 or 4, that is, the number of transfer signal lines SW included in part of the transfer wire group 40 is 3 (as shown in Figure 6), and the number of transfer signal lines SW included in the other part of the transfer wire group 40 is 4.

[0144] In some embodiments, the difference in the number of transfer signal wires SW included in different transfer wire groups 40 is less than or equal to 1.

[0145] Exemplarily, different patch cable groups 40 include the same number of patch signal wires SW. In this case, the difference in the number of patch signal wires SW included in different patch cable groups 40 is equal to 0.

[0146] Exemplarily, different patch cable groups 40 include different numbers of patch cable SW. For example, one patch cable group 40 includes M number of patch cable SW, while another patch cable group 40 includes M+1 number of patch cable SW. In this case, the difference in the number of patch cable SW included in the different patch cable groups 40 is 1.

[0147] In some embodiments, the number of adapter wire groups 40 connected to different scan signal lines GT is the same. For example, each scan signal line GT is connected to N adapter wire groups 40 .

[0148] In some embodiments, as shown in FIG. 6 , the data signal lines DT and the switching signal lines SW are alternately arranged in sequence in the first direction f1 .

[0149] 6 , the display area AA includes a plurality of sub-pixels P1 arrayed in rows and columns, where the row direction is a first direction f1 and the column direction is a second direction f2. Each sub-pixel P1 includes, for example, a thin film transistor.

[0150] In some embodiments, as shown in FIG. 2 or FIG. 3 , the plurality of scan signal lines GT include a tenth scan signal line GT10 and an eleventh scan signal line GT11 located on either side of the same sub-pixel row RW. The tenth scan signal line GT10 is connected to odd-numbered sub-pixel columns in the same sub-pixel row RW, and the eleventh scan signal line GT11 is connected to even-numbered sub-pixel columns in the same sub-pixel row RW. This allows for dual-gate driving, i.e., each sub-pixel row RW is driven by two scan signal lines GT, thereby reducing the number of data signal lines DT.

[0151] Furthermore, as shown in FIG. 2 or FIG. 3 , the data signal lines DT and the switching signal lines SW are alternately arranged between two adjacent sub-pixel columns. One of the data signal lines DT and the switching signal lines SW is provided between two adjacent sub-pixel columns, and the data signal line DT is connected to two adjacent sub-pixel columns located on both sides of the data signal line DT.

[0152] Exemplarily, as shown in FIG. 2 or FIG. 3 , for each sub-pixel column, the data signal line DT and the switching signal line SW are located on different sides of the sub-pixel column.

[0153] For example, as shown in FIG6 , the display area AA includes a first subpixel column cl1, a second subpixel column cl2, a third subpixel column cl3, ..., and an nth subpixel column cln, arranged sequentially along a first direction f1. The data signal line DT is located between the first subpixel column cl1 and the second subpixel column cl2, between the third subpixel column cl3 ​​and the fourth subpixel column cl4, ..., and between the n-1th subpixel column cln-1 and the nth subpixel column cln. The switching signal line SW is located between the second subpixel column cl2 and the third subpixel column cl3, between the fourth subpixel column cl4 and the fifth subpixel column cl5, ..., and between the n-2th subpixel column cln-2 and the n-1th subpixel column cln-1.

[0154] For example, as shown in FIG6 , a first edge transfer line 61 is provided on the side of the first subpixel column cl1 facing away from the second subpixel column cl2. The connection between this first edge transfer line 61 and the scan signal line GT is identical to the connection between the adjacent transfer signal line SW (i.e., the transfer signal line SW located between the second subpixel column cl2 and the third subpixel column cl3) and the scan signal line GT. Similarly, a second edge transfer line 62 is provided on the side of the nth subpixel column cln facing away from the n-1th subpixel column cln-1. The connection between this second edge transfer line 62 and the scan signal line GT is identical to the connection between the adjacent transfer signal line SW (i.e., the transfer signal line SW located between the n-2th subpixel column cln-2 and the n-1th subpixel column cln-1) and the scan signal line GT. This improves consistency between subpixel columns and prevents poor image quality caused by different pulls from the scan signal between subpixels P1 near the edge and those located in the middle.

[0155] For example, the scan signal line GT is used to transmit a scan signal, which is used to control the on / off state of the thin-film transistor within the sub-pixel P1. Therefore, the voltage of the scan signal is related to characteristics such as the turn-on voltage of the thin-film transistor. The turn-on voltage of the thin-film transistor can be, for example, 17V, 18V, 20V, 30V, or 35V, and can be determined based on actual needs.

[0156] For example, each switching signal line SW in the display area AA is connected to and only connected to one scanning signal line GT. In this way, the consistency of the environment on both sides of each sub-pixel P1 in the display panel can be ensured.

[0157] In specific implementation, the scanning signal is a pulse waveform, and the pulse amplitude is the turn-on voltage VGH or the turn-off voltage VGL. Since the voltage value of the turn-on voltage VGH or the turn-off voltage VGL is relatively large, the electric field formed therein may affect the deflection of the liquid crystal, thereby causing defects such as light leakage.

[0158] To improve light leakage, in some embodiments, as shown in FIG. 7 or FIG. 8 b or d, the scan signal line GT is located between the transfer signal line SW and the base substrate 11. The display area AA further includes a common electrode layer 71 located on a side of the transfer signal line SW facing away from the base substrate 11 and including a plurality of common electrodes COM. In an orthographic projection onto the base substrate 11, the common electrode layer 71 covers the transfer signal line SW at least in the first direction f1.

[0159] In this embodiment, the common electrode layer 71 is used to transmit a voltage-stabilized signal. By setting the common electrode layer 71 on the side of the transfer signal line SW away from the base substrate 11, and the common electrode layer 71 covers the transfer signal line SW at least in the first direction f1, the common electrode layer 71 can shield the electric field formed by the scanning signal, reduce the impact on the deflection of the liquid crystal, and thus improve poor light leakage.

[0160] In some embodiments, as shown in FIG. 7 or FIG. 8 b, the scan signal lines GT are located between the switching signal lines SW and the base substrate 11. As shown in FIG. 2 or FIG. 3, the display area AA further includes: a plurality of touch signal lines TC extending along the second direction f2. As shown in FIG. 7 c, FIG. 8 c, or FIG. 8 e, the touch signal lines TC are located on the side of the data signal lines DT facing away from the base substrate 11. In an orthographic projection onto the base substrate 11, the touch signal lines TC overlap the data signal lines DT at least in the first direction f1.

[0161] In this embodiment, the touch signal line TC is provided on the side of the data signal line DT away from the base substrate 11 , and the touch signal line TC covers the data signal line DT at least in the first direction f1 , thereby reducing the influence of the touch signal line TC on the aperture ratio.

[0162] In some embodiments, as shown in Figure 7 or Figure c in Figure 8, the display area AA further includes: a common electrode layer 71, located between the data signal line DT and the touch signal line TC (as shown in Figure c in Figure 8), or located on the side of the touch signal line TC away from the base substrate 11 (as shown in Figure c in Figure 7).

[0163] As shown in FIG9 , the common electrode layer 71 includes a plurality of touch blocks 91 separated from each other. Each touch block 91 includes a plurality of interconnected common electrodes COM. As shown in FIG10 , a touch block 91 is connected to a touch signal line TC (as shown in the left figure of FIG10 ), or to multiple adjacent touch signal lines TC (as shown in the right figure of FIG10 ), via a touch hole HL2. As shown in the right figure of FIG10 , multiple touch signal lines TC connected to the same touch block 91 are connected to the same touch signal terminal PINT, while touch signal lines TC connected to different touch blocks 91 are connected to different touch signal terminals PINT.

[0164] In this embodiment, since the touch signal line TC is connected to the common electrode layer 71 and the common electrode layer 71 is used to transmit a voltage-stabilized signal, the touch signal line TC can also function to shield the data signal.

[0165] In some embodiments, as shown in Figure c of Figure 8 , the common electrode layer 71 is located between the data signal line DT and the touch signal line TC, and the display area AA further includes: a first pixel electrode layer 81 located on the side of the touch signal line TC away from the base substrate 11.

[0166] As shown in Figure 11, the first pixel electrode layer 81 includes a plurality of first pixel electrodes PX1 separated from each other, and a switching electrode 82 separated from the first pixel electrodes PX1. The plurality of first pixel electrodes PX1 may be located in different sub-pixels P1.

[0167] In FIG11 , the left figure shows a schematic planar structural diagram of the first pixel electrode layer 81 , and the right figure shows a partial enlarged view of the display substrate at the position of the dotted circle 3 shown in FIG3 .

[0168] For example, as shown in FIG8 , the display area AA includes: a base substrate 11, a first metal layer M1, a first active layer ACT1, a first insulating layer GI1, a second metal layer M2, a second insulating layer PVX1, a first organic insulating film layer ORG1, a common electrode layer 71, a third insulating layer PVX2, a third metal layer M3, a fourth insulating layer PVX3, and a first pixel electrode layer 81, which are stacked in sequence. The first metal layer M1 includes scan signal lines GT, the second metal layer M2 includes data signal lines DT, transfer signal lines SW, and source and drain electrodes SD of thin film transistors, and the third metal layer M3 includes touch signal lines TC.

[0169] Exemplarily, the common electrode layer 71 and the first pixel electrode layer 81 are made of transparent conductive materials such as indium tin oxide.

[0170] FIG3 is a circuit layout diagram of the display substrate shown in FIG8. In FIG8, FIGa shows a schematic cross-sectional structure diagram of the display substrate shown in FIG3 at the position of dotted circle 1, FIGb shows a schematic cross-sectional structure diagram of the display substrate shown in FIG3 at the position of dotted circle 2, FIGc shows a schematic cross-sectional structure diagram of the display substrate shown in FIG3 at the position of dotted circle 3, FIGd shows a schematic cross-sectional structure diagram of the display substrate shown in FIG3 at the position of dotted line 4, and FIGe shows a schematic cross-sectional structure diagram of the display substrate shown in FIG3 at the position of dotted line 5.

[0171] As shown in Figure a in Figure 8, in the same sub-pixel P1, the first pixel electrode PX1 is connected to the source and drain electrodes SD of the thin film transistor through a first via hole H1 provided on the fourth insulating layer PVX3, the third insulating layer PVX2 and the second insulating layer PVX1. The first via hole H1 forms a sleeve hole with the second via hole H2 provided on the first organic insulating film layer ORG1, and the hole wall of the second via hole H2 is located on the periphery of the first via hole H1.

[0172] As shown in FIG. 8 b , the switching signal line SW is connected to the scanning signal line GT through a switching hole HT1 provided on the first insulating layer GI1 .

[0173] As shown in Figure 8(c), the touch hole HL2 includes a half hole 83 and a first through hole 84. The transfer electrode 82 is connected to the touch signal line TC through the half hole 83, and the transfer electrode 82 is connected to the touch block 91 through the first through hole 84. In this way, the transfer electrode 82 is connected to the touch signal line TC and the touch block 91 respectively, thereby connecting the touch signal line TC to the touch block 91.

[0174] For example, in order to prevent the touch signal line TC from being oxidized, the transfer electrode 82 may completely cover the touch signal line TC exposed in the half hole 83 .

[0175] Referring to the right figure in Figure 12, a flow chart of a preparation method of the display substrate shown in Figures 3 and 8 is shown. The display substrate is prepared using a 9-time patterning process. In the right figure in Figure 12, the second insulating layer PVX1, the third insulating layer PVX2 and the fourth insulating layer PVX3 can be prepared simultaneously using a single patterning process, and the remaining film layers each use a corresponding patterning process.

[0176] During the etching process of the first organic insulating film layer ORG1, parameters can be adjusted to prevent the second insulating layer PVX1 from being etched. This ensures that the second insulating layer PVX1 protects the first metal layer M1 and the second metal layer M2 at the location where the first organic insulating film layer ORG1 is removed, thereby improving the corrosion resistance of the surrounding metals. After etching the first organic insulating film layer ORG1, a single patterning process can be used to form the second insulating layer PVX1, the third insulating layer PVX2, and the fourth insulating layer PVX3.

[0177] In the present disclosure, the patterning process may include, for example, one or more steps of film formation, exposure, development, and etching, and the present disclosure does not limit this.

[0178] In some embodiments, as shown in FIG. 7 c , the common electrode layer 71 is located on a side of the touch signal line TC away from the base substrate 11 , and the touch block 91 is connected to the touch signal line TC through the touch hole HL2 .

[0179] For example, as shown in FIG7 , the display substrate includes: a base substrate 11, a fourth metal layer M4, a second active layer ACT2, a fifth insulating layer GI2, a fifth metal layer M5, a sixth insulating layer PVX6, a second organic insulating film layer ORG2, a second pixel electrode layer 72, a seventh insulating layer PVX7, a sixth metal layer M6, an eighth insulating layer PVX8, and a common electrode layer 71, which are stacked in sequence. The fourth metal layer M4 includes scan signal lines GT, the fifth metal layer M5 includes data signal lines DT, transfer signal lines SW, and source and drain electrodes SD of thin film transistors, and the sixth metal layer M6 includes touch signal lines TC.

[0180] In this embodiment, the second pixel electrode layer 72 includes a plurality of second pixel electrodes PX2 located in different sub-pixels P1.

[0181] Exemplarily, the common electrode layer 71 and the second pixel electrode layer 72 are made of transparent conductive materials such as indium tin oxide.

[0182] FIG2 shows a circuit layout diagram of the display substrate shown in FIG7 . In FIG7 , FIGa shows a schematic cross-sectional structural diagram of the display substrate shown in FIG2 at the position of dotted circle 1, FIGb shows a schematic cross-sectional structural diagram of the display substrate shown in FIG2 at the position of dotted circle 2, FIGc shows a schematic cross-sectional structural diagram of the display substrate shown in FIG2 at the position of dotted circle 3, and FIGd shows a schematic cross-sectional structural diagram of the display substrate shown in FIG2 at the position of dotted line 4.

[0183] As shown in Figure 7a, within the same sub-pixel P1, the second pixel electrode PX2 is connected to the source and drain electrodes SD of the thin-film transistor through vias provided in the second organic insulating film layer ORG2 and the sixth insulating layer PVX6. The vias provided in the second organic insulating film layer ORG2 and the sixth insulating layer PVX6 can be formed simultaneously using a single patterning process. Because the vias connecting the second pixel electrode PX2 and the source and drain electrodes SD of the thin-film transistor pass through a thin film thickness, smaller via diameters can be fabricated, thereby improving the aperture ratio.

[0184] As shown in FIG. 7 b , the switching signal line SW is connected to the scanning signal line GT through a switching hole HT1 provided on the fifth insulating layer GI2 .

[0185] As shown in FIG. 7 c , the touch block 91 is connected to the touch signal line TC via a touch hole HL2 provided on the eighth insulating layer PVX8 .

[0186] Referring to the left figure in Figure 12, a flow chart of a method for preparing the display substrate shown in Figures 2 and 7 is shown. The display substrate is prepared using a 9-time patterning process. In the left figure in Figure 12, the seventh insulating layer PVX7 and the eighth insulating layer PVX8 can be simultaneously prepared using a single patterning process, the sixth insulating layer PVX6 and the second organic insulating film layer ORG2 can be simultaneously prepared using a single patterning process, and the remaining film layers each correspond to a single patterning process.

[0187] In some embodiments, as shown in FIG9 , a plurality of touch blocks 91 are arranged in an array along a first direction f1 and a second direction f2. The plurality of touch blocks 91 are divided into a plurality of touch regions 93 arranged along the first direction f1. The touch region 93 includes one or multiple adjacent columns of touch blocks 91. The plurality of touch regions 93 include a first touch region 931 and a second touch region 932. The plurality of touch holes HL2 located in the first touch region 931 are axially symmetrical or translationally symmetrical with the plurality of touch holes HL2 located in the second touch region 932.

[0188] 9 and 10 , the touch unit 92 includes a plurality of touch holes HL2 connected to the same touch block 91. The touch units 92 connected to different touch blocks 91 have the same number of touch holes HL2, and the arrangement of the touch holes HL2 is the same.

[0189] The multiple touch holes HL2 located in the first touch area 931 and the multiple touch holes HL2 located in the second touch area 932 are translationally symmetric, which means that the multiple touch holes HL2 located in the first touch area 931 can be roughly overlapped with the multiple touch holes HL2 located in the second touch area 932 when translated along the first direction f1.

[0190] For example, as shown in Figure 9a, a touch area 93 includes a column of touch blocks 91. The multiple touch holes HL2 located in the first touch area 931 are translationally symmetrical with the multiple touch holes HL2 located in the second touch area 932. The first touch area 931 and the second touch area 932 can be any two touch areas 93.

[0191] For example, as shown in FIG. 9(b), a touch area 93 includes four columns of touch blocks 91. The multiple touch holes HL2 located in the first touch area 931 are axially symmetric with the multiple touch holes HL2 located in the second touch area 932. The symmetry axis o1 can be, for example, an axis of symmetry extending along the second direction f2 of the orthographic projection of the display area AA on the base substrate 11. In this example, within the same touch area 93, the touch holes HL2 located in different columns of touch blocks 91 can be translationally symmetric.

[0192] For example, as shown in Figure 9(c), a touch region 93 includes four columns of touch blocks 91. The multiple touch holes HL2 located in the first touch region 931 are translationally symmetrical with the multiple touch holes HL2 located in the second touch region 932. In this example, the four columns of touch blocks 91 in the same touch region 93 can be arranged axially symmetrically, with the symmetry axis o2 being the symmetry axis extending along the second direction f2 of the orthographic projection of the touch region 93 on the substrate 11.

[0193] For example, as shown in FIG10 , a touch signal line TC may be connected to a touch block 91 through a plurality of touch holes HL2 , and these touch holes HL2 are evenly distributed in the second direction f2 , for example, a touch hole HL2 may be provided for every four sub-pixels P1 .

[0194] For example, as shown in FIG10 , the number of touch holes HL2 connected to each touch block 91 is a preset number, which may be greater than or equal to 5 and less than or equal to 20. In FIG10 , the preset number is 10. When the same touch block 91 is connected to two adjacent touch signal lines TC, the number of touch holes HL2 provided on each touch signal line TC is half of the preset number.

[0195] In some embodiments, as shown in FIG13 , the border area BA includes: touch signal terminals PINT, disposed on the same layer as and interconnected with touch signal lines TC, for providing touch signals to the touch signal lines TC; and data signal terminals PIND, disposed on the same layer as and interconnected with data signal lines DT, for providing data signals to the data signal lines DT. The touch signal terminals PINT are located between multiple data signal terminals PIND, and both the touch signal terminals PINT and the data signal terminals PIND are used to bind to a source driver chip Source IC.

[0196] In some embodiments, as shown in Figures 13 and 14, the border area BA includes: a scan signal terminal PING, which is provided on the same layer as the scan signal line GT and is connected to the transfer signal line SW via a via hole, and is used to provide a scan signal to the transfer signal line SW and the scan signal line GT; and a data signal terminal PIND, which is provided on the same layer as the data signal line DT and is connected to each other, and is used to provide a data signal to the data signal line DT. The scan signal terminal PING and the data signal terminal PIND are located on the same side of the display area AA.

[0197] Exemplarily, the scan signal terminal PING, the data signal terminal PIND, and the touch signal terminal PINT are respectively located in different metal layers. These three metal layers can be wired independently. Since an insulating layer is provided between different metal layers, the lines can overlap or cross in the orthographic projection on the base substrate 11, which is beneficial to save wiring space and reduce the frame size.

[0198] Exemplarily, as shown in FIG15 , the scan signal terminal PING (located below the gate driver chip Gate IC in FIG15 ) is connected to the transfer signal line SW via a first lead 151 , and the first lead 151 may be provided on the same layer as the scan signal line GT.

[0199] As shown in FIG16 , multiple transfer signal lines SW in the same transfer line group 40 extend to the frame area BA, are short-circuited together by the short-circuit pattern 161, and then connected to the scan signal terminal PING through the first lead 151. The short-circuit pattern 161 is provided on the same layer as the scan signal line GT.

[0200] Exemplarily, as shown in FIG15 , the data signal terminal PIND (located below the source driver chip Source IC in FIG15 ) is connected to the data signal line DT via a second lead 152 , and the second lead 152 is provided on the same layer as the data signal line DT.

[0201] For example, as shown in FIG15 , the touch signal terminal PINT (located below the source driver chip Source IC in FIG15 ) is connected to the touch signal line TC via a third lead 153 , and the third lead 153 can be provided on the same layer as the touch signal line TC.

[0202] For example, as shown in FIG. 15 and FIG. 17 , the first lead 151 , the second lead 152 , and the third lead 153 may be mixedly wired, and any two of them may overlap or cross each other, which is not limited in the present disclosure.

[0203] In Figure 17, Figure a, Figure b and Figure c are structural diagrams of three different positions within the border area BA. In Figure a, Figure b or Figure c, the left figure is a planar circuit layout diagram, and the right figure is a cross-sectional structural diagram.

[0204] For example, the scan signal terminal PING may be an output port of a gate driver chip Gate IC, or an output port of a gate driver circuit. For example, the gate driver circuit may include multiple shift registers connected in cascade, and the scan signal terminal PING may be an output port of a shift register.

[0205] In some embodiments, as shown in FIG18 , a plurality of scan signal terminals PING are divided into one or more scan signal binding areas G, and the scan signal binding area G is used to bind the gate driver chip Gate IC; a plurality of data signal terminals PIND are divided into a plurality of data signal binding areas S, and the data signal binding area S is used to bind the source driver chip Source IC; wherein, the scan signal binding area G is arranged between two adjacent data signal binding areas S, and at most one scan signal binding area G is arranged between two adjacent data signal binding areas S, and at most two data signal binding areas S are arranged between two adjacent scan signal binding areas G.

[0206] In this way, by distributing the scan signal binding areas G between the data signal binding areas S, it is beneficial to reduce the routing length of the first lead 151, save the wiring space of the first lead 151, and help reduce the frame size.

[0207] 18 , the plurality of scan signal terminals PING are divided into six scan signal binding areas G, namely scan signal binding areas G-1 to G-6, and the plurality of data signal terminals PIND are divided into ten data signal binding areas S, namely data signal binding areas S-1 to S-10.

[0208] For example, as shown in FIG. 18 , a plurality of data signal binding areas S may be evenly distributed within the border area BA along the first direction f1 , which is beneficial for reducing the routing length of the second lead 152 and saving wiring space.

[0209] Exemplarily, the touch signal terminal PINT is located in the data signal binding area S and between the plurality of data signal terminals PIND.

[0210] In some embodiments, as shown in Figure 18, multiple data signal binding areas S include a first data signal binding area S-10 and a second data signal binding area S-9, and the first data signal binding area S-10 and the second data signal binding area S-9 are arranged close to the first edge b1 (as shown in Figure 18) or the second edge b2, and the first edge b1 and the second edge b2 are two opposite edges of the display substrate in the first direction f1.

[0211] For example, as shown in Figure a in Figure 18, no scanning signal binding area G is set between the first data signal binding area S-10 and the second data signal binding area S-9. The longest first lead 151 needs to be from c to d, which is longer in length. The first lead 151 requires a larger wiring space.

[0212] For example, as shown in FIG. 18 b or FIG. 18 c, a scan signal binding area G is provided between the first data signal binding area S-10 and the second data signal binding area S-9. Thus, by providing the scan signal binding area G between the first data signal binding area S-10 and the second data signal binding area S-9, the longest first lead 151 only needs to run from a to b, and its length is shorter, thereby saving wiring space for the first lead 151.

[0213] Compared with the wiring method shown in Figure 18a, the wiring methods shown in Figures 18b and c can save 0.9mm of frame size.

[0214] The present disclosure provides a display panel including: a cell substrate, a liquid crystal layer, and a display substrate as provided in any embodiment, wherein the liquid crystal layer is located between the cell substrate and the display substrate, and a display area AA is disposed close to the liquid crystal layer.

[0215] Those skilled in the art will appreciate that the display panel provided by the present disclosure has the advantages of the above-mentioned display substrate.

[0216] The present disclosure provides a display device, including: a display substrate as provided in any embodiment; a source driver chip Source IC, bound and connected to the border area BA, for providing a data signal to the data signal line DT; and one of the following: a gate driver chip Gate IC, bound and connected to the border area BA, located on the same side of the display area AA as the source driver chip Source IC, for providing a scan signal to the transfer signal line SW and the scan signal line GT; a gate driver circuit, located in the border area BA, located on the same side of the display area AA as the source driver chip Source IC, for providing a scan signal to the transfer signal line SW and the scan signal line GT.

[0217] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the above-mentioned display substrate.

[0218] The display device provided by the present disclosure can be: a display module, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a car display device, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.

[0219] Exemplarily, the output ports of the source driver chip Source IC include: a data signal port for outputting a data signal, and a touch signal port for outputting a touch signal.

[0220] Exemplarily, the output port of the gate driving chip Gate IC includes: a scan signal port for outputting a scan signal.

[0221] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0222] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

[0223] As used herein, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0224] References herein to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0225] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0226] When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0227] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0228] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0229] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0230] The use of "for" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0231] The use of "based on" or "according to" in this document is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values.

[0232] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0233] As used herein, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute equality and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.

[0234] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0235] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0236] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display substrate, comprising a base substrate, and a display area and a frame area located on one side of the base substrate, wherein the display area comprises: A plurality of scanning signal lines extending along a first direction, a plurality of switching signal lines extending along a second direction, and a plurality of data signal lines extending along the second direction, the first direction and the second direction intersecting each other; Among them, the scanning signal line and the data signal line are arranged in different layers, the scanning signal line and the switching signal line are arranged in different layers, the data signal line and the switching signal line are arranged in the same layer, the scanning signal line is connected to at least one switching signal line, and different scanning signal lines are connected to different switching signal lines.

2. The display substrate according to claim 1, wherein: The plurality of scan signal lines include a first scan signal line and a second scan signal line, and the number of transfer signal lines connected to the first scan signal line is equal to the number of transfer signal lines connected to the second scan signal line.

3. The display substrate according to claim 1 or 2, wherein: The plurality of transfer signal lines are divided into a plurality of transfer line groups arranged along a first direction, and the transfer line group includes one or a plurality of adjacent transfer signal lines; and The transfer signal lines in the same transfer line group are connected to the same scan signal terminal and the same scan signal line, and the transfer signal lines in different transfer line groups are connected to different scan signal terminals and different scan signal lines.

4. The display substrate according to claim 3, wherein: The plurality of scan signal lines include a third scan signal line and a fourth scan signal line, and the same number of adapter line groups are arranged between two adapter line groups adjacent to the third scan signal line and between two adapter line groups adjacent to the fourth scan signal line.

5. The display substrate according to claim 3, wherein: The multiple scan signal lines include a fifth scan signal line and a sixth scan signal line, a first number of adapter line groups are arranged between two adapter line groups connected to and adjacent to the fifth scan signal line, and a second number of adapter line groups are arranged between two adapter line groups connected to and adjacent to the sixth scan signal line, and the first number is greater than or less than the second number.

6. The display substrate according to claim 5, wherein: The plurality of scan signal lines further include a seventh scan signal line, the sixth scan signal line is located between the fifth scan signal line and the seventh scan signal line, and a third number of adapter line groups are arranged between two adapter line groups connected to and adjacent to the seventh scan signal line; The first number, the second number and the third number increase or decrease sequentially.

7. The display substrate according to any one of claims 3 to 6, wherein: The plurality of adapter wire groups include: a first adapter wire group, a second adapter wire group, and a third adapter wire group connected to the same scan signal line and arranged in sequence along a first direction; The number of patch cord groups arranged between the first patch cord group and the second patch cord group is equal to the number of patch cord groups arranged between the second patch cord group and the third patch cord group.

8. The display substrate according to any one of claims 3 to 6, wherein: The plurality of scanning signal lines include an eighth scanning signal line, and the plurality of adapter wire groups include: a fourth adapter wire group, a fifth adapter wire group, and a sixth adapter wire group connected to the eighth scanning signal line and arranged in sequence along the first direction; A fourth number of patch cord groups are arranged between the fourth patch cord group and the fifth patch cord group, a fifth number of patch cord groups are arranged between the fifth patch cord group and the sixth patch cord group, and the fourth number is greater than or less than the fifth number.

9. The display substrate according to claim 8, wherein: The plurality of scanning signal lines further include a ninth scanning signal line, and the plurality of adapter wire groups further include: a seventh adapter wire group, an eighth adapter wire group, and a ninth adapter wire group connected to the ninth scanning signal line and arranged in sequence along the first direction; A sixth number of patch cord groups are provided between the seventh patch cord group and the eighth patch cord group, and a seventh number of patch cord groups are provided between the eighth patch cord group and the ninth patch cord group; The fourth number is greater than the fifth number, and the sixth number is smaller than the seventh number, or the fourth number is smaller than the fifth number, and the sixth number is greater than the seventh number.

10. The display substrate according to any one of claims 3 to 9, wherein: The multiple adapter wire groups include: a tenth adapter wire group and an eleventh adapter wire group connected to the same scanning signal line, the tenth adapter wire group and the eleventh adapter wire group are axially symmetrically arranged about a first axis, and the first axis is a symmetry axis extending along a second direction of an orthographic projection of the display area on the base substrate.

11. The display substrate according to any one of claims 3 to 10, wherein: The scanning signal line is connected to the transfer signal line through a transfer hole, and the transfer holes connecting all the transfer signal lines in the same transfer line group constitute a transfer hole group; In the orthographic projection on the base substrate, the arrangement shapes of the multiple adapter hole groups include at least one of the following: V-shape, inverted V-shape, N-shape, inverted N-shape, a bar extending along a third direction, and a plurality of bars extending along a third direction and parallel to each other, and the third direction is respectively arranged to intersect with the first direction and the second direction.

12. The display substrate according to any one of claims 3 to 11, wherein: The number of transfer signal lines included in the transfer line group is M or M+1, where M is a positive integer obtained by rounding down m*3 / (2N*2n), m is a row resolution of the display area, n is a column resolution of the display area, and N is the number of transfer line groups connected to the same scan signal line; and / or The difference in the number of transfer signal lines included in different transfer line groups is less than or equal to 1; and / or The number of adapter cable groups connected to different scan signal lines is the same.

13. The display substrate according to any one of claims 3 to 12, wherein: The scanning signal line is connected to the transfer signal line through a transfer hole, and the transfer holes connecting all the transfer signal lines in the same transfer line group constitute a transfer hole group; The multiple adapter hole groups are divided into multiple adapter units arranged along the first direction, each of the adapter units includes the same number of multiple adapter hole groups, the multiple adapter units include a first adapter unit and a second adapter unit, and the first adapter unit is translationally symmetric or axially symmetric with the second adapter unit.

14. The display substrate according to any one of claims 1 to 13, wherein: The display area includes a plurality of sub-pixels arranged in an array along a row direction and a column direction, the row direction is a first direction, and the column direction is a second direction; The plurality of scanning signal lines include: a tenth scanning signal line and an eleventh scanning signal line located on both sides of the same sub-pixel row, the tenth scanning signal line is connected to the sub-pixels in odd columns in the same sub-pixel row, and the eleventh scanning signal line is connected to the sub-pixels in even columns in the same sub-pixel row; The data signal lines and the switching signal lines are alternately arranged between two adjacent columns of sub-pixels. One of the data signal lines and the switching signal lines is arranged between two adjacent columns of sub-pixels. The data signal line is connected to two adjacent columns of sub-pixels located on both sides of the data signal line.

15. The display substrate according to any one of claims 1 to 14, wherein: The scanning signal line is located between the switching signal line and the base substrate, and the display area further includes: A common electrode layer, located on a side of the transfer signal line away from the base substrate, comprising a plurality of common electrodes; Wherein, in the orthographic projection on the base substrate, the common electrode layer covers the switching signal line at least in the first direction.

16. The display substrate according to any one of claims 1 to 15, wherein: The scanning signal line is located between the switching signal line and the base substrate, and the display area further includes: A plurality of touch signal lines extend along the second direction, the touch signal lines are located on a side of the data signal lines away from the base substrate, and in an orthographic projection on the base substrate, the touch signal lines at least cover the data signal lines in the first direction.

17. The display substrate according to claim 16, wherein: The display area also includes: A common electrode layer, located between the data signal line and the touch signal line, or located on a side of the touch signal line away from the base substrate, including a plurality of touch blocks separated from each other, wherein the touch blocks include a plurality of common electrodes connected to each other; The touch block is connected to one or multiple adjacent touch signal lines through a touch hole, multiple touch signal lines connected to the same touch block are connected to the same touch signal terminal, and touch signal lines connected to different touch blocks are connected to different touch signal terminals.

18. The display substrate according to claim 17, wherein: The common electrode layer is located between the data signal line and the touch signal line, and the display area further includes: A first pixel electrode layer, located at a side of the touch signal line away from the base substrate, comprising a plurality of first pixel electrodes separated from each other, and a transfer electrode separated from the first pixel electrodes; The touch hole includes a half hole and a first through hole, the switching electrode is connected to the touch signal line through the half hole, and the switching electrode is connected to the touch block through the first through hole.

19. The display substrate according to claim 17 or 18, wherein: The plurality of touch blocks are arranged in an array along a first direction and a second direction, the plurality of touch blocks are divided into a plurality of touch areas arranged along the first direction, and the touch areas include one column or a plurality of adjacent columns of touch blocks; The multiple touch areas include a first touch area and a second touch area, and the multiple touch holes in the first touch area are axially symmetrical or translationally symmetrical with the multiple touch holes in the second touch area.

20. The display substrate according to any one of claims 16 to 19, wherein: The border area includes: a touch signal terminal, which is arranged in the same layer as the touch signal line and is connected to each other, and is used to provide a touch signal to the touch signal line; and A data signal terminal, arranged in the same layer as the data signal line and connected to each other, and used to provide a data signal to the data signal line; The touch signal terminal is located between the plurality of data signal terminals, and both the touch signal terminal and the data signal terminal are used to bind a source driver chip.

21. The display substrate according to any one of claims 1 to 20, wherein: The border area includes: a scanning signal terminal, which is provided in the same layer as the scanning signal line and connected to the switching signal line via hole, and is used to provide a scanning signal to the switching signal line and the scanning signal line; and A data signal terminal, arranged in the same layer as the data signal line and connected to each other, and used to provide a data signal to the data signal line; Wherein, the scan signal terminal and the data signal terminal are located on the same side of the display area.

22. The display substrate according to claim 21, wherein: The plurality of scan signal terminals are divided into one or more scan signal binding areas, and the scan signal binding area is used to bind a gate drive chip; The plurality of data signal terminals are divided into a plurality of data signal binding areas, and the data signal binding areas are used to bind a source driver chip; The scan signal binding area is arranged between two adjacent data signal binding areas, and at most one scan signal binding area is arranged between two adjacent data signal binding areas, and at most two data signal binding areas are arranged between two adjacent scan signal binding areas.

23. The display substrate according to claim 22, wherein: The plurality of data signal binding areas include a first data signal binding area and a second data signal binding area, the first data signal binding area and the second data signal binding area are arranged close to a first edge or a second edge, the first edge and the second edge are two opposite edges of the display substrate in a first direction; and The scan signal binding area is disposed between the first data signal binding area and the second data signal binding area.

24. A display panel comprising: A cell substrate, a liquid crystal layer, and a display substrate as claimed in any one of claims 1 to 23, wherein the liquid crystal layer is located between the cell substrate and the display substrate, and the display area is arranged close to the liquid crystal layer.

25. A display device comprising: The display substrate according to any one of claims 1 to 23; A source driver chip, bound and connected to the frame area, for providing a data signal to the data signal line; and one of the following: A gate driving chip, which is bound and connected to the frame area and is located on the same side of the display area as the source driving chip, and is used to provide scanning signals to the switching signal lines and the scanning signal lines; The gate driving circuit is located in the frame area and on the same side of the display area as the source driving chip, and is used to provide scanning signals to the switching signal lines and the scanning signal lines.

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