Test method, test system, upper computer and lower computer

Abstract

The invention relates to the field of testing, and discloses a testing method, a testing system, an upper computer and a lower computer, the upper computer obtains an interface testing signal name input by a user, and determines a signal identifier of the interface testing signal name; generating an interface test sending signal according to a hardware resource and a signal data structure corresponding to the signal identifier, and sending the interface test sending signal to a data interaction medium; receiving a data receiving notification issued by the data interaction medium, and obtaining test response data; determining an interface test result according to the interface test signal name and the test response data; a user inputs the interface test signal name on the upper computer, the upper computer can select the specified interface of the corresponding to-be-tested equipment for testing through the hardware resource corresponding to the signal identifier, the operation of the user is simple, and the interface test of the plurality of to-be-tested equipment can be realized by inputting the plurality of interface test signal names on the upper computer by the user. The test efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of testing, and particularly to a testing method, a testing system, a host computer, and a slave computer. Background Art

[0002] In industries such as aviation, military, automotive, marine, and power, testing has received increasing attention. With the continuous progress of technology and the improvement of safety standards, testing can ensure the reliability and safety of products.

[0003] In the prior art, the testing efficiency of interface testing for products in industries such as aviation, military, automotive, marine, and power is relatively low. Summary of the Invention

[0004] The purpose of the embodiments of this application is to provide a testing method, a testing system, a host computer, and a slave computer to improve testing efficiency.

[0005] To solve the above technical problems, an embodiment of this application provides a testing method applied to a host computer. The method includes: obtaining the interface test signal name input by a user, and determining the signal identifier of the interface test signal name; generating an interface test sending signal according to the hardware resources and signal data structure corresponding to the signal identifier, and sending the interface test sending signal to a data interaction medium; receiving a received data notification issued by the data interaction medium, and obtaining test response data; determining an interface test result according to the interface test signal name and the test response data.

[0006] An embodiment of this application also provides a testing method. The hardware resources include: slave computer address, slave computer board card number, board card channel number, board card number of a device under test, and channel number of the device under test.

[0007] An embodiment of this application also provides a testing method. The determining the signal identifier of the interface test signal name includes: determining the management handle of the interface test signal corresponding to the interface test signal name; querying and obtaining the signal identifier in the management handle of the interface test signal.

[0008] An embodiment of this application also provides a testing method applied to a slave computer. The method includes: obtaining an interface test sending signal issued by a data interaction medium; if the slave computer address in the interface test sending signal is the address of the slave computer, packing the signal data structure in the interface test sending signal to obtain a data packet, and based on the hardware resources in the interface test sending signal, sending the data packet to the target channel of the device under test corresponding to the hardware resources; receiving test response data sent by the target device under test, and writing the test response data to the target memory address of the data interaction medium.

[0009] An embodiment of the present application further provides a test method. After obtaining the interface test sending signal released by the data interaction medium, it further includes: if the slave machine address in the interface test sending signal is not the address of the slave machine, discard the interface test sending signal.

[0010] An embodiment of the present application further provides a test method. The hardware resources include: the slave machine address, the slave machine board card number, the board card channel number, the board card number of the device under test, and the channel number of the device under test.

[0011] An embodiment of the present application further provides a test method. Based on the hardware resources in the interface test sending signal, sending the data packet to the target channel to be tested of the target device under test corresponding to the hardware resources includes: determining the target board card of the slave machine and the target channel of the slave machine board card in the slave machine according to the slave machine board card number and the board card channel number; determining the board card to be tested and the target channel to be tested in the target device under test according to the board card number of the device under test and the channel number of the device under test; the target board card of the slave machine in the slave machine sends the data packet to the target channel to be tested of the board card to be tested in the target device under test through the target channel of the slave machine board card.

[0012] An embodiment of the present application further provides a test system. The system includes: a host computer, a data interaction medium, at least one slave machine, and at least one device under test; the host computer is used to execute the test method described in any one of the above; the slave machine is used to execute the test method described in any one of the above; the host computer is connected to the data interaction medium, and each slave machine is connected to the data interaction medium; each slave machine includes at least one board card, and each board card is provided with at least one channel; each channel of the board card of the slave machine is connected to a channel of the device under test.

[0013] An embodiment of the present application further provides a host computer, including: at least one first processor; and a first memory communicatively connected to the at least one first processor; wherein, the first memory stores instructions executable by the at least one first processor, and the instructions are executed by the at least one first processor so that the at least one first processor can execute the test method described in any one of the above.

[0014] An embodiment of the present application further provides a lower computer, including: at least one second processor; and at least one board card communicatively connected to the at least one second processor; a second memory communicatively connected to the at least one second processor; wherein the second memory stores instructions executable by the at least one second processor, and the instructions are executed by the at least one second processor so that the at least one second processor can execute the test method described in any one of the above.

[0015] In the present application, a user can input an interface test signal name on an upper computer. The upper computer can select a specified interface of a corresponding device under test through the hardware resources corresponding to the signal identifier for testing. The operation of the user is simple. Moreover, when the user inputs multiple interface test signal names on the upper computer, the interface test of multiple devices under test can be realized, and the test efficiency can be improved. Description of the Drawings

[0016] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplary illustrations do not constitute a limitation on the embodiments.

[0017] Figure 1 is a schematic structural diagram of a test system provided by an embodiment of the present application;

[0018] Figure 2 is a flowchart of a test method provided by an embodiment of the present application;

[0019] Figure 3 is a flowchart of another test method provided by an embodiment of the present application;

[0020] Figure 4 is a schematic structural diagram of an upper computer provided by an embodiment of the present application;

[0021] Figure 5 is a schematic structural diagram of a lower computer provided by an embodiment of the present application. Detailed Embodiments

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are proposed for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be implemented. The following division of each embodiment is for convenience of description and should not constitute any limitation on the specific implementation manner of the present application. Each embodiment can be combined and cross-referenced with each other on the premise of not conflicting.

[0023] An embodiment of the present application relates to a test systemFigure 1 This is a schematic structural diagram of a test system provided by an embodiment of the present application. As Figure 1 shown, the test system includes: multiple host computers 10, a data interaction medium 20, multiple slave computers 30, and multiple devices under test 40.

[0024] Among them, the multiple host computers 10 are connected to the data interaction medium 20. The host computer 10 can send data to the data interaction medium 20, can also obtain data from the data interaction medium 20, and receive data sent by the data interaction medium 20.

[0025] The multiple slave computers 30 are connected to the data interaction medium 20. Each slave computer 30 can send data to the data interaction medium 20, can also obtain data from the data interaction medium 20, and receive data sent by the data interaction medium 20.

[0026] In the embodiment of the present application, the data interaction medium 20 can ensure the consistency of the data between the host computer and the slave computer.

[0027] Optionally, the data interaction medium 2 can include: a host computer data interaction medium and a slave computer data interaction medium. When the data in the host computer data interaction medium changes, the data in the slave computer data interaction medium changes synchronously, ensuring the consistency of the data in the host computer data interaction medium and the slave computer data interaction medium, and further ensuring the consistency of the data between the host computer and the slave computer.

[0028] Each slave computer 30 includes at least one board. The board is a hardware component integrating electronic components and functional modules, and can exist in the form of a circuit board. The board is used to implement specific functions of the slave computer, such as data acquisition, signal processing, communication interfaces, etc.

[0029] Each board is provided with at least one channel. Among them, the channel can be a communication interface of the board. The communication interface of the board is a physical connection and protocol interface for data exchange between the board and the device under test. Different communication interfaces can support different communication protocols, transmission rates, connection distances, etc.

[0030] Optionally, different types of boards can provide different communication interfaces to enable efficient data interaction with different devices under test.

[0031] In the embodiment of the present application, the multiple channels of each board are different communication interfaces, supporting different communication protocols.

[0032] Each channel of the board of the slave computer is connected to a channel of a device under test. Exemplarily, as Figure 1As shown in the figure, one channel (left channel) of the board 1 of the lower computer 1 is connected to one channel of the device under test 1, and the other channel (right channel) of the board 1 is connected to one channel of the device under test 2. In other cases, each channel of the board of the lower computer is connected to one channel (the channel of the device under test). One channel (left channel) of the board 1 of the lower computer 1 can be connected to one channel of the device under test 1, and the other channel (right channel) of the board 1 is connected to another channel of the device under test 1, and the communication protocols corresponding to the two channels of the device under test are different.

[0033] Among them, one of the boards of each lower computer can be connected to multiple channels of multiple devices under test through multiple channels. The number of devices under test connected by each board can be the same or different, and no specific limitation is made in the embodiments of the present application.

[0034] Optionally, the number of upper computers can also be two, three, etc. Each upper computer is connected to the data interaction medium 20, and the test interfaces of each upper computer are different. For example, one upper computer can test multiple devices under test, and all the devices under test tested by multiple upper computers are all components of a product.

[0035] In the test system provided by the embodiments of the present application, each upper computer can test the interfaces of the devices under test, and multiple upper computers can test multiple interfaces of multiple devices under test simultaneously, which can improve the test efficiency.

[0036] Based on the test system provided in the above embodiments, the embodiments of the present application also provide a test method. Figure 2 It is a flowchart of a test method provided by the embodiments of the present application. As Figure 2 shown, this test method is applied to the upper computer in the above test system, and specifically includes the following steps.

[0037] Step 201, obtain the interface test signal name input by the user, and determine the signal identifier of the interface test signal name.

[0038] A user interface is set on the upper computer. The user can input the interface test signal name on the input interface. The upper computer obtains the interface test signal name and determines the signal identifier (ID, IDentity) of the interface test signal name based on the pre-set mapping relationship between the interface test signal name and the signal identifier.

[0039] Step 202, generate an interface test sending signal according to the hardware resources and signal data structure corresponding to the signal identifier, and send the interface test sending signal to the data interaction medium.

[0040] The mapping relationship between the signal identifier and the hardware resources and signal data structure is pre-set in the upper computer, and the corresponding hardware resources and signal data structure can be determined based on the signal identifier.

[0041] Among them, the hardware resources refer to the hardware information in the transmission path of the interface test signal corresponding to the signal identifier and the channel information in the hardware. Since different channels correspond to different communication protocols and different communication protocols have different data structures, the signal data structure refers to the management structure of the detailed information of the interface test signal corresponding to the signal identifier, and the interface test signal is an ICD (Interface Control Document) signal.

[0042] Exemplarily, according to the signal data structure corresponding to the signal identifier, initialize the interface test transmission signal, and then update / write information such as hardware resources into the interface test transmission signal to obtain the final interface test transmission signal.

[0043] The host computer sends the interface test transmission signal to the data interaction medium. In one case, the data interaction medium multicasts the interface test transmission signal, so that the channels of the lower-level machines corresponding to the hardware resources receive the interface test transmission signal and respond to the data interaction medium; in another case, when the host computer data interaction medium receives the interface test transmission signal, the data synchronization in the lower-level machine data interaction medium changes, ensuring that the data in the host computer data interaction medium and the lower-level machine data interaction medium are consistent. The lower-level machine data interaction medium multicasts the data change situation, so that the specified channels of the lower-level machines corresponding to the hardware resources receive the data change situation and respond to the lower-level machine data interaction medium, and the data synchronization in the host computer data interaction medium changes.

[0044] Step 203: Receive the received data notification issued by the data interaction medium and obtain the test response data.

[0045] After the data interaction medium receives the test response data, it will issue a received data notification to the host computer. If there are multiple host computers, it will send the received data notification to all of them. Among them, the received data notification contains the test response data, and the host computer can obtain the test response data.

[0046] Step 204: Determine the interface test result according to the interface test signal name and the test response data.

[0047] Optionally, if the host computer is the host computer that sends the interface test transmission signal, then this host computer obtains the test response data and determines the interface test result according to the interface test signal name and the test response data; if the host computer is not the host computer that sends the interface test transmission signal, then this host computer directly discards the test response data after obtaining it.

[0048] In the embodiments of the present application, the interface test signal name corresponds to expected data or an expected data range. If the test response data is the expected data or the test response data is within the expected data range, the test passes; otherwise, the test fails. When the test fails, it is necessary to further optimize and adjust the interface of the device under test.

[0049] Optionally, a user can input multiple interface test signal names on one host computer to test multiple specified interfaces of multiple devices under test. For example, Figure 1 as shown, the user inputs interface test signal name 1 and interface test signal name 2 on host computer 1. Through the hardware resource 1 corresponding to the signal identifier 1 of interface test signal name 1, the specified interface of the corresponding device under test 1 can be selected for testing. Through the hardware resource 2 corresponding to the signal identifier 2 of interface test signal name 2, the specified interface of the corresponding device under test 2 can be selected for testing.

[0050] Optionally, multiple users can respectively input multiple interface test signal names on two host computers to test multiple specified interfaces of multiple devices under test. As Figure 1 shown, user 1 inputs interface test signal name 1 on host computer 1, and user 2 inputs interface test signal name 2 on host computer 2. Host computer 1 can select the specified interface of the corresponding device under test 1 through the hardware resource 1 corresponding to the signal identifier 1 of interface test signal name 1, and host computer 2 can select the specified interface of the corresponding device under test 5 through the hardware resource 2 corresponding to the signal identifier 2 of interface test signal name 2.

[0051] In the embodiments of the present application, the user can input the interface test signal name on the host computer, and through the hardware resource corresponding to the signal identifier, the specified interface of the corresponding device under test can be selected for testing. The operation of the user is simple. Moreover, when the user inputs multiple interface test signal names on the host computer, the interface test of multiple devices under test can be realized, improving the test efficiency.

[0052] Based on the above Figure 2 shown test method, the embodiments of the present application also provide another test method. The hardware resources in step 202 above include: slave computer address, slave computer board card number, board card channel number, device under test board card number, and device under test channel number.

[0053] Among them, the slave computer address is used to identify the unique identifier of a slave computer in the system. For example, the slave computer address can be the IP (Internet Protocol Address) address of the slave computer, and the IP address of the slave computer is used to identify the unique location of the slave computer in the system. In a multi-device system, the host computer communicates with a specific slave computer through the slave computer address.

[0054] The slave computer in the embodiments of the present application includes at least one board. In a slave computer with multiple boards, a slave computer board card number is used. The slave computer board card number is a number that uniquely identifies different boards in the slave computer. In a slave computer with multiple boards, each board is responsible for a different function or processes different tasks, and the slave computer board card number is used to distinguish different boards. For example, as Figure 1 shown, the slave computer 1 has two boards. Board 1 can be responsible for data acquisition, and board 2 can be responsible for control output. At this time, the slave computer board card number 001 is used to identify board 1, and the slave computer board card number is used to identify board 2.

[0055] The board card channel number is used to identify different input and output channels on a slave computer board. Each channel can independently process different signals or tasks. The board card channel number helps to identify and distinguish multiple independent channels on the board. For example, a data acquisition board may have multiple input channels (channel 0, channel 1, channel 2, channel 3), and each channel is used to collect data from different sensors.

[0056] The board card number of the device under test refers to the number used to identify a specific board in the device under test during the test process, and is used to indicate which board in the device under test participates in the test. During the test process, the test content of different boards may be different, so it is necessary to specify the specific test object through the board card number of the device under test. For example, board 1 in the device under test may be used for temperature monitoring, and board 2 in the device under test may be used for pressure monitoring. During the test, it is necessary to specify which board participates in the test.

[0057] The channel number of the device under test refers to the number used to identify a specific channel of the board in the device under test during the test process. Similar to the board card channel number in the slave computer, each channel of each board in the device under test may have different functions or input and output signals. The channel number of the device under test is used to specify a specific input or output channel of the board corresponding to the board card number of the device under test in the device under test, for precise testing and monitoring. Different tests may only involve specific channels.

[0058] The data interaction medium sends a signal according to the interface test, uses the board corresponding to the slave computer board card number corresponding to the slave computer address in the hardware resources, and adopts the channel corresponding to the board card channel number to test the specified channel of the board corresponding to the board card number of the device under test in the hardware resources and corresponding to the channel number of the device under test.

[0059] Optionally, the hardware resources may further include: the status of the channel (sending data / receiving data).

[0060] In the embodiments of the present application, the slave machine address is used to uniquely identify the slave machine in the entire system. The slave machine board card number is used to identify the specific hardware board card in the slave machine. The slave machine channel number is used to identify the specific input / output channel on the slave machine board card. The device under test board card number is used to identify the specific board card in the device under test. The device under test channel number is used to identify the specific input / output channel of the board card in the device under test. Through the hardware resources including the slave machine address, the slave machine board card number, the board card channel number, the device under test board card number, and the device under test channel number, the specified interface and the detailed test path of the device under test can be specified to perform accurate interface testing.

[0061] Based on the above Figure 2 shown test method, the embodiments of the present application also provide another test method. The above step 201 of determining the signal identifier of the interface test signal name includes: determining the management handle of the interface test signal corresponding to the interface test signal name; querying the signal identifier in the management handle of the interface test signal.

[0062] In the embodiments of the present application, the management handle of the interface test signal includes: signal data structure, source interface for signal transmission, destination interface for signal transmission, signal type, signal identifier, etc.

[0063] Among them, the source interface for signal transmission can be the slave machine address, the slave machine board card number, and the board card channel number; the destination interface for signal transmission can be the device under test board card number and the device under test channel number; the signal type can be an analog signal or a digital signal, etc.; the signal identifier is used to uniquely identify each interface test signal, and it can be an ID or a similar mark to help the test system identify and operate specific signals.

[0064] Optionally, the signal identifier and the signal type can also be recorded in the signal data structure. The source interface for signal transmission and the destination interface for signal transmission can form hardware resources, and there are no specific restrictions in the embodiments of the present application.

[0065] Optionally, the management handle of the interface test signal can be the attribute information of the interface test signal, or the management handle of the interface test signal can also be included in the attribute information of the interface test signal, and there are no specific restrictions in the embodiments of the present application.

[0066] In the embodiments of the present application, by effectively associating the signal name with the management handle and the signal identifier, the interface test signal can be quickly located and identified, improving the efficiency of interface testing and avoiding the cumbersome process of manual search and manual judgment.

[0067] Based on the test method provided in the above embodiments, the embodiments of the present application also provide a test method. Figure 3is a flow chart of another testing method provided in an embodiment of the present application, such as Figure 3 As shown, the test method is applied to the lower computer in the above test system, and specifically includes the following steps.

[0068] Step 301: Acquire an interface test sending signal issued by a data interaction medium.

[0069] The data interaction medium multicasts the interface test sending signal so that all lower computers can obtain the interface test sending signal.

[0070] Optionally, after receiving the interface test transmission signal, the data interaction medium may re-package the data according to the interface test transmission signal, and then multicast the new package, so that all lower computers can obtain the new package.

[0071] Step 302, if the lower computer address in the interface test signal is the address of the lower computer, the signal data structure in the interface test signal is packaged to obtain a data packet, and based on the hardware resources in the interface test signal, the data packet is sent to the target channel under test of the target device under test corresponding to the hardware resources.

[0072] If the lower computer address in the interface test signal is the address of the lower computer, it means that the lower computer is the lower computer in the test path. If the lower computer address in the interface test signal is not the address of the lower computer, the lower computer discards the interface test signal.

[0073] In the embodiment of the present application, the slave computer address in the interface test sending signal corresponds to at most one slave computer in the test system.

[0074] For example, Figure 1 As shown, if the address of lower computer 1 is different from the lower computer address in the interface test signal, lower computer 1 directly discards the interface test signal; if the address of lower computer 2 is the same as the lower computer address in the interface test signal, lower computer 2 is a lower computer in the test path.

[0075] The lower computer 2 packages the signal data structure in the interface test transmission signal to obtain a data packet, and based on the hardware resources in the interface test transmission signal, sends the data packet to the target channel to be tested of the target device to be tested corresponding to the hardware resources.

[0076] The packetization process is to combine the parts of the signal data structure into a complete transmittable data packet according to a specific protocol or format, wherein the specific protocol or format may be a communication protocol or communication format of a target channel to be tested of the target device to be tested corresponding to the hardware resource.

[0077] Optionally, the packetization method includes: fixed-length packetization or variable-length packetization. Fixed-length packetization means that the size of each data packet is fixed and includes a predefined header and footer; variable-length packetization means that the length of the data packet can vary according to the size of the actual signal to adapt to signal data of different sizes.

[0078] The hardware resources in the interface test transmission signal can ensure that the data packet can be correctly sent to the target channel of the device under test.

[0079] Step 303: Receive the test response data sent by the device under test, and write the test response data to the target memory address of the data interaction medium.

[0080] After the lower computer receives the test response data sent by the target interface of the device under test, based on the test response data and the target interface of the device under test, it determines the signal identifier corresponding to the interface test transmission signal. According to the signal identifier corresponding to the interface test transmission signal, it determines the management handle of the interface test transmission signal, searches for the target memory address of the test response data from the management handle of the interface test transmission signal, and writes the test response data to the target memory address of the data interaction medium.

[0081] If the data of the data interaction medium is updated, then the data interaction medium will multicast the test response data to the upper computers in the test system. The upper computer receives the received data notification issued by the data interaction medium, and then obtains the test response data and displays it.

[0082] Optionally, if there are multiple upper computers in the test system, the upper computer that monitors the interface test transmission signal will obtain the test response data and display it, and other upper computers that do not monitor the interface test transmission signal will discard the test response data.

[0083] Optionally, when the data interaction medium includes an upper computer data interaction medium and a lower computer data interaction medium, after the data of the lower computer data interaction medium is updated, the upper computer data interaction medium will be synchronously updated. The upper computer data interaction medium will multicast the test response data to the upper computers in the test system. The upper computer receives the received data notification issued by the upper computer data interaction medium, and then obtains the test response data and displays it.

[0084] In the embodiments of the present application, the test response data can be a signal code stream. Writing the test response data to the target memory address of the data interaction medium can also be: updating the signal code stream to a specific signal, where the memory address of the signal can be the target memory address. At this time, the data interaction medium issues a received signal notification, and the signal subscribed by the upper computer receives a notification that the code stream has changed, obtains the test response data and updates the interface.

[0085] In the embodiment of the present application, the slave computer sends a data packet to a target channel to be tested of a target device to be tested corresponding to the hardware resource based on the hardware resource in the interface test signal. The data interaction between the slave computer and the device to be tested is automatically performed without the participation of user operations. Moreover, each board of the slave computer and the channels of the device to be tested are independently connected, and interface tests of multiple channels can be performed simultaneously to improve the test efficiency.

[0086] Based on the above Figure 3 shown test method, an embodiment of the present application further provides another test method. The hardware resources in step 302 above include: slave computer address, slave computer board card number, board card channel number, device to be tested board card number, and device to be tested channel number.

[0087] The slave computer address, slave computer board card number, board card channel number, device to be tested board card number, and device to be tested channel number have all been introduced in detail in the above embodiment and will not be elaborated here.

[0088] Optionally, the slave computer address may not be included in the hardware resources, and there is no specific limitation in the embodiment of the present application.

[0089] Optionally, the hardware resources may further include: the state of the channel (sending data / receiving data).

[0090] The above step 302, based on the hardware resource in the interface test signal, sends a data packet to a target channel to be tested of a target device to be tested corresponding to the hardware resource, includes: determining the target board of the slave computer and the target channel of the slave computer board in the slave computer according to the slave computer board card number and the board card channel number; determining the target board to be tested and the target channel to be tested in the target device to be tested according to the device to be tested board card number and the device to be tested channel number; the target board of the slave computer in the slave computer sends the data packet to the target channel to be tested of the target board to be tested in the target device to be tested through the target channel of the slave computer board.

[0091] The target device to be tested usually has multiple boards, and each board usually has multiple channels to be tested, such as multiple data input channels or communication ports. The slave computer needs to select a specified target channel to be tested according to the hardware resources.

[0092] Exemplarily, such as Figure 1As shown in the figure, the target lower computer board card corresponding to the lower computer board card number can be the board card 1 in the lower computer 1, the target channel of the lower computer board card corresponding to the board card channel number can be the left channel of the board card 1, the target device under test corresponding to the device under test board card number can be the device under test 1, the target board card of the device under test corresponding to the device under test board card number can be a certain board card in the device under test 1, and the target channel of the device under test corresponding to the device under test channel number can be a certain channel of a certain board card in the device under test 1. The board card 1 in the lower computer 1 sends data packets through the left channel to a certain channel of a certain board card in the device under test 1.

[0093] Optionally, the transmission mode of the data packet may be synchronous or asynchronous. During synchronous transmission, when sending data packets, the lower computer and the device under test are synchronized in strict time sequence to ensure that the data is received in order. During asynchronous transmission, the data packet is sent asynchronously through the interface, and the device under test performs data reorganization and verification by itself.

[0094] In actual interface testing, the upper computer may send multiple interface test sending signals simultaneously. At this time, the test system needs to handle the concurrent transmission of multiple signals to ensure that each signal can be correctly sent to the corresponding target channel of the device under test.

[0095] Optionally, different priorities can also be set for different types of interface test sending signals to ensure that high-priority signals can be sent first when the system resources are sufficient. In the case of limited hardware resources and transmission channels, the load balancing algorithm is used to ensure that the resources are not occupied by a single signal, thereby improving the overall throughput of the system. Precise management of the sending timings of multiple signals is required to ensure that the signals are sent in the correct time sequence and to avoid interference with each other.

[0096] In the embodiment of the present application, through the hardware resources including the lower computer address, the lower computer board card number, the board card channel number, the device under test board card number, and the device under test channel number, the specified interface of the device under test and the detailed test path can be quickly located, which can not only improve the efficiency of interface testing, but also perform accurate interface testing.

[0097] The present application not only supports editing and inputting signals during the communication and collaboration process, but also uniformly manages different subsystems and components in a tree-like form. Through this management method, users can clearly understand how many components are under each subsystem and the number of transceiver signals involved in each component. In addition, this technology also provides a signal tracking function, enabling users to accurately know which hardware unit each signal is sent or received through. This transparent management method helps to improve the maintainability and efficiency of the system, ensuring smoother collaborative work among various components.

[0098] This application adopts a distributed architecture design, which can support the separate deployment of 5 to 20 device systems in multiple systems. Through one of the devices, it is possible to control the joint debugging of simulation interfaces such as the verification of interfaces, the injection of faults, and the elimination of faults based on the ICD and the hardware units of each system among any systems; this application provides a complete set of design and verification technologies, including the design of ICD, the management of hardware resources, the verification of interfaces, the injection and elimination of faults, effectively ensuring the testing and verification of the entire set of design solutions in industries such as aviation, military, automotive, marine, and power.

[0099] During the distributed simulation test based on ICD in this application, it is ensured that effective communication and collaboration are carried out among different parts based on ICD, including the verification of interfaces between different systems, the injection of faults, the elimination of faults, etc.

[0100] This application can perform ICD management, which is mainly used for designing and managing various bus interfaces, including attributes such as devices, buses, channels, signals, and specific signal parameters.

[0101] This application can perform channel management, which is mainly used for binding the ICD interface to the hardware unit, including two parts. One part is the hardware information of all distributed systems, such as the physical information of all boards in each system and all channels of each board; the other part is the binding of the bus interface designed and defined by the ICD management module to the physical information of the lower computer; finally, it specifically shows the relationship between the bus interface of the ICD and the specific board channel interface.

[0102] An embodiment of this application relates to a host computer. Figure 4 It is a schematic structural diagram of the host computer provided by the embodiment of this application, as Figure 4 shown, including: at least one first processor 401; and a first memory 402 communicatively connected to at least one first processor 401; wherein, the first memory 402 stores instructions executable by at least one first processor 401, and the instructions are executed by at least one first processor 401, so that at least one first processor 401 can execute the test methods in the above embodiments.

[0103] Among them, the first memory 402 and the first processor 401 are connected by a bus, and the bus can include any number of interconnected buses and bridges, and the bus connects various circuits of one or more first processors and the first memory together.

[0104] An embodiment of this application relates to a slave computer. Figure 5 It is a schematic structural diagram of the slave computer provided by the embodiment of this application, as Figure 5As shown, it includes: at least one second processor 501; and at least one board 503 communicatively connected to the at least one second processor; a second memory 502 communicatively connected to the at least one second processor 501; wherein, the second memory 502 stores instructions executable by the at least one second processor 501, and the instructions are executed by the at least one second processor 501 to enable the at least one second processor 501 to execute the test methods in the above various embodiments.

[0105] Wherein, the second memory 502 and the second processor 501 are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more second processors and the second memory together.

[0106] An embodiment of the present application relates to a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the above method embodiments are implemented.

[0107] That is, those skilled in the art can understand that all or part of the steps in implementing the above method embodiments can be completed by instructing relevant hardware through a program. This program is stored in a storage medium and includes several instructions to enable a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0108] Those of ordinary skill in the art can understand that the above various embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A testing method, characterized in that: Applied to a host computer, the method includes: Obtaining an interface test signal name input by a user, and determining a signal identifier of the interface test signal name; Generate an interface test sending signal according to the hardware resources and signal data structure corresponding to the signal identifier, and send the interface test sending signal to the data interaction medium; Receiving a data receiving notification issued by the data interaction medium, and acquiring test response data; An interface test result is determined according to the interface test signal name and the test response data.

2. The testing method according to claim 1, characterized in that: The hardware resources include: a lower computer address, a lower computer board number, a board channel number, a board number of a device under test, and a channel number of a device under test.

3. The testing method according to claim 1, characterized in that: The step of determining the signal identifier of the interface test signal name comprises: Determine the management handle of the interface test signal corresponding to the interface test signal name; The signal identifier is obtained by querying in the management handle of the interface test signal.

4. A testing method, characterized in that: Applied to a lower computer, the method includes: Obtaining an interface test sending signal issued by a data interaction medium; If the lower computer address in the interface test signal is the address of the lower computer, packetize the signal data structure in the interface test signal to obtain a data packet, and send the data packet to the target channel to be tested of the target device to be tested corresponding to the hardware resource based on the hardware resource in the interface test signal; Receive test response data sent by the target device under test, and write the test response data into a target memory address of the data exchange medium.

5. The testing method according to claim 4, characterized in that: After obtaining the interface test sending signal issued by the data interaction medium, the method further includes: If the lower computer address in the interface test sending signal is not the address of the lower computer, the interface test sending signal is discarded.

6. The testing method according to claim 4, characterized in that: The hardware resources include: the lower computer address, the lower computer board number, the board channel number, the device under test board number, and the device under test channel number.

7. The testing method according to claim 6, characterized in that: The step of sending the data packet to a target channel of a target device under test corresponding to the hardware resource based on the hardware resource in the interface test sending signal comprises: Determine the lower computer target board and the lower computer board target channel in the lower computer according to the lower computer board number and the board channel number; Determine the target board and the target channel in the target device under test according to the device under test board number and the device under test channel number; The lower-computer target board in the lower-computer sends the data packet to the target channel to be tested of the target board to be tested in the target device to be tested through the lower-computer board target channel.

8. A testing system, characterized in that: The system comprises: a plurality of host computers, a data interaction medium, a plurality of slave computers, and a plurality of devices to be tested; the host computers are used to execute the test method described in any one of claims 1 to 3; the slave computers are used to execute the test method described in any one of claims 4 to 7; The multiple host computers are connected to the data interaction medium, and the multiple slave computers are connected to the data interaction medium; each of the slave computers includes at least one board card, and each of the board cards is provided with at least one channel; each channel of the board card of the slave computer is connected to a channel of the device under test.

9. A host computer, characterized in that: include: at least one first processor; as well as, a first memory communicatively connected to the at least one first processor; wherein, The first memory stores instructions that can be executed by the at least one first processor, and the instructions are executed by the at least one first processor to enable the at least one first processor to perform the testing method according to any one of claims 1 to 3.

10. A lower computer, characterized in that: include: at least one second processor; as well as, at least one board in communication with the at least one second processor; a second memory communicatively connected to the at least one second processor; wherein, The second memory stores instructions that can be executed by the at least one second processor, and the instructions are executed by the at least one second processor so that the at least one second processor can perform the testing method according to any one of claims 4 to 7.

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