System and method for verifying critical paths of integrated circuits

Abstract

A verification circuit is disposed near a critical path for testing the critical path. The verification circuit receives test data from the control circuit for testing the critical path. The test data indicates a delay value associated with the critical path. The verification circuit generates a plurality of set signals and enable signals to facilitate the testing of the critical path based on the test data. The verification circuit generates a first test signal based on the enable signal and generates a second test signal based on the first test signal and the set signal. The second test signal is a delayed version of the first test signal. The verification circuit compares the first test signal and the second test signal. A mismatch between the first test signal and the second test signal indicates a deviation from the delay value.

Description

Technical Field

[0001] The present disclosure generally relates to electronic circuits, and more particularly, to systems and methods for verifying critical paths of integrated circuits. Background Art

[0002] Integrated circuits (ICs) include various critical paths for coupling components of the IC. A critical path may refer to a path that includes a series of components such that the critical path maximizes the delay of signals passing through the critical path. The critical paths of an IC are prone to delays due to aging effects, process variations, etc. The delay associated with a critical path causes a delay when receiving an input signal from a component of the critical path. Therefore, verifying such critical paths is essential. Conventional test circuits for verifying such critical paths utilize multiple patterns to stimulate a single critical path. Additionally, conventional test circuits are unable to stimulate critical paths determined to be non-stimulable. As a result, such critical paths are not verified. Summary of the Invention

[0003] According to an embodiment of the present application, a verification circuit for an electronic device is provided, including: a register circuit configured to: receive test data to verify a critical path of the electronic device, wherein the test data indicates a delay value associated with the critical path; and generate a plurality of setting signals and a first enable signal associated with the delay value based on the test data; and a delay circuit coupled to the register circuit, wherein the delay circuit is configured to: receive the plurality of setting signals from the register circuit, wherein after receiving the plurality of setting signals, the delay circuit is configured with the delay value; receive a first test signal generated based on the first enable signal; and delay the first test signal based on configuring the delay circuit with the delay value to output a delayed output signal, wherein a second test signal is generated based on the delayed output signal, and wherein a mismatch between the second test signal and the first test signal indicates a deviation from the delay value associated with the critical path.

[0004] According to one or more embodiments, the verification circuit further includes a first flip-flop coupled to a clock generator, the register circuit, and the delay circuit of the electronic device, and wherein the first flip-flop includes: an input terminal coupled to the register circuit, wherein the input terminal is configured to receive the first enable signal; a clock terminal coupled to the clock generator, wherein the clock terminal is configured to receive a first clock signal; and an output terminal coupled to the delay circuit, wherein the output terminal is configured to generate the first test signal.

[0005] According to one or more embodiments, the delay circuit includes a first delay unit, wherein the first delay unit is coupled to the first flip-flop and the register circuit, and wherein the first delay unit is configured to: receive a first setup signal among the plurality of setup signals from the register circuit, wherein the first setup signal indicates a first value of the delay value, and wherein after receiving the first setup signal, the first delay unit is configured with the first value; receive the first test signal from the output of the first flip-flop; and output a coarse delay signal based on the first value, wherein the coarse delay signal is one of the first test signal and a delayed test signal among a plurality of delayed test signals, and wherein the plurality of delayed test signals are generated based on the delay of the first test signal.

[0006] According to one or more embodiments, the first delay unit includes a plurality of coarse buffers, wherein each coarse buffer of the plurality of coarse buffers includes an input terminal and an output terminal, the input terminal of the first coarse buffer of the plurality of coarse buffers is coupled to the output of the first flip-flop and is configured to receive the first test signal, the input terminal of each of the remaining coarse buffers of the plurality of coarse buffers is coupled to the corresponding output terminal of the previous coarse buffer of the plurality of coarse buffers, and each coarse buffer of the plurality of coarse buffers is configured to generate a corresponding delayed test signal among the plurality of delayed test signals.

[0007] According to one or more embodiments, the first delay unit further includes a first programmable circuit, and wherein the first programmable circuit includes: a first plurality of input terminals, wherein a first input terminal of the first plurality of input terminals is coupled to the output of the first flip-flop, wherein the first input terminal of the first plurality of input terminals is configured to receive the first test signal, wherein each of the remaining input terminals of the first plurality of input terminals is coupled to the output of one of the coarse buffers of the plurality of coarse buffers, and wherein each of the remaining plurality of first input terminals is configured to receive one of the plurality of delayed test signals; a first selection terminal, which is coupled to the register circuit, wherein the first selection terminal is configured to receive the first setup signal, and wherein the first selection terminal is further configured to select one of the first test signal and the delayed test signal among the plurality of delayed test signals based on the first value; and an output terminal, which is configured to output the coarse delay signal based on the selection of one of the first test signal and the delayed test signal.

[0008] According to one or more embodiments, the delay circuit further includes a second delay unit coupled to the first delay unit and the register circuit, and wherein the second delay unit is configured to: receive, from the register circuit, a second setting signal among the plurality of setting signals, wherein the second setting signal indicates a second value of the delay value, and wherein, after receiving the second value setting signal, the second value delay unit is configured with the second value; receive the coarse delay signal from the first delay unit; and output the delayed output signal based on the second value, wherein the delayed output signal is one of the coarse delay signal and one of the coarsely delayed signals of a plurality of delayed coarsely adjusted signals, and wherein the plurality of delayed coarsely adjusted signals are generated based on the delay of the coarse delay signal.

[0009] According to one or more embodiments, the second delay unit includes a plurality of fine adjustment buffers, wherein each fine adjustment buffer of the plurality of fine adjustment buffers includes an input terminal and an output terminal, the input terminal of a first fine adjustment buffer of the plurality of fine adjustment buffers is coupled to the first delay unit and is configured to receive the coarse delay signal, the input terminal of each remaining fine adjustment buffer of the plurality of fine adjustment buffers is coupled to a corresponding output terminal of the previous fine adjustment buffer of the plurality of fine adjustment buffers, and each fine adjustment buffer of the plurality of fine adjustment buffers is configured to generate a coarsely delayed signal corresponding to a delay among the plurality of delayed coarsely adjusted signals.

[0010] According to one or more embodiments, the second delay unit further includes a second programmable circuit, and wherein the second programmable circuit includes: a second plurality of input terminals, wherein a first input terminal of the second plurality of input terminals is coupled to the first delay unit, wherein the first input terminal of the second plurality of input terminals is configured to receive the coarse delay signal, wherein each remaining input terminal of the second plurality of input terminals is coupled to an output terminal of one of the fine adjustment buffers of the plurality of fine adjustment buffers, and wherein each remaining input terminal of the second plurality of input terminals is configured to receive one of the coarsely delayed signals of the plurality of delayed coarsely adjusted signals; a second selection terminal coupled to the register circuit, wherein the second selection terminal is configured to receive the second setting signal, and wherein the second selection terminal is further configured to select one of the coarse delay signal and the coarsely delayed signal of the plurality of delayed coarsely adjusted signals based on the second value; and an output terminal configured to output the delayed output signal based on one of the coarse delay signal and the coarsely delayed signal.

[0011] According to one or more embodiments, the register circuit is further configured to generate a second enable signal based on the test data.

[0012] According to one or more embodiments, the verification circuit further includes a second flip - flop, wherein the second flip - flop is coupled to a clock generator, the register circuit, and the delay circuit of the electronic device, and wherein the second flip - flop includes: a first input terminal coupled to the register circuit, wherein the first input terminal is configured to receive the second enable signal; a second input terminal coupled to the delay circuit, wherein the second input terminal is configured to receive the delayed output signal; a clock terminal coupled to the clock generator, wherein the clock terminal is configured to receive a first clock signal; and an output terminal configured to generate the second test signal.

[0013] According to one or more embodiments, the register circuit includes a control register, the control register is coupled to the delay circuit, and wherein the control register is configured to: receive the test data from a control circuit of the electronic device; and generate the first enable signal, the second enable signal, and the plurality of setting signals based on the test data.

[0014] According to one or more embodiments, the register circuit includes a status register, the status register is coupled to the second flip - flop, and wherein the status register is configured to: receive the second test signal from the second flip - flop; and store data associated with the second test signal based on the reception of the second test signal.

[0015] According to one or more embodiments, the verification circuit further includes a comparator, and wherein the comparator is configured to: receive the first test signal and the second test signal; compare the first test signal and the second test signal; and generate a fault signal, wherein the fault signal toggles based on a mismatch between the second test signal and the first test signal.

[0016] According to one or more embodiments, the second test signal and the fault signal are provided to a control circuit of the electronic device, and wherein a deviation from the delay value is detected by the control circuit based on the toggling of the fault signal, and the control circuit transitions from an active state to a safe state based on the fault signal and the second test signal.

[0017] According to one or more embodiments, a match between the second test signal and the first test signal indicates a normal delay associated with the critical path.

[0018] According to one or more embodiments, the verification circuit is located near the critical path.

[0019] According to one or more embodiments, the deviation from the delay value indicates one of the following: the aging effect on the critical path and the impact of process variations on the critical path.

[0020] According to a second aspect of the present application, there is provided a verification method, including: receiving, by a register circuit, test data to test a critical path of an electronic device, where the test data indicates a delay value associated with the critical path; generating, by the register circuit, a plurality of setting signals and a first enable signal associated with the delay value based on the test data; receiving, by a delay circuit, the plurality of setting signals indicating configuring the delay circuit with the delay value and a first test signal generated based on the first enable signal; and delaying, by the delay circuit, the first test signal based on the delay value to output a delayed output signal, where a second test signal is generated based on the delayed output signal, and where a mismatch between the second test signal and the first test signal indicates a deviation from the delay value associated with the critical path.

[0021] According to one or more embodiments, the register circuit and the delay circuit are included in a verification circuit of the electronic device, where the verification circuit is located near the critical path, and where the deviation from the delay value indicates one of the following: the aging effect on the critical path and the impact of process variations on the critical path.

[0022] According to one or more embodiments, a match between the second test signal and the first test signal indicates that the delay value is within the normal range of the critical path. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following detailed description of the embodiments of the present disclosure will be better understood when read in conjunction with the accompanying drawings. The present disclosure is illustrated by way of example and is not limited by the drawings, in which like reference numerals indicate like elements.

[0024] Figure 1 A block diagram showing an electronic device according to an embodiment of the present disclosure;

[0025] Figure 2 A schematic block diagram showing a delay circuit of an electronic device according to an embodiment of the present disclosure; and

[0026] Figures 3A - 3C Representing a flowchart according to an embodiment of the present disclosure, showing a verification method for verifying Figure 1 the critical path of an electronic device. DETAILED DESCRIPTION

[0027] The detailed description of the drawings is intended to describe embodiments of the present disclosure and is not intended to represent the only form in which the present disclosure may be practiced. It should be understood that the same or equivalent functions may be implemented by different embodiments that are intended to be covered by the spirit and scope of the present disclosure.

[0028] Overview:

[0029] Verification of all critical paths of an integrated circuit (IC) is crucial for ensuring that the IC performs a specific function in a desired manner. In the case where any critical path is not verified, the security of the IC may be compromised. Conventional test circuits utilize labor-intensive processes such as writing multiple test patterns to stimulate a single critical path. Additionally, multiple test patterns are written for the remaining critical paths, thereby increasing the verification time of the critical paths. Additionally, conventional test circuits are unable to verify critical paths that are determined to be unverifiable.

[0030] Various embodiments of the present disclosure disclose an electronic device that includes a verification circuit located near a critical path of the electronic device. The verification circuit may provide the same delay as the delay associated with the critical path based on being equally exposed to various factors (e.g., aging, process variations, etc.) or the influence from various factors. The verification circuit may include a register circuit, a delay circuit, a first flip-flop, a second flip-flop, and a comparator. The register circuit may receive test data from a control circuit of the electronic device. The test data may indicate a delay value associated with the critical path. Additionally, the register circuit may generate a set signal based on the reception of the test data. The delay circuit may receive the set signal based on the delay value from the register circuit. The delay circuit may be configured with the delay value. Additionally, the first flip-flop may generate a test signal based on an enable signal generated by the register circuit. The delay circuit may additionally delay the test signal based on the delay value to generate a delayed output signal. The second flip-flop may generate another test signal based on the delayed output signal.

[0031] The comparator may compare two test signals from the first flip-flop and the second flip-flop. The comparator may switch a fault signal to indicate a mismatch between the two test signals. Additionally, the comparator may provide the fault signal to the control circuit. Based on the reception of the fault signal, the control circuit may detect a deviation from the delay value.

[0032] Therefore, the technique of verifying critical paths in the present disclosure implements a simple verification design by utilizing a delay circuit, a register circuit, a first flip-flop, and a second flip-flop. The verification circuit can additionally be capable of testing critical paths on a single IC of an electronic device that are determined to be non-feasible for excitation by a conventional test circuit. Additionally, in a scenario where an IC may include multiple critical paths in close proximity to each other, the verification circuit can verify the critical path that provides the maximum delay compared to other critical paths among the critical paths. The verification of the critical path with the maximum delay further verifies other critical paths of the IC. Therefore, multiple critical paths are verified simultaneously by the verification circuit. The verification circuit can additionally test the critical path without interrupting the function of the critical path. Therefore, the normal function of the electronic device remains unaffected during verification. Additionally, when a fault signal toggles, the electronic device can transition to a safe state. In the safe state, the electronic device can perform a controlled shutdown or a reduction in the operating efficiency of operations involving the critical path to ensure that other operations of the electronic device remain unaffected. The present disclosure can additionally enable a control circuit to be coupled to multiple verification circuits and can provide test data to each verification circuit to verify the delay of the corresponding critical path. Additionally, the verification of all critical paths of the electronic device is performed in a similar manner and obviates the need to test a single critical path using multiple test modes.

[0033] Figure 1 FIG. shows a block diagram of an electronic device 100 according to an embodiment of the present disclosure. The electronic device 100 may include a verification circuit 102 that can be used to verify a critical path 106 of the electronic device 100. The electronic device 100 can be an automotive device, a mobile device, etc. The electronic device 100 may additionally include a control circuit 108 and a clock generator 110. The verification circuit 102 and the critical path 106 may be included on an integrated circuit (IC) (not shown).

[0034] Critical path 106:

[0035] To ensure that the electronic device 100 operates in a desired (e.g., normal) manner, the electronic device 100 can be tested by testing critical paths such as the critical path 106 of the electronic device 100. The critical path 106 may refer to a path that includes a series of components (not shown) of the electronic device 100 such that the critical path 106 can provide the maximum delay of a signal passing through the critical path 106. The testing of the critical path 106 is explained in the ongoing description.

[0036] Control circuit 108:

[0037] The control circuit 108 may be included in the electronic device 100 to enable testing of the critical path 106. The control circuit 108 may be coupled to the verification circuit 102. The control circuit 108 may include suitable circuitry configured to perform one or more operations. For example, the control circuit 108 may be configured to provide test data TD to the verification circuit 102. The test data TD may be an expected delay value (e.g., normal delay value) associated with the critical path 106 under normal operating conditions of the electronic device 100. In other words, when data is provided to the various components of the electronic device 100 via the critical path 106, the delay value may be set based on the expected delay associated with the components on the critical path 106. The control circuit 108 may additionally be configured to receive a fault signal FS from the verification circuit 102 based on the test data TD. The control circuit 108 may additionally be configured to determine the status of the test of the critical path 106 based on the fault signal FS. Examples of the control circuit 108 may include, but are not limited to, an application specific integrated circuit (ASIC) processor, a complex instruction set computer (CISC) processor, a central processing unit (CPU), etc.

[0038] Verification circuit 102:

[0039] The verification circuit 102 may be located near the critical path 106. For example, the verification circuit 102 may be located within 2 millimeters (mm) of the critical path 106. The verification circuit 102 is placed near the critical path 106 such that the effects of aging and a number of other factors such as physical damage, wear and tear, manufacturing defects, environmental contaminants, etc. on the verification circuit 102 may be similar to the effects on the critical path 106. The verification circuit 102 may include suitable circuitry configured to perform one or more operations. For example, the verification circuit 102 may test (e.g., verify) the critical path 106. The verification circuit 102 may be coupled to the control circuit 108 and the clock generator 110. The verification circuit 102 may include a register circuit 112, a first flip-flop 114, a delay circuit 116, a second flip-flop 118, and a comparator 120.

[0040] Register circuit 112:

[0041] The register circuit 112 can be coupled to the control circuit 108, the first flip-flop 114, the delay circuit 116, and the second flip-flop 118. The register circuit 112 can be configured to receive test data TD from the control circuit 108. Additionally, the register circuit 112 can be configured to generate a plurality of setting signals S1 - S2, a first enable signal E1, and a second enable signal E2 associated with a delay value. In an example, the first enable signal E1 and the second enable signal E2 can be logic low signals. In another example, the first enable signal E1 and the second enable signal E2 can be logic high signals. The plurality of setting signals S1 - S2 can include a first setting signal S1 and a second setting signal S2. The register circuit 112 can additionally be configured to provide a second test signal T2 to the control circuit 108. The register circuit 112 can include a control register 122 and a status register 124. In an embodiment, the control register 122 and the status register 124 can be data registers.

[0042] Control register 122:

[0043] The control register 122 can be coupled to the control circuit 108, the first flip-flop 114, the delay circuit 116, and the second flip-flop 118. The control register 122 can include suitable circuitry configured to perform one or more operations. For example, the control register 122 can be configured to receive test data TD from the control circuit 108. The control register 122 can additionally be configured to generate a plurality of setting signals S1 - S2, a first enable signal E1, and a second enable signal E2 associated with a delay value based on the test data TD.

[0044] The status register 124 can include suitable circuitry configured to perform one or more operations. The status register 124 has been explained in detail later.

[0045] First flip - flop 114:

[0046] The first flip-flop 114 may be coupled to the register circuit 112, the clock generator 110, and the delay circuit 116. Specifically, the first flip-flop 114 may be coupled to the control register 122 of the register circuit 112. In an embodiment, the first flip-flop 114 may be a D flip-flop. The first flip-flop 114 may include an input terminal, a clock terminal, and an output terminal. The input terminal of the first flip-flop 114 may be coupled to the register circuit 112 (e.g., the control register 122). The input terminal of the first flip-flop 114 may be configured to receive a first enable signal E1 from the register circuit 112 (e.g., the control register 122). The clock terminal of the first flip-flop 114 may be coupled to the clock generator 110. The clock terminal of the first flip-flop 114 may be configured to receive a first clock signal CS from the clock generator 110. Additionally, the output terminal of the first flip-flop 114 may be coupled to the delay circuit 116. The output terminal of the first flip-flop 114 may be configured to generate a first test signal T1 and provide the first test signal T1 to the delay circuit 116.

[0047] Delay circuit 116:

[0048] The delay circuit 116 may be coupled to the first flip-flop 114, the second flip-flop 118, and the control register 122. The delay circuit 116 may be configured to receive a plurality of setting signals S1 - S2 from the control register 122. After receiving the plurality of setting signals S1 - S2, the delay circuit 116 may be configured with a delay value. The delay circuit 116 may additionally be configured to receive the first test signal T1 from the first flip-flop 114 based on the first enable signal E1. The delay circuit 116 may additionally be configured to delay the first test signal T1 based on the configuration of the delay circuit 116 with the delay value and generate a delayed output signal DO. The delayed output signal DO may be a delayed version of the first test signal T1. In an embodiment, compared to the rest of the components of the verification circuit 102, the delay circuit 116 may be near the critical path 106 (shown by the dashed line in Figure 1 . The delay circuit 116 has been explained in detail in Figure 2 .

[0049] The second flip-flop 118:

[0050] The second flip-flop 118 may be coupled to the delay circuit 116, the clock generator 110, and the register circuit 112. Specifically, the second flip-flop 118 may be coupled to the control register 122 and the status register 124 of the register circuit 112. In an embodiment, the second flip-flop 118 may be a D flip-flop. The second flip-flop 118 may include a first input terminal, a second input terminal, a clock terminal, and an output terminal. The first input terminal of the second flip-flop 118 may be coupled to the register circuit 112 (e.g., the control register 122). The first input terminal of the second flip-flop 118 may be configured to receive a second enable signal E2 from the register circuit 112 (e.g., the control register 122). The second input terminal of the second flip-flop 118 may be coupled to the delay circuit 116. The second input terminal of the second flip-flop 118 may be configured to receive a delayed output signal DO from the delay circuit 116. The clock terminal of the second flip-flop 118 may be coupled to the clock generator 110. The clock terminal of the second flip-flop 118 may be configured to receive a first clock signal CS from the clock generator 110. Additionally, the output terminal of the second flip-flop 118 may be coupled to the status register 124. The output terminal of the second flip-flop 118 may be configured to generate a second test signal T2 and provide the second test signal T2 to the status register 124 and the comparator 120.

[0051] Comparator 120:

[0052] Comparator 120 may be coupled to control circuit 108, first flip-flop 114, and second flip-flop 118. Comparator 120 may be configured to receive a first test signal T1 and a second test signal T2 from the output terminals of first flip-flop 114 and second flip-flop 118, respectively. Comparator 120 may be further configured to compare the first test signal T1 and the second test signal T2. Comparator 120 may be further configured to generate a fault signal FS. Based on a mismatch between the first test signal T1 and the second test signal T2, the fault signal FS may switch (e.g., from a logic low state to a logic high state, or from a logic high state to a logic low state). A mismatch between the first test signal T1 and the second test signal T2 may indicate a mismatch in the data associated with the first test signal T1 and the second test signal T2. A mismatch in the data associated with the first test signal T1 and the second test signal T2 may indicate a deviation from a delay value. In an example, a mismatch in the data associated with the first test signal T1 and the second test signal T2 may occur because the first test signal T1 is a logic high signal and the second test signal T2 is a logic low signal. The deviation from the delay value may be associated with critical path 106. Additionally, the deviation from the delay value may occur due to one of the following: aging effects on critical path 106 and the impact of process variations on critical path 106. Based on a match between the first test signal T1 and the second test signal T2, the fault signal FS may remain in the same state as a previous state or a current state (e.g., a logic low state or a logic high state). Additionally, a match between the first test signal T1 and the second test signal T2 may indicate a normal delay associated with critical path 106, such that the normal delay may be within an acceptable range of the delay value. An example of an acceptable range of the delay value may be within 5 milliseconds (ms) of the delay value. In this example, the delay value may be 20 ms, and the acceptable range may be within 5 ms of the delay value. In the case of a mismatch in the data associated with the second test signal T2 and the first test signal T1, the deviation of the delay value associated with critical path 106 may be in the range of 10 ms to 30 ms, while in the case of a match between the second test signal T2 and the first test signal T1, the delay value associated with critical path 106 may be in the range of 15 ms to 25 ms. Examples of comparator 120 may include, but are not limited to, digital comparators, voltage comparators, etc.

[0053] The aging effect on the critical path 106 can be attributed to the aging effect in the electronic device 100 and can be associated with the gradual degradation of the electrical and physical characteristics of components over time, thereby affecting the performance of the electronic device 100. The aging effect can be additionally affected by environmental factors such as temperature, voltage, and the use of the electronic device 100. The process variation of the critical path 106 can refer to non-uniform deviations in the manufacturing of the electronic device 100. The non-uniform deviations can be physical damage, etc. The deviations may cause changes in the electrical and physical characteristics of the components of the electronic device 100, thereby affecting the delay associated with the critical path 106.

[0054] Status register 124:

[0055] The status register 124 can be coupled to the control circuit 108 and the second flip-flop 118. The status register 124 can be coupled to the output terminal of the second flip-flop 118. The status register 124 can be configured to receive the second test signal T2 from the output terminal of the second flip-flop 118. The status register 124 can be additionally configured to store data associated with the second test signal T2 based on receiving the second test signal T2. The status register 124 can be additionally configured to provide the second test signal T2 to the control circuit 108.

[0056] Returning to the reference control circuit 108, the control circuit 108 can be additionally configured to receive the second test signal T2 and the fault signal FS. Since the fault signal FS can switch based on a mismatch between the first test signal T1 and the second test signal T2, the switching of the fault signal FS can act as an interruption to the control circuit 108. In an example, if the current state of the fault signal FS is a logic low state, the fault signal FS can switch from the logic low state to the logic high state based on the mismatch. In another example, if the current state of the fault signal FS is a logic high state, the fault signal FS can switch from the logic high state to the logic low state based on the mismatch. The control circuit 108 can be additionally configured to transition from an active state to a safe state based on the switching of the fault signal FS and the second test signal T2. In the safe state, the electronic device 100 can perform a controlled shutdown or a reduction in the operating efficiency involving the critical path 106 to ensure that the additional operations of the electronic device 100 can remain unaffected. In the absence of the switching of the fault signal FS, the control circuit 108 can remain in the active state and can detect that the critical path 106 is operating normally. Additionally, the control circuit 108 can generate additional test data for testing an alternative critical path (not shown) of the electronic device 100.

[0057] Clock generator 110:

[0058] The clock generator 110 may include suitable circuitry that can be configured to perform one or more operations. For example, the clock generator 110 may be configured to generate a first clock signal CS. Examples of the clock generator 110 may include a crystal oscillator, a voltage-controlled crystal oscillator, a phase-locked loop clock generator, etc.

[0059] Although the electronic device 100 is shown to include a critical path 106, the scope of the present disclosure is not limited thereto. Those skilled in the art should understand that the electronic device 100 may include multiple critical paths and multiple verification circuits, and the control circuit 108 may be configured to test all such critical paths through such verification circuits.

[0060] Figure 2 A schematic block diagram of a delay circuit 116 of an electronic device 100 according to an embodiment of the present disclosure is shown. The delay circuit 116 may include a first delay unit 202 and a second delay unit 204.

[0061] First delay unit 202:

[0062] The first delay unit 202 may be coupled to the first flip-flop 114 and the control register 122 of the register circuit 112. The first delay unit 202 may be configured to receive a first setting signal S1 among a plurality of setting signals S1 - S2 from the control register 122 of the register circuit 112. The first setting signal S1 may indicate a first value of a delay value. The first delay unit 202 may be configured with the first value. The configuration of the first delay unit 202 with the first value indicates the amount of delay provided by the first delay unit 202 to the first test signal T1. The first delay unit 202 may additionally be configured to receive the first test signal T1 from the output of the first flip-flop 114. The first delay unit 202 may additionally be configured to generate a plurality of delayed test signals D1 - DN based on delaying the first test signal T1 by the first value. The first delay unit 202 may additionally be configured to output a coarse delay signal CO based on the first value. The coarse delay signal CO may include one of the first test signal T1 and the delayed test signals among the plurality of delayed test signals D1 - DN. Based on the coarse delay signal CO, the delay circuit 116 may generate a delayed output signal DO.

[0063] The first delay unit 202 may include a plurality of coarse adjustment buffers CB1 - CBN and a first programmable circuit 206. The plurality of coarse adjustment buffers CB1 - CBN may include a first coarse adjustment buffer CB1, a second coarse adjustment buffer CB2,..., and an nth coarse adjustment buffer CBN. In an embodiment, each of the plurality of coarse adjustment buffers CB1 - CBN may be a voltage buffer. Additionally, each of the plurality of coarse adjustment buffers CB1 - CBN may be a delay buffer.

[0064] Multiple coarse buffers CB1-CBN can be coupled in series. The multiple coarse buffers CB1-CBN can be configured to generate multiple delayed test signals D1-DN. For example, the multiple coarse buffers CB1-CBN can be configured to generate multiple delayed test signals D1-DN such that each coarse buffer can generate a corresponding delayed test signal. Each of the multiple delayed test signals D1-DN can be a delayed version of the first test signal T1. Additionally, each of the multiple coarse buffers CB1-CBN can include an input terminal and an output terminal.

[0065] The input terminal of the first coarse buffer CB1 can be coupled to the output terminal of the first flip-flop 114. The input terminal of the first coarse buffer CB1 can be configured to receive the first test signal T1 from the output terminal of the first flip-flop 114. Additionally, since the multiple coarse buffers CB1-CBN can be coupled in series, the input terminal of the second coarse buffer CB2 can be coupled to the output terminal of the first coarse buffer CB1. In other words, the input terminal of each remaining coarse buffer (e.g., the second to the nth coarse buffers CB2-CBN) can be coupled to the output terminal of the previous coarse buffer.

[0066] The output terminal of the first coarse buffer CB1 can be configured to generate the first delayed test signal D1 among the multiple delayed test signals D1-DN. The first delayed test signal D1 can be generated based on the first test signal T1 and the delay value of the first coarse buffer CB1. Additionally, the output terminal of each of the second to the nth coarse buffers CB2-CBN can be configured to generate a corresponding delayed test signal among the multiple delayed test signals D1-DN. Thus, the second coarse buffer CB2 can generate the second delayed test signal D2 based on the first delayed test signal D1 and the delay value of the second coarse buffer CB2. Similarly, the nth coarse buffer CBN can generate the nth delayed test signal DN. In one or more embodiments, the delay provided by each of the multiple coarse buffers CB1-CBN can be essentially the same. In another embodiment, each of the multiple coarse buffers CB1-CBN can provide an incremental delay compared to the previous coarse buffer in the series.

[0067] First programmable circuit 206:

[0068] The first programmable circuit 206 can be coupled to the first flip-flop 114, a plurality of coarse adjustment buffers CB1-CBN, and the control register 122 of the register circuit 112. The first programmable circuit 206 can be configured to output a coarse adjustment delay signal CO. In an embodiment, the first programmable circuit 206 can be a multiplexer. The first programmable circuit 206 can include a first plurality of input terminals, a first selection terminal, and an output terminal. The first programmable circuit 206 can be configured with a first value associated with a first setting signal S1 received from the control register 122 of the register circuit 112. The first value can be based on a delay value. The first programmable circuit 206 can be further configured to select, based on the first value, one of the first test signal T1 and the delayed test signals D1-DN of a plurality of delayed test signals as the coarse adjustment delay signal CO. In other words, the first value can indicate the selection of one of the first test signal T1 and one of the delayed test signals of the plurality of delayed test signals D1-DN.

[0069] The first input terminal of the first plurality of input terminals can be coupled to the output terminal of the first flip-flop 114. The first input terminal can be configured to receive the first test signal T1 from the output terminal of the first flip-flop 114. Additionally, each of the remaining input terminals of the first plurality of input terminals can be coupled to an output terminal among the first plurality of output terminals of the plurality of coarse adjustment buffers CB1-CBN. Each of the remaining input terminals of the first plurality of input terminals can be configured to receive one of the delayed test signals D1-DN of the plurality of delayed test signals. The first selection terminal can be coupled to the control register 122 of the register circuit 112. The first selection terminal can be configured to receive the first setting signal S1 from the control register 122 of the register circuit 112. The first setting signal S1 can indicate the first value. The first selection terminal can be configured to select, based on the first value, one of the first test signal T1 and the delayed test signals of the plurality of delayed test signals D1-DN. In an example, when the first value indicates zero delay, the first test signal T1 can be output as the coarse adjustment delay signal CO. In another example, based on the delay value indicated by the first value, one of the delayed test signals D1-DN of the plurality of delayed test signals can be output as the coarse adjustment delay signal CO. Additionally, the output terminal of the first programmable circuit 206 can be coupled to the second delay unit 204. The output terminal can be configured to output the coarse adjustment delay signal CO and provide the coarse adjustment delay signal CO to the second delay unit 204 based on the selection of one of the first test signal T1 and the delayed test signal.

[0070] Second delay unit 204:

[0071] The second delay unit 204 may be coupled to the first delay unit 202 and the control register 122 of the register circuit 112. The second delay unit 204 may be configured to receive a second setting signal S2 among a plurality of setting signals S1 - S2 from the control register 122 of the register circuit 112. The second setting signal S2 may indicate a second value of a delay value. The second delay unit may be configured with the second value. The second delay unit 204 may be further configured to receive a coarse - tuned delay signal CO from the first delay unit 202 (e.g., the output of the first programmable circuit 206). The second delay unit 204 may be further configured to generate a plurality of delayed coarse - tuned signals C1 - CN based on the delay of the coarse - tuned delay signal CO. The second delay unit 204 may be further configured to output a delay output signal DO. The delay output signal DO is one of the coarse - tuned delay signal CO and one of the plurality of delayed coarse - tuned signals C1 - CN. Based on the delay output signal DO, the second test signal T2 may be generated by the second flip - flop 118.

[0072] The second delay unit 204 may include a plurality of fine - tuned buffers FB1 - FBN and a second programmable circuit 208. The plurality of fine - tuned buffers FB1 - FBN may include a first fine - tuned buffer FB1, a second fine - tuned buffer FB2, …, and an nth fine - tuned buffer FBN. In an embodiment, each of the plurality of fine - tuned buffers FB1 - FBN may be a voltage buffer. Additionally, each of the plurality of fine - tuned buffers FB1 - FBN may be a delay buffer.

[0073] The plurality of fine - tuned buffers FB1 - FBN may be coupled in series. The plurality of fine - tuned buffers FB1 - FBN may be configured to generate a plurality of delayed coarse - tuned signals C1 - CN. For example, the plurality of fine - tuned buffers FB1 - FBN may be configured to generate a plurality of delayed coarse - tuned signals C1 - CN such that each fine - tuned buffer may generate a corresponding delayed coarse - tuned signal. Each of the plurality of delayed coarse - tuned signals C1 - CN may be a delayed version of the coarse - tuned delay signal CO. Additionally, each of the plurality of fine - tuned buffers FB1 - FBN may include an input terminal and an output terminal.

[0074] The input terminal of the first fine - tuned buffer FB1 may be coupled to the first delay unit 202 (e.g., the output of the first programmable circuit 206). The input terminal of the first fine - tuned buffer FB1 may be configured to receive the coarse - tuned delay signal CO from the output of the first programmable circuit 206. Additionally, the plurality of fine - tuned buffers FB1 - FBN may be coupled in series such that the input terminal of the second fine - tuned buffer FB2 may be coupled to the output terminal of the first fine - tuned buffer FB1. In other words, the input terminal of each remaining fine - tuned buffer (e.g., the second to the nth fine - tuned buffers FB2 - FBN) may be coupled to the output terminal of the previous fine - tuned buffer.

[0075] The output of the first fine-tuning buffer FB1 can be configured to generate the first delayed coarse-tuning signal C1 among the multiple delayed coarse-tuning signals C1-CN. Additionally, the output of each of the second to nth fine-tuning buffers FB2-FBN can be configured to generate the corresponding delayed coarse-tuning signal among the multiple delayed coarse-tuning signals C1-CN. Each of the multiple delayed coarse-tuning signals C1-CN can be a delayed version of the coarse-tuning delay signal CO. Thus, the second fine-tuning buffer FB2 can generate the second delayed coarse-tuning signal C2 based on the first delayed coarse-tuning signal C1 and the delay value of the second fine-tuning buffer FB2. Similarly, the nth fine-tuning buffer FBN can generate the nth delayed coarse-tuning signal CN.

[0076] In one or more embodiments, the delay provided by each of the multiple fine-tuning buffers FB1-FBN is the same. In another embodiment, the delay provided by each of the multiple fine-tuning buffers FB1-FB2 can be the same as the delay provided by each of the multiple coarse-tuning buffers CB1-CBN. In yet another embodiment, each of the multiple fine-tuning buffers FB1-FBN can provide an incremental delay compared to the previous fine-tuning buffer in series.

[0077] Second programmable circuit 208:

[0078] The second programmable circuit 208 can be coupled to the first delay unit 202, the multiple fine-tuning buffers FB1-FBN, and the register circuit 112. Specifically, the second programmable circuit 208 can be coupled to the control register 122 of the register circuit 112. In an embodiment, the second programmable circuit 208 can be a multiplexer. The second programmable circuit 208 can be configured to output a delayed output signal DO. The second programmable circuit 208 can include a second plurality of input terminals, a second selection terminal, and an output terminal. The second programmable circuit 208 can be configured with a second value associated with a second setting signal S2 received from the control register 122 of the register circuit 112. The second value can be based on the delay value. The second programmable circuit 208 can be further configured to select, based on the second value, either the coarse-tuning delay signal CO or one of the delayed coarse-tuning signals C1-CN as the delayed output signal DO. In other words, the second value can indicate the selection of either the coarse-tuning delay signal CO or one of the multiple delayed coarse-tuning signals C1-CN.

[0079] The first input terminal among the second plurality of input terminals may be coupled to a first delay unit 202 (e.g., the output terminal of the first programmable circuit 206). The first input terminal may be configured to receive a coarse delay signal CO from the output terminal of the first programmable circuit 206. Each of the remaining input terminals among the second plurality of input terminals may be coupled to an output terminal among the second plurality of output terminals. Additionally, each of the remaining input terminals among the second plurality of input terminals may be configured to receive one of the plurality of delayed coarse adjustment signals C1-CN. The second selection terminal may be coupled to the control register 122 of the register circuit 112. The second selection terminal may be configured to receive a second setting signal S2 from the control register 122. The second setting signal S2 may indicate a second value. The second selection terminal may be configured to select one of the coarse delay signal CO and the delayed coarse adjustment signal among the plurality of delayed coarse adjustment signals C1-CN. In an embodiment, the selection of the coarse delay signal CO may indicate zero delay associated with the second delay unit 204. Additionally, the output terminal of the second programmable circuit 208 may be coupled to the second flip-flop 118. The output terminal may be configured to output a delayed output signal DO and provide the delayed output signal DO to the second flip-flop 118 based on the selection of one of the coarse delay signal CO and the delayed coarse adjustment signal.

[0080] During operation:

[0081] The control circuit 108 may provide test data TD to the control register 122 of the verification circuit 102. The test data TD indicates a normal delay value that may be associated with the critical path 106. In an exemplary scenario, the delay value associated with the critical path 106 is 21 ms. The control register 122 may generate a plurality of setting signals S1-S2 based on the delay value (e.g., 21 ms). The control circuit 108 may additionally generate a first enable signal E1 and a second enable signal E2.

[0082] The input terminal of the first flip-flop 114 may receive the first enable signal E1 from the control register 122. The clock terminal of the first flip-flop 114 may receive a first clock signal CS from the clock generator 110. The output terminal of the first flip-flop 114 may generate a first test signal T1.

[0083] The first delay unit 202 of the delay circuit 116 may receive the first test signal T1 from the first flip-flop 114. The first delay unit 202 may output a coarse delay signal CO based on the first setting signal S1. The first setting signal S1 indicates a first value of the delay value.

[0084] The first delay unit 202 may include a first coarse buffer CB1, a second coarse buffer CB2, …, and an nth coarse buffer CBN connected in a series configuration such that a delay of 10 ms is introduced to the output of the previous coarse buffer. In other words, the first coarse buffer CB1 may generate a first delayed test signal D1 to introduce a 10-ms delay to the first test signal T1, the second coarse buffer CB2 may generate a second delayed test signal D2 to introduce a 20-ms delay to the first test signal T1, …, and the nth coarse buffer CBN may generate an nth delayed test signal DN to introduce a delay of N times 10 (e.g., N*10) ms to the first test signal T1.

[0085] The first plurality of input terminals of the first programmable circuit 206 may receive the first test signal T1, the first delayed test signal D1, the second delayed test signal D2, …, and the nth delayed test signal DN. Additionally, the first selection terminal may receive a first setting signal S1 from the control register 122. The first setting signal S1 may indicate a first value of the delay value (e.g., 20 ms). The first selection terminal may select the second coarse buffer CB2 based on the first setting signal S1 because the second coarse buffer CB2 delays the first test signal T1 by 20 ms to generate the second delayed test signal D2. The output terminal of the first programmable circuit 206 may output the second delayed test signal D2 as the coarse delay signal CO such that the delay generated by the first delay unit 202 is 20 ms based on the first setting signal S1.

[0086] The second delay unit 204 of the delay circuit 116 may receive the coarse delay signal CO. The second delay unit 204 may output a delay output signal DO based on a second setting signal S2. The second setting signal S2 indicates a second value of the delay value. The second delay unit 204 may include a first fine buffer FB1, a second fine buffer FB2, …, an nth fine buffer FBN connected in a series configuration such that a delay of 1 millisecond is introduced to the output of the previous fine buffer. In other words, the first fine buffer FB1 may generate a first delayed coarse signal C1 to introduce a 1-ms delay to the coarse delay signal CO, the second fine buffer FB2 may generate a second delayed coarse signal C2 to introduce a 2-ms delay to the coarse delay signal CO, …, and the nth fine buffer FBN may generate an nth delayed coarse signal CN to introduce an N-ms delay to the coarse delay signal CO.

[0087] The second plurality of input terminals of the second programmable circuit 208 may receive the coarse delay signal CO, the first delayed coarse adjustment signal C1, the second delayed coarse adjustment signal C2, …, and the nth delayed coarse adjustment signal CN. Additionally, the second selection terminal may receive a second setting signal S2 from the control register 122. The second setting signal S2 may indicate a second value of the delay value (e.g., 1 millisecond). The second selection terminal may select the first fine adjustment buffer FB1 based on the second setting signal S2, because the first fine adjustment buffer FB1 delays the coarse delay signal CO by 1 millisecond to generate the first delayed coarse adjustment signal C1. The output terminal of the second programmable circuit 208 may output the first delayed coarse adjustment signal C1 as the delayed output signal DO, such that the total delay generated by the delay circuit 116 is 21 ms.

[0088] The first input terminal of the second flip - flop 118 may receive a second enable signal E2 from the control register 122. The second input terminal of the second flip - flop 118 may receive the delayed output signal DO. The clock terminal of the second flip - flop 118 may receive a first clock signal CS from the clock generator 110. The output terminal of the second flip - flop 118 may generate a second test signal T2.

[0089] The comparator 120 may receive the first test signal T1 and the second test signal T2 from the output terminals of the first flip - flop 114 and the second flip - flop 118, respectively. The comparator 120 may generate a fault signal FS. In a certain scenario, the comparison between the first test signal T1 and the second test signal T2 indicates a match. Based on the match between the first test signal T1 and the second test signal T2, the fault signal FS may remain in the same state. Additionally, the match between the first test signal T1 and the second test signal T2 may indicate a normal delay associated with the critical path 106. The normal delay is within the acceptable range of the delay value. The delay provided by the critical path 106 may be 21 ms. The control circuit 108 may remain in an active state and may detect that the critical path 106 is operating normally. Additionally, the control circuit 108 may generate another test data for testing different critical paths (not shown) of the electronic device 100.

[0090] The status register 124 may receive the second test signal T2 from the second flip - flop 118 and store the data associated with the second test signal T2. The status register 124 may provide the second test signal T2 to the control circuit 108.

[0091] In another scenario, a comparison between a first test signal T1 and a second test signal T2 indicates a mismatch. The mismatch between the first test signal T1 (generated based on a first enable signal E1) and the second test signal T2 (generated based on a delayed output signal DO and a delay associated with test data TD) can thus indicate a deviation from the delay value associated with the critical path 106. A deviation from the delay value can occur due to at least one of the following: incorrectly configuring the first delay unit 202 with a first value or the second delay unit 204 with a second value, insufficient delay provided by at least one of the plurality of coarse-tuning buffers CB1-CBN or the plurality of fine-tuning buffers FB1-FBN, deviation from the normal operation of at least one of the first flip-flop 114, the delay circuit 116, and the second flip-flop 118, etc. The foregoing deviation causes can additionally occur due to the effects of aging and process variations. Thus, the deviation from the delay value can indicate one of the aging effects and process variations on the electronic device 100 (e.g., the critical path 106). A fault signal FS can thus be switched due to the mismatch between the first test signal T1 and the second test signal T2. In an example, the deviation from the delay value can be 15 ms. The control circuit 108 can detect the deviation from the delay value based on the switching of the fault signal FS. In an embodiment, the switching of the fault signal FS can indicate an interruption to the control circuit 108. Additionally, the control circuit 108 can transition from an active state to a safe state based on the switching of the fault signal FS and the second test signal T2. During the safe state, the electronic device 100 can perform a controlled shutdown or operate at a reduced operating efficiency involving the critical path 106 to ensure that the additional operations of the electronic device 100 remain unaffected.

[0092] Figures 3A - 3C FIG. 300 is a flowchart showing a verification method for verifying a critical path 106 of an electronic device 100 according to an embodiment of the present disclosure.

[0093] Referring Figure 3A , in step 302, the control register 122 of the register circuit 112 can receive test data TD from the control circuit 108 of the electronic device 100. The test data TD can indicate a delay value associated with the critical path 106 of the electronic device 100 under normal operating conditions. In step 304, the control register 122 of the register circuit 112 can generate a plurality of setting signals S1-S2, a first enable signal E1, and a second enable signal E2 based on the test data TD. In step 308, the first flip-flop 114 can generate a first test signal T1 based on the first enable signal E1. In step 310, the first delay unit 202 of the delay circuit 116 can generate a plurality of delayed test signals D1-DN based on the first test signal T1. Each of the plurality of delayed test signals D1-DN can be a delayed version of the first test signal T1.

[0094] Reference Figure 3B , at step 312, the first delay unit 202 of the delay circuit 116 may output a coarse delay signal CO based on the first setting signal S1 among the plurality of setting signals S1 - S2. The first setting signal S1 may indicate a first value of the delay value. The coarse delay signal CO is one of the first test signal T1 and the delayed test signals D1 - DN among the plurality of delayed test signals. Based on the coarse delay signal CO, a delayed output signal DO may be generated by the delay circuit 116. At step 314, the second delay unit 204 of the delay circuit 116 may generate a plurality of coarse signals C1 - CN by delaying the coarse delay signal CO. At step 316, the second delay unit 204 of the delay circuit 116 may output the delayed output signal DO based on the second setting signal S2 among the plurality of setting signals S1 - S2. The second setting signal S2 may indicate a second value of the delay value. At step 318, the second flip - flop 118 may generate a second test signal T2 based on the delayed output signal DO. At step 320, the comparator 120 may compare the first test signal T1 with the second test signal T2 and generate a fault signal FS. The control circuit 108 may determine the status of the test of the critical path 106 based on the fault signal FS. In one scenario, the match between the first test signal T1 and the second test signal T2 may indicate a normal delay associated with the critical path 106. The normal delay is within an acceptable range of the delay value. Based on the match between the first test signal T1 and the second test signal T2, the fault signal FS may remain in the same state. To simplify the current description of the flowchart 300, Figure 3C the mismatch between the first test signal T1 and the second test signal T2 is explained.

[0095] Reference Figure 3C , at step 322, the comparator 120 may switch the fault signal FS based on the mismatch between the first test signal T1 and the second test signal T2. The mismatch between the first test signal T1 and the second test signal T2 may indicate a mismatch of the data associated with the first test signal T1 and the second test signal T2. Additionally, the mismatch may indicate a deviation of the delay value associated with the critical path 106. At step 326, the comparator 120 may provide the switched fault signal FS to the control circuit 108. At step 328, the status register 124 of the register circuit 112 may store the data associated with the second test signal T2. At step 330, the status register 124 of the register circuit 112 may provide the second test signal T2 to the control circuit 108. Based on the switching of the fault signal FS and the reception of the second test signal T2, the control circuit 108 may transition from the active state to the safe state.

[0096] Accordingly, the technique for verifying the critical path 106 of the present disclosure implements a simple verification design by utilizing the delay circuit 116, the register circuit 112, the first flip-flop 114, and the second flip-flop 118. In addition, the verification of all critical paths of the electronic device 100 can be performed in a similar manner, and it is not necessary to utilize multiple test patterns to test a single critical path. The verification circuit 102 can additionally be capable of testing critical paths on a single IC of the electronic device 100 that are determined to be non-feasible for excitation by a conventional test circuit. In an embodiment, the electronic device 100 can include multiple critical paths that are in proximity to each other, and the verification circuit 102 can verify the critical path (e.g., the critical path 106) that provides the maximum delay among the critical paths. The verification of the critical path 106 with the maximum delay in turn verifies other critical paths of the IC. Accordingly, multiple critical paths are verified simultaneously by the verification circuit 102. In other embodiments, the electronic device 100 can include multiple verification circuits to test multiple critical paths of the electronic device 100 that are in proximity to the multiple verification circuits. The multiple verification circuits can be located on various ICs of the electronic device 100. Additionally, the verification circuit 102 can test the critical path 106 without interrupting the function of the critical path 106. Accordingly, the normal function of the electronic device 100 can remain unaffected during verification. Additionally, when the fault signal FS toggles, the electronic device 100 can transition to a safe state. In the safe state, the electronic device 100 can perform a controlled shutdown or a reduction in the operating efficiency involving the critical path 106 to ensure that the additional operations of the electronic device 100 remain unaffected. The verification circuit 102 obviates the need to write multiple test patterns to verify the critical path 106. Accordingly, the verification time for verifying the critical path 106 is reduced compared to a conventional test circuit that writes multiple test patterns for verifying a single critical path.

[0097] In an embodiment of the present disclosure, a verification circuit for an electronic device is disclosed. The verification circuit can include a register circuit and a delay circuit. The register circuit can be configured to receive test data to verify a critical path of the electronic device. The test data can indicate a delay value associated with the critical path. The register circuit can additionally be configured to generate a plurality of setting signals associated with the delay value and a first enable signal based on the test data. The delay circuit can be coupled to the register circuit. The delay circuit can be configured to receive the plurality of setting signals from the register circuit. After receiving the plurality of setting signals, the delay circuit can be configured with the delay value. The delay circuit can additionally be configured to receive a first test signal that can be generated based on the first enable signal. The delay circuit can additionally be configured to delay the first test signal based on configuring the delay circuit with the delay value to output a delayed output signal. A second test signal can be generated based on the delayed output signal, and a mismatch between the second test signal and the first test signal can indicate a deviation from the delay value associated with the critical path.

[0098] In some embodiments, the verification circuit may further include a first flip-flop, which may be coupled to a clock generator, a register circuit, and a delay circuit of the electronic device. The first flip-flop may include an input terminal, a clock terminal, and an output terminal. The input terminal may be coupled to the register circuit. The input terminal may be configured to receive a first enable signal. The clock terminal may be coupled to the clock generator. The clock terminal may be configured to receive a first clock signal. The output terminal may be coupled to the delay circuit. The output terminal may be configured to generate a first test signal.

[0099] In some embodiments, the delay circuit may include a first delay unit. The first delay unit may be coupled to the first flip-flop and the register circuit. The first delay unit may be configured to receive a first setting signal among a plurality of setting signals from the register circuit. The first setting signal may indicate a first value of a delay value, and after receiving the first setting signal, the first delay unit may be configured with the first value. The first delay unit may further be configured to receive the first test signal from the output terminal of the first flip-flop. The first delay unit may further be configured to output a coarse delay signal based on the first value. The coarse delay signal may be one of the first test signal and a delayed test signal among a plurality of delayed test signals. The plurality of delayed test signals may be generated based on the delay of the first test signal.

[0100] In some embodiments, the first delay unit may include a plurality of coarse buffers. Each of the plurality of coarse buffers includes an input terminal and an output terminal. The input terminal of the first coarse buffer among the plurality of coarse buffers may be coupled to the output terminal of the first flip-flop and may be configured to receive the first test signal. The input terminal of each of the remaining coarse buffers among the plurality of coarse buffers may be coupled to the corresponding output terminal of the previous coarse buffer among the plurality of coarse buffers. Each of the plurality of coarse buffers may be configured to generate a corresponding delayed test signal among the plurality of delayed test signals.

[0101] In some embodiments, the first delay unit may further include a first programmable circuit. The first programmable circuit may include a first plurality of input terminals, a first selection terminal, and an output terminal. A first input terminal among the first plurality of input terminals may be coupled to the output terminal of the first flip-flop. The first input terminal among the first plurality of input terminals may be configured to receive a first test signal. Each of the remaining input terminals among the first plurality of input terminals may be coupled to the output terminal of one of a plurality of coarse adjustment buffers. Each of the remaining first input terminals may be configured to receive one of a plurality of delayed test signals. The first selection terminal may be coupled to the register circuit. The first selection terminal may be configured to receive a first setting signal. The first selection terminal may further be configured to select one of the first test signal and the delayed test signal among the plurality of delayed test signals based on a first value. The output terminal may be configured to output a coarse adjustment delay signal based on the selection of one of the first test signal and the delayed test signal.

[0102] In some embodiments, the delay circuit may further include a second delay unit, which may be coupled to the first delay unit and the register circuit, and the second delay unit may be configured to receive a second setting signal among a plurality of setting signals from the register circuit. The second setting signal may indicate a second value of the delay value. After receiving the second setting signal, the second delay unit may be configured with the second value. The second delay unit may further be configured to receive the coarse adjustment delay signal from the first delay unit. The second delay unit may further be configured to output a delay output signal based on the second value. The delay output signal may be one of the coarse adjustment delay signal and a delayed coarse adjustment signal among a plurality of delayed coarse adjustment signals. The plurality of delayed coarse adjustment signals may be generated based on the delay of the coarse adjustment delay signal.

[0103] In some embodiments, the second delay unit may include a plurality of fine adjustment buffers. Each of the plurality of fine adjustment buffers includes an input terminal and an output terminal. The input terminal of the first fine adjustment buffer among the plurality of fine adjustment buffers may be coupled to the first delay unit and may be configured to receive the coarse adjustment delay signal. The input terminal of each of the remaining fine adjustment buffers among the plurality of fine adjustment buffers may be coupled to the corresponding output terminal of the previous fine adjustment buffer among the plurality of fine adjustment buffers. Each of the plurality of fine adjustment buffers may be configured to generate a corresponding delayed coarse adjustment signal among the plurality of delayed coarse adjustment signals.

[0104] In some embodiments, the second delay unit may further include a second programmable circuit. The second programmable circuit may include a second plurality of input terminals, a second selection terminal, and an output terminal. A first input terminal among the second plurality of input terminals may be coupled to the first delay unit. The first input terminal among the second plurality of input terminals may be configured to receive a coarse delay signal. Each of the remaining input terminals among the second plurality of input terminals may be coupled to an output terminal of one of the plurality of fine-tuning buffers. Each of the remaining input terminals among the second plurality of input terminals may be configured to receive one of the plurality of delayed coarse delay signals. The second selection terminal may be coupled to the register circuit. The second selection terminal may be configured to receive a second setting signal. The second selection terminal may be further configured to select one of the coarse delay signal and one of the plurality of delayed coarse delay signals based on a second value. The output terminal may be configured to output a delayed output signal based on one of the coarse delay signal and one of the plurality of delayed coarse delay signals.

[0105] In some embodiments, the register circuit may be further configured to generate a second enable signal based on test data.

[0106] In some embodiments, the verification circuit may further include a second flip-flop. The second flip-flop may be coupled to a clock generator, a register circuit, and a delay circuit of the electronic device. The second flip-flop may include a first input terminal, a second input terminal, a clock terminal, and an output terminal. The first input terminal may be coupled to the register circuit. The first input terminal may be configured to receive the second enable signal. The second input terminal may be coupled to the delay circuit. The second input terminal may be configured to receive the delayed output signal. The clock terminal may be coupled to the clock generator. The clock terminal may be configured to receive a first clock signal. The output terminal may be configured to generate a second test signal.

[0107] In some embodiments, the register circuit may include a control register coupled to the delay circuit. The control register may be configured to receive test data from a control circuit of the electronic device. The control register may be further configured to generate a first enable signal, a second enable signal, and a plurality of setting signals based on the test data.

[0108] In some embodiments, the register circuit may include a status register coupled to the second flip-flop. The status register may be configured to receive the second test signal from the second flip-flop. The status register may be further configured to store data associated with the second test signal based on receiving the second test signal.

[0109] In some embodiments, the verification circuit may further include a comparator. The comparator may be configured to receive a first test signal and a second test signal. The comparator may be further configured to compare the first test signal and the second test signal. The comparator may be further configured to generate a fault signal. The fault signal may be switched based on a mismatch between the second test signal and the first test signal.

[0110] In some embodiments, a second test signal and a fault signal may be provided to a control circuit of an electronic device, wherein a deviation from a delay value may be detected by the control circuit based on a transition of the fault signal, and the control circuit may transition from an active state to a safe state based on the fault signal and the second test signal.

[0111] In some embodiments, a match between the second test signal and the first test signal may indicate a normal delay associated with a critical path.

[0112] In some embodiments, a verification circuit may be located near the critical path.

[0113] In some embodiments, a deviation from a delay value may indicate one of the following: an aging effect on the critical path and an impact of a process variation on the critical path.

[0114] In another embodiment of the present disclosure, a verification method may be disclosed. The verification method may include receiving, by a register circuit, test data to test a critical path of an electronic device. The test data may indicate a delay value associated with the critical path. The verification method may include generating, by the register circuit, a plurality of setting signals and a first enable signal associated with the delay value based on the test data. Additionally, the verification method may include receiving, by a delay circuit, the plurality of setting signals that may indicate configuring the delay circuit with the delay value and a first test signal that may be generated based on the first enable signal. The verification method may further include delaying, by the delay circuit, the first test signal based on the delay value to output a delayed output signal. A second test signal may be generated based on the delayed output signal. A mismatch between the second test signal and the first test signal may indicate a deviation from the delay value associated with the critical path.

[0115] In some embodiments, the register circuit and the delay circuit may be included in a verification circuit of the electronic device. The verification circuit may be located near the critical path. Additionally, a deviation from a delay value may indicate one of the following: an aging effect on the critical path and an impact of a process variation on the critical path.

[0116] In some embodiments, a match between the second test signal and the first test signal may indicate that the delay value is within a normal range of the critical path.

[0117] Although various embodiments of the present disclosure have been shown and described, it should be clear that the present disclosure is not limited to these embodiments. Many modifications, alterations, variations, substitutions, and equivalents will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure as described in the claims. Additionally, unless otherwise stated, terms such as "first" and "second" are used arbitrarily to distinguish such elements described by such terms. Therefore, these terms are not necessarily intended to indicate a temporal or other prioritization of such elements.

Claims

1. A verification circuit for an electronic device, characterized in that: include: A register circuit configured to: receiving test data to verify a critical path of the electronic device, wherein the test data indicates a delay value associated with the critical path; as well as generating a plurality of set signals and a first enable signal associated with the delay value based on the test data; and a delay circuit coupled to the register circuit, wherein the delay circuit is configured to: receiving the plurality of setting signals from the register circuit, wherein upon receiving the plurality of setting signals, the delay circuit is configured with the delay value; receiving a first test signal generated based on the first enabling signal; as well as The first test signal is delayed based on configuring the delay circuit with the delay value to output a delayed output signal, wherein a second test signal is generated based on the delayed output signal, and wherein a mismatch between the second test signal and the first test signal indicates a deviation from the delay value associated with the critical path.

2. The verification circuit according to claim 1, characterized in that: The verification circuit additionally includes a first flip-flop coupled to a clock generator of the electronic device, the register circuit, and the delay circuit, and wherein the first flip-flop includes: an input terminal coupled to the register circuit, wherein the input terminal is configured to receive the first enable signal; a clock terminal coupled to the clock generator, wherein the clock terminal is configured to receive a first clock signal; and An output terminal is coupled to the delay circuit, wherein the output terminal is configured to generate the first test signal.

3. The verification circuit according to claim 2, characterized in that: The delay circuit comprises a first delay unit, wherein the first delay unit is coupled to the first flip-flop and the register circuit, and wherein the first delay unit is configured to: receiving a first setting signal of the plurality of setting signals from the register circuit, wherein the first setting signal indicates a first value of the delay value, and wherein upon receiving the first setting signal, the first delay unit is configured with the first value; receiving the first test signal from the output terminal of the first trigger; as well as A coarse delay signal is output based on the first value, wherein the coarse delay signal is one of a delayed test signal of the first test signal and a delayed test signal of a plurality of delayed test signals, and wherein the plurality of delayed test signals are generated based on a delay of the first test signal.

4. The verification circuit according to claim 3, characterized in that: The first delay unit includes a plurality of coarse adjustment buffers, wherein each of the plurality of coarse adjustment buffers includes an input terminal and an output terminal. The input terminal of a first coarse tuning buffer of the plurality of coarse tuning buffers is coupled to the output terminal of the first flip-flop and is configured to receive the first test signal, The input terminal of each remaining coarse tuning buffer of the plurality of coarse tuning buffers is coupled to a corresponding output terminal of a previous coarse tuning buffer of the plurality of coarse tuning buffers, and Each coarse tuning buffer of the plurality of coarse tuning buffers is configured to generate a corresponding delayed test signal of the plurality of delayed test signals.

5. The verification circuit according to claim 4, characterized in that: The first delay unit further comprises a first programmable circuit, and wherein the first programmable circuit comprises: a first plurality of inputs, wherein a first input of the first plurality of inputs is coupled to the output of the first flip-flop, wherein the first input of the first plurality of inputs is configured to receive the first test signal, wherein each remaining input of the first plurality of inputs is coupled to the output of one of the plurality of coarse tuning buffers, and wherein each of the remaining plurality of first inputs is configured to receive one of the plurality of delayed test signals; a first selection terminal coupled to the register circuit, wherein the first selection terminal is configured to receive the first setting signal, and wherein the first selection terminal is further configured to select one of the first test signal and the delayed test signal of the plurality of delayed test signals based on the first value; and An output terminal is configured to output the coarse delay signal based on a selection of one of the first test signal and the delayed test signal.

6. The verification circuit according to claim 3, characterized in that: The delay circuit further comprises a second delay unit coupled to the first delay unit and the register circuit, and wherein the second delay unit is configured to: receiving a second setting signal of the plurality of setting signals from the register circuit, wherein the second setting signal indicates a second value of the delay value, and wherein upon receiving the second value setting signal, the second value delay cell is configured with the second value; receiving the coarse delay signal from the first delay unit; and The delayed output signal is output based on the second value, wherein the delayed output signal is one of the coarse adjustment delay signal and a delayed coarse adjustment signal among a plurality of delayed coarse adjustment signals, and wherein the plurality of delayed coarse adjustment signals are generated based on a delay of the coarse adjustment delay signal.

7. The verification circuit according to claim 6, characterized in that: The second delay unit includes a plurality of fine adjustment buffers, wherein each of the plurality of fine adjustment buffers includes an input terminal and an output terminal. The input terminal of a first fine tuning buffer of the plurality of fine tuning buffers is coupled to the first delay unit and is configured to receive the coarse tuning delay signal, The input terminal of each remaining fine tuning buffer of the plurality of fine tuning buffers is coupled to a corresponding output terminal of a previous fine tuning buffer of the plurality of fine tuning buffers, and Each fine tune buffer of the plurality of fine tune buffers is configured to generate a corresponding delayed coarse tune signal of the plurality of delayed coarse tune signals.

8. The verification circuit according to claim 7, characterized in that: The second delay unit further comprises a second programmable circuit, and wherein the second programmable circuit comprises: a second plurality of inputs, wherein a first input of the second plurality of inputs is coupled to the first delay unit, wherein the first input of the second plurality of inputs is configured to receive the coarse delay signal, wherein each remaining input of the second plurality of inputs is coupled to the output of one of the plurality of fine buffers, and wherein each remaining input of the second plurality of inputs is configured to receive one of the plurality of delayed coarse signals; a second selection terminal coupled to the register circuit, wherein the second selection terminal is configured to receive the second setting signal, and wherein the second selection terminal is further configured to select one of the coarse adjustment delay signal and the delayed coarse adjustment signal of the plurality of delayed coarse adjustment signals based on the second value; and An output terminal is configured to output the delayed output signal based on one of the coarse adjustment delay signal and the delayed coarse adjustment signal.

9. The verification circuit according to claim 1, characterized in that: The register circuit is additionally configured to generate a second enable signal based on the test data.

10. A verification method, characterized in that: include: receiving, by a register circuit, test data to test a critical path of an electronic device, wherein the test data indicates a delay value associated with the critical path; generating, by the register circuit, a plurality of setting signals and a first enabling signal associated with the delay value based on the test data; receiving, by a delay circuit, the plurality of setting signals indicating configuration of the delay circuit with the delay value and a first test signal generated based on the first enable signal; as well as The first test signal is delayed by the delay circuit based on the delay value to output a delayed output signal, wherein a second test signal is generated based on the delayed output signal, and wherein a mismatch between the second test signal and the first test signal indicates a deviation from the delay value associated with the critical path.

Images